Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17239

1

T8

18

T12

4

T13

14

auto[1]

12650

1

T17

51

T31

22

T40

116

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3611	1			T31	21		T41	23		T85	12
values[1]	3724	1			T41	20		T168	20		T42	20
values[2]	3325	1			T31	22		T42	40		T44	74
values[3]	3900	1			T8	18		T13	14		T40	33
values[4]	4170	1			T39	12		T40	79		T41	23
values[5]	3728	1			T14	12		T17	20		T40	20
values[6]	3701	1			T17	20		T40	54		T43	16
values[7]	3730	1			T12	4		T17	58		T41	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4195	1			T17	20		T39	12		T44	169
values[1]	3077	1			T17	24		T40	31		T43	16
values[2]	2692	1			T13	14		T17	20		T31	22
values[3]	3535	1			T8	18		T17	34		T40	33
values[4]	3938	1			T41	45		T85	12		T42	20
values[5]	4425	1			T14	12		T40	23		T41	43
values[6]	4223	1			T31	21		T40	79		T41	23
values[7]	3804	1			T12	4		T40	20		T41	21

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	248	1			T210	11		T211	9		T180	13
auto[0]	values[0]	values[1]	136	1			T157	4		T159	10		T203	14
auto[0]	values[0]	values[2]	139	1			T56	12		T240	13		T189	12
auto[0]	values[0]	values[3]	227	1			T217	10		T210	9		T240	12
auto[0]	values[0]	values[4]	422	1			T85	12		T44	14		T33	17
auto[0]	values[0]	values[5]	197	1			T41	11		T22	16		T209	6
auto[0]	values[0]	values[6]	198	1			T31	12		T32	14		T33	39
auto[0]	values[0]	values[7]	223	1			T159	12		T198	23		T59	7
auto[0]	values[1]	values[0]	368	1			T27	15		T198	17		T51	13
auto[0]	values[1]	values[1]	193	1			T198	24		T56	45		T211	14
auto[0]	values[1]	values[2]	188	1			T33	6		T223	14		T241	9
auto[0]	values[1]	values[3]	252	1			T191	9		T242	15		T52	11
auto[0]	values[1]	values[4]	173	1			T41	9		T42	6		T166	15
auto[0]	values[1]	values[5]	370	1			T165	8		T203	12		T197	20
auto[0]	values[1]	values[6]	285	1			T45	11		T22	14		T198	82
auto[0]	values[1]	values[7]	509	1			T243	2		T207	12		T163	27
auto[0]	values[2]	values[0]	332	1			T44	46		T165	14		T59	27
auto[0]	values[2]	values[1]	179	1			T165	9		T209	17		T191	16
auto[0]	values[2]	values[2]	201	1			T31	9		T32	14		T166	11
auto[0]	values[2]	values[3]	170	1			T42	8		T22	7		T217	15
auto[0]	values[2]	values[4]	297	1			T32	12		T45	14		T33	19
auto[0]	values[2]	values[5]	278	1			T42	9		T33	31		T244	2
auto[0]	values[2]	values[6]	148	1			T51	16		T59	21		T223	9
auto[0]	values[2]	values[7]	289	1			T44	12		T22	20		T29	6
auto[0]	values[3]	values[0]	263	1			T166	31		T180	17		T175	8
auto[0]	values[3]	values[1]	390	1			T32	11		T165	16		T209	13
auto[0]	values[3]	values[2]	138	1			T13	14		T42	9		T32	13
auto[0]	values[3]	values[3]	254	1			T8	18		T40	27		T45	9
auto[0]	values[3]	values[4]	159	1			T163	7		T245	2		T27	16
auto[0]	values[3]	values[5]	519	1			T29	82		T211	22		T212	8
auto[0]	values[3]	values[6]	290	1			T33	16		T165	16		T56	9
auto[0]	values[3]	values[7]	233	1			T42	13		T246	12		T247	14
auto[0]	values[4]	values[0]	316	1			T39	12		T44	8		T159	6
auto[0]	values[4]	values[1]	266	1			T44	33		T32	7		T248	2
auto[0]	values[4]	values[2]	317	1			T32	13		T249	8		T163	11
auto[0]	values[4]	values[3]	446	1			T33	111		T165	15		T166	13
auto[0]	values[4]	values[4]	464	1			T32	11		T162	14		T185	10
auto[0]	values[4]	values[5]	185	1			T42	14		T44	13		T166	10
auto[0]	values[4]	values[6]	360	1			T40	9		T41	11		T32	15
auto[0]	values[4]	values[7]	176	1			T163	24		T234	16		T165	9
auto[0]	values[5]	values[0]	241	1			T166	11		T155	10		T160	18
auto[0]	values[5]	values[1]	234	1			T44	8		T32	14		T202	12
auto[0]	values[5]	values[2]	211	1			T17	11		T41	9		T56	5
auto[0]	values[5]	values[3]	338	1			T250	2		T218	16		T166	26
auto[0]	values[5]	values[4]	278	1			T41	11		T84	10		T219	12
auto[0]	values[5]	values[5]	350	1			T14	12		T251	4		T51	136
auto[0]	values[5]	values[6]	238	1			T163	14		T33	13		T22	28
auto[0]	values[5]	values[7]	357	1			T40	13		T41	13		T206	16
auto[0]	values[6]	values[0]	277	1			T17	9		T44	11		T227	14
auto[0]	values[6]	values[1]	190	1			T40	12		T155	76		T198	13
auto[0]	values[6]	values[2]	141	1			T44	14		T56	13		T223	12
auto[0]	values[6]	values[3]	297	1			T32	9		T166	10		T191	12
auto[0]	values[6]	values[4]	197	1			T191	12		T180	12		T186	10
auto[0]	values[6]	values[5]	288	1			T40	9		T27	10		T184	8
auto[0]	values[6]	values[6]	204	1			T32	9		T209	11		T252	2
auto[0]	values[6]	values[7]	341	1			T215	52		T166	11		T22	14
auto[0]	values[7]	values[0]	305	1			T44	56		T33	44		T51	12
auto[0]	values[7]	values[1]	251	1			T17	16		T191	13		T208	10
auto[0]	values[7]	values[2]	143	1			T166	11		T211	16		T52	10
auto[0]	values[7]	values[3]	231	1			T17	11		T44	12		T163	11
auto[0]	values[7]	values[4]	376	1			T191	27		T240	10		T253	2
auto[0]	values[7]	values[5]	319	1			T41	9		T254	2		T185	11
auto[0]	values[7]	values[6]	474	1			T255	2		T155	209		T29	46
auto[0]	values[7]	values[7]	160	1			T12	4		T42	13		T165	10
auto[1]	values[0]	values[0]	308	1			T210	17		T211	11		T180	13
auto[1]	values[0]	values[1]	143	1			T159	10		T203	6		T256	13
auto[1]	values[0]	values[2]	162	1			T56	8		T240	7		T189	69
auto[1]	values[0]	values[3]	167	1			T217	16		T210	26		T240	8
auto[1]	values[0]	values[4]	318	1			T44	6		T33	9		T164	14
auto[1]	values[0]	values[5]	330	1			T41	12		T183	18		T22	7
auto[1]	values[0]	values[6]	183	1			T31	9		T32	6		T33	7
auto[1]	values[0]	values[7]	210	1			T159	8		T198	23		T59	13
auto[1]	values[1]	values[0]	303	1			T257	18		T27	6		T198	3
auto[1]	values[1]	values[1]	82	1			T198	3		T56	9		T211	6
auto[1]	values[1]	values[2]	209	1			T33	14		T223	6		T241	11
auto[1]	values[1]	values[3]	164	1			T191	13		T242	5		T52	10
auto[1]	values[1]	values[4]	174	1			T41	11		T42	14		T166	22
auto[1]	values[1]	values[5]	227	1			T168	20		T165	12		T203	8
auto[1]	values[1]	values[6]	123	1			T45	9		T22	6		T198	5
auto[1]	values[1]	values[7]	104	1			T163	9		T33	6		T192	14
auto[1]	values[2]	values[0]	178	1			T44	8		T258	12		T165	6
auto[1]	values[2]	values[1]	173	1			T165	15		T209	10		T191	10
auto[1]	values[2]	values[2]	125	1			T31	13		T32	6		T166	9
auto[1]	values[2]	values[3]	169	1			T42	12		T22	17		T217	5
auto[1]	values[2]	values[4]	183	1			T32	8		T45	7		T33	29
auto[1]	values[2]	values[5]	161	1			T42	11		T33	5		T166	33
auto[1]	values[2]	values[6]	158	1			T51	4		T59	19		T223	13
auto[1]	values[2]	values[7]	284	1			T44	8		T22	9		T29	14
auto[1]	values[3]	values[0]	164	1			T166	14		T180	10		T186	10
auto[1]	values[3]	values[1]	144	1			T32	9		T165	4		T209	9
auto[1]	values[3]	values[2]	154	1			T42	11		T32	7		T33	70
auto[1]	values[3]	values[3]	135	1			T40	6		T45	11		T127	44
auto[1]	values[3]	values[4]	106	1			T226	20		T163	18		T27	5
auto[1]	values[3]	values[5]	379	1			T259	12		T29	17		T260	18
auto[1]	values[3]	values[6]	390	1			T33	66		T165	4		T56	40
auto[1]	values[3]	values[7]	182	1			T42	7		T59	9		T180	14
auto[1]	values[4]	values[0]	222	1			T44	12		T159	14		T238	4
auto[1]	values[4]	values[1]	184	1			T44	5		T32	13		T180	8
auto[1]	values[4]	values[2]	185	1			T32	7		T163	22		T22	10
auto[1]	values[4]	values[3]	149	1			T33	18		T165	11		T166	7
auto[1]	values[4]	values[4]	154	1			T32	9		T185	10		T217	6
auto[1]	values[4]	values[5]	111	1			T42	6		T44	7		T166	10
auto[1]	values[4]	values[6]	471	1			T40	70		T41	12		T32	5
auto[1]	values[4]	values[7]	164	1			T163	53		T165	13		T29	13
auto[1]	values[5]	values[0]	138	1			T166	16		T155	10		T56	9
auto[1]	values[5]	values[1]	147	1			T44	12		T32	6		T22	14
auto[1]	values[5]	values[2]	143	1			T17	9		T41	11		T56	45
auto[1]	values[5]	values[3]	214	1			T236	10		T166	7		T198	14
auto[1]	values[5]	values[4]	227	1			T41	14		T165	23		T51	6
auto[1]	values[5]	values[5]	188	1			T51	6		T210	18		T261	7
auto[1]	values[5]	values[6]	167	1			T163	6		T33	20		T22	11
auto[1]	values[5]	values[7]	257	1			T40	7		T41	8		T29	89
auto[1]	values[6]	values[0]	239	1			T17	11		T44	9		T211	12
auto[1]	values[6]	values[1]	188	1			T40	19		T43	16		T155	10
auto[1]	values[6]	values[2]	114	1			T44	6		T56	7		T223	8
auto[1]	values[6]	values[3]	149	1			T32	11		T166	10		T262	2
auto[1]	values[6]	values[4]	171	1			T191	8		T180	8		T186	10
auto[1]	values[6]	values[5]	364	1			T40	14		T27	10		T223	9
auto[1]	values[6]	values[6]	334	1			T32	11		T209	9		T220	47
auto[1]	values[6]	values[7]	207	1			T46	24		T166	9		T22	6
auto[1]	values[7]	values[0]	293	1			T44	19		T33	10		T51	15
auto[1]	values[7]	values[1]	177	1			T17	8		T191	11		T208	10
auto[1]	values[7]	values[2]	122	1			T166	64		T211	4		T52	11
auto[1]	values[7]	values[3]	173	1			T17	23		T44	26		T163	9
auto[1]	values[7]	values[4]	239	1			T191	21		T240	10		T263	12
auto[1]	values[7]	values[5]	159	1			T41	11		T185	9		T191	7
auto[1]	values[7]	values[6]	200	1			T155	9		T264	4		T29	73
auto[1]	values[7]	values[7]	108	1			T42	7		T165	11		T27	13