Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14839

1

T8

9

T12

2

T13

7

auto[1]

45577

1

T2

270

T3

127

T6

287

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1206	1			T2	9		T3	3		T6	1
auto[4:7]	25282	1			T2	73		T3	57		T6	95
auto[8:11]	1267	1			T2	1		T3	1		T6	5
auto[12:15]	352	1			T3	1		T6	3		T10	1
auto[16:19]	307	1			T2	1		T6	1		T10	1
auto[20:23]	1875	1			T2	15		T3	5		T6	9
auto[24:27]	328	1			T2	2		T6	2		T10	8
auto[28:31]	318	1			T6	1		T10	1		T17	1
auto[32:35]	289	1			T6	2		T10	3		T16	1
auto[36:39]	301	1			T2	1		T3	1		T6	6
auto[40:43]	333	1			T2	1		T3	1		T6	1
auto[44:47]	352	1			T2	1		T3	2		T6	4
auto[48:51]	340	1			T2	3		T6	12		T10	3
auto[52:55]	1849	1			T2	9		T3	1		T6	10
auto[56:59]	1252	1			T2	5		T3	1		T6	3
auto[60:63]	347	1			T2	1		T6	2		T10	6
auto[64:67]	304	1			T2	1		T3	4		T6	1
auto[68:71]	299	1			T10	4		T17	4		T50	1
auto[72:75]	358	1			T2	4		T6	3		T10	1
auto[76:79]	333	1			T2	2		T3	2		T6	3
auto[80:83]	319	1			T2	3		T3	1		T6	5
auto[84:87]	373	1			T2	3		T6	2		T10	1
auto[88:91]	1834	1			T2	11		T6	4		T8	6
auto[92:95]	346	1			T2	8		T3	1		T6	1
auto[96:99]	321	1			T10	5		T31	2		T40	3
auto[100:103]	300	1			T3	1		T6	4		T17	1
auto[104:107]	1296	1			T2	8		T3	1		T6	3
auto[108:111]	328	1			T3	6		T6	2		T10	2
auto[112:115]	343	1			T2	1		T3	1		T6	5
auto[116:119]	300	1			T6	1		T10	2		T17	2
auto[120:123]	315	1			T2	2		T6	3		T10	4
auto[124:127]	320	1			T3	1		T6	4		T10	7
auto[128:131]	329	1			T3	1		T10	1		T16	1
auto[132:135]	338	1			T2	5		T6	2		T10	6
auto[136:139]	316	1			T2	2		T10	1		T40	3
auto[140:143]	346	1			T2	2		T6	2		T10	3
auto[144:147]	364	1			T2	1		T6	3		T10	1
auto[148:151]	341	1			T2	1		T6	1		T10	1
auto[152:155]	309	1			T6	3		T10	7		T144	1
auto[156:159]	1850	1			T2	10		T3	5		T6	8
auto[160:163]	294	1			T2	2		T3	3		T6	1
auto[164:167]	280	1			T2	2		T3	5		T6	5
auto[168:171]	301	1			T2	3		T3	3		T6	2
auto[172:175]	304	1			T2	2		T6	1		T13	2
auto[176:179]	374	1			T2	5		T6	6		T10	5
auto[180:183]	1843	1			T2	13		T3	1		T6	12
auto[184:187]	1227	1			T2	3		T3	4		T6	7
auto[188:191]	309	1			T3	1		T6	1		T8	2
auto[192:195]	377	1			T2	3		T6	2		T10	1
auto[196:199]	314	1			T2	1		T10	8		T31	1
auto[200:203]	318	1			T2	1		T10	6		T31	1
auto[204:207]	284	1			T6	2		T10	5		T50	7
auto[208:211]	309	1			T2	3		T3	1		T10	5
auto[212:215]	291	1			T2	5		T6	1		T10	5
auto[216:219]	363	1			T2	3		T6	4		T10	3
auto[220:223]	269	1			T2	6		T6	1		T10	2
auto[224:227]	291	1			T2	1		T6	1		T10	3
auto[228:231]	312	1			T2	1		T3	1		T6	4
auto[232:235]	2816	1			T2	15		T3	7		T6	14
auto[236:239]	365	1			T2	5		T6	1		T10	4
auto[240:243]	305	1			T2	5		T6	4		T10	2
auto[244:247]	365	1			T2	2		T6	1		T10	5
auto[248:251]	299	1			T3	2		T10	5		T16	1
auto[252:255]	326	1			T2	3		T3	2		T10	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	408	1			T8	1		T12	1		T14	2
auto[0:3]	auto[1]	798	1			T2	9		T3	3		T6	1
auto[4:7]	auto[0]	5698	1			T12	1		T17	3		T31	5
auto[4:7]	auto[1]	19584	1			T2	73		T3	57		T6	95
auto[8:11]	auto[0]	453	1			T17	3		T31	1		T40	2
auto[8:11]	auto[1]	814	1			T2	1		T3	1		T6	5
auto[12:15]	auto[0]	66	1			T13	2		T164	1		T183	2
auto[12:15]	auto[1]	286	1			T3	1		T6	3		T10	1
auto[16:19]	auto[0]	61	1			T41	1		T44	2		T32	2
auto[16:19]	auto[1]	246	1			T2	1		T6	1		T10	1
auto[20:23]	auto[0]	447	1			T8	1		T13	1		T17	2
auto[20:23]	auto[1]	1428	1			T2	15		T3	5		T6	9
auto[24:27]	auto[0]	70	1			T44	1		T32	1		T163	1
auto[24:27]	auto[1]	258	1			T2	2		T6	2		T10	8
auto[28:31]	auto[0]	69	1			T17	1		T41	1		T42	2
auto[28:31]	auto[1]	249	1			T6	1		T10	1		T50	3
auto[32:35]	auto[0]	50	1			T17	1		T22	1		T159	1
auto[32:35]	auto[1]	239	1			T6	2		T10	3		T16	1
auto[36:39]	auto[0]	81	1			T40	1		T41	1		T43	1
auto[36:39]	auto[1]	220	1			T2	1		T3	1		T6	6
auto[40:43]	auto[0]	72	1			T17	4		T226	1		T33	1
auto[40:43]	auto[1]	261	1			T2	1		T3	1		T6	1
auto[44:47]	auto[0]	84	1			T43	1		T85	2		T44	2
auto[44:47]	auto[1]	268	1			T2	1		T3	2		T6	4
auto[48:51]	auto[0]	86	1			T42	1		T44	1		T32	1
auto[48:51]	auto[1]	254	1			T2	3		T6	12		T10	3
auto[52:55]	auto[0]	421	1			T17	2		T41	4		T42	5
auto[52:55]	auto[1]	1428	1			T2	9		T3	1		T6	10
auto[56:59]	auto[0]	425	1			T14	2		T17	2		T41	4
auto[56:59]	auto[1]	827	1			T2	5		T3	1		T6	3
auto[60:63]	auto[0]	74	1			T42	1		T32	1		T163	1
auto[60:63]	auto[1]	273	1			T2	1		T6	2		T10	6
auto[64:67]	auto[0]	80	1			T42	1		T44	1		T45	1
auto[64:67]	auto[1]	224	1			T2	1		T3	4		T6	1
auto[68:71]	auto[0]	71	1			T17	2		T44	1		T257	1
auto[68:71]	auto[1]	228	1			T10	4		T17	2		T50	1
auto[72:75]	auto[0]	74	1			T32	4		T45	1		T162	1
auto[72:75]	auto[1]	284	1			T2	4		T6	3		T10	1
auto[76:79]	auto[0]	99	1			T31	4		T42	1		T44	1
auto[76:79]	auto[1]	234	1			T2	2		T3	2		T6	3
auto[80:83]	auto[0]	75	1			T40	1		T42	1		T32	3
auto[80:83]	auto[1]	244	1			T2	3		T3	1		T6	5
auto[84:87]	auto[0]	83	1			T41	1		T44	1		T163	1
auto[84:87]	auto[1]	290	1			T2	3		T6	2		T10	1
auto[88:91]	auto[0]	469	1			T8	3		T13	1		T17	2
auto[88:91]	auto[1]	1365	1			T2	11		T6	4		T8	3
auto[92:95]	auto[0]	88	1			T8	1		T33	1		T258	1
auto[92:95]	auto[1]	258	1			T2	8		T3	1		T6	1
auto[96:99]	auto[0]	76	1			T31	2		T40	3		T32	1
auto[96:99]	auto[1]	245	1			T10	5		T144	5		T167	2
auto[100:103]	auto[0]	62	1			T17	1		T40	2		T32	1
auto[100:103]	auto[1]	238	1			T3	1		T6	4		T31	1
auto[104:107]	auto[0]	483	1			T8	2		T14	1		T17	1
auto[104:107]	auto[1]	813	1			T2	8		T3	1		T6	3
auto[108:111]	auto[0]	85	1			T17	2		T41	4		T32	1
auto[108:111]	auto[1]	243	1			T3	6		T6	2		T10	2
auto[112:115]	auto[0]	54	1			T41	2		T42	2		T164	1
auto[112:115]	auto[1]	289	1			T2	1		T3	1		T6	5
auto[116:119]	auto[0]	74	1			T17	2		T40	2		T32	2
auto[116:119]	auto[1]	226	1			T6	1		T10	2		T40	1
auto[120:123]	auto[0]	56	1			T17	2		T226	1		T166	1
auto[120:123]	auto[1]	259	1			T2	2		T6	3		T10	4
auto[124:127]	auto[0]	76	1			T17	1		T40	1		T42	1
auto[124:127]	auto[1]	244	1			T3	1		T6	4		T10	7
auto[128:131]	auto[0]	77	1			T42	1		T32	2		T163	4
auto[128:131]	auto[1]	252	1			T3	1		T10	1		T16	1
auto[132:135]	auto[0]	78	1			T31	1		T40	1		T41	3
auto[132:135]	auto[1]	260	1			T2	5		T6	2		T10	6
auto[136:139]	auto[0]	79	1			T40	3		T42	4		T32	4
auto[136:139]	auto[1]	237	1			T2	2		T10	1		T50	1
auto[140:143]	auto[0]	76	1			T17	3		T43	1		T168	2
auto[140:143]	auto[1]	270	1			T2	2		T6	2		T10	3
auto[144:147]	auto[0]	82	1			T32	2		T45	2		T33	1
auto[144:147]	auto[1]	282	1			T2	1		T6	3		T10	1
auto[148:151]	auto[0]	93	1			T41	1		T42	2		T44	3
auto[148:151]	auto[1]	248	1			T2	1		T6	1		T10	1
auto[152:155]	auto[0]	72	1			T33	1		T165	1		T166	6
auto[152:155]	auto[1]	237	1			T6	3		T10	7		T144	1
auto[156:159]	auto[0]	437	1			T17	2		T40	2		T41	1
auto[156:159]	auto[1]	1413	1			T2	10		T3	5		T6	8
auto[160:163]	auto[0]	76	1			T40	1		T41	2		T32	2
auto[160:163]	auto[1]	218	1			T2	2		T3	3		T6	1
auto[164:167]	auto[0]	56	1			T41	1		T168	2		T42	2
auto[164:167]	auto[1]	224	1			T2	2		T3	5		T6	5
auto[168:171]	auto[0]	68	1			T42	1		T257	1		T163	1
auto[168:171]	auto[1]	233	1			T2	3		T3	3		T6	2
auto[172:175]	auto[0]	81	1			T13	1		T40	4		T32	1
auto[172:175]	auto[1]	223	1			T2	2		T6	1		T13	1
auto[176:179]	auto[0]	104	1			T17	1		T32	4		T165	4
auto[176:179]	auto[1]	270	1			T2	5		T6	6		T10	5
auto[180:183]	auto[0]	415	1			T40	2		T41	2		T42	3
auto[180:183]	auto[1]	1428	1			T2	13		T3	1		T6	12
auto[184:187]	auto[0]	450	1			T14	1		T17	1		T31	1
auto[184:187]	auto[1]	777	1			T2	3		T3	4		T6	7
auto[188:191]	auto[0]	90	1			T8	1		T40	4		T32	1
auto[188:191]	auto[1]	219	1			T3	1		T6	1		T8	1
auto[192:195]	auto[0]	99	1			T40	2		T168	1		T42	3
auto[192:195]	auto[1]	278	1			T2	3		T6	2		T10	1
auto[196:199]	auto[0]	67	1			T31	1		T32	1		T163	3
auto[196:199]	auto[1]	247	1			T2	1		T10	8		T50	1
auto[200:203]	auto[0]	69	1			T31	1		T40	1		T44	2
auto[200:203]	auto[1]	249	1			T2	1		T10	6		T50	4
auto[204:207]	auto[0]	68	1			T42	2		T165	2		T265	1
auto[204:207]	auto[1]	216	1			T6	2		T10	5		T50	7
auto[208:211]	auto[0]	66	1			T32	3		T246	1		T185	3
auto[208:211]	auto[1]	243	1			T2	3		T3	1		T10	5
auto[212:215]	auto[0]	70	1			T40	1		T44	1		T165	4
auto[212:215]	auto[1]	221	1			T2	5		T6	1		T10	5
auto[216:219]	auto[0]	94	1			T85	1		T42	2		T45	1
auto[216:219]	auto[1]	269	1			T2	3		T6	4		T10	3
auto[220:223]	auto[0]	58	1			T41	1		T44	1		T32	1
auto[220:223]	auto[1]	211	1			T2	6		T6	1		T10	2
auto[224:227]	auto[0]	68	1			T44	1		T163	1		T33	2
auto[224:227]	auto[1]	223	1			T2	1		T6	1		T10	3
auto[228:231]	auto[0]	67	1			T41	1		T42	2		T32	1
auto[228:231]	auto[1]	245	1			T2	1		T3	1		T6	4
auto[232:235]	auto[0]	876	1			T17	2		T31	2		T40	3
auto[232:235]	auto[1]	1940	1			T2	15		T3	7		T6	14
auto[236:239]	auto[0]	74	1			T13	1		T45	1		T246	1
auto[236:239]	auto[1]	291	1			T2	5		T6	1		T10	4
auto[240:243]	auto[0]	74	1			T45	2		T33	1		T155	1
auto[240:243]	auto[1]	231	1			T2	5		T6	4		T10	2
auto[244:247]	auto[0]	77	1			T13	1		T163	3		T22	3
auto[244:247]	auto[1]	288	1			T2	2		T6	1		T10	5
auto[248:251]	auto[0]	58	1			T32	2		T162	1		T202	1
auto[248:251]	auto[1]	241	1			T3	2		T10	5		T16	1
auto[252:255]	auto[0]	50	1			T40	1		T44	2		T32	2
auto[252:255]	auto[1]	276	1			T2	3		T3	2		T10	2