Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	424	1			T14	4		T17	1		T40	1
auto[ReadAddrCrossIntoMailbox]	272	1			T14	2		T40	1		T42	3
auto[ReadAddrCrossOutOfMailbox]	276	1			T14	4		T17	1		T40	3
auto[ReadAddrCrossAllMailbox]	187	1			T44	1		T32	2		T45	1
auto[ReadAddrOutsideMailbox]	3432	1			T8	6		T12	2		T14	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2347

1

T8

3

T12

1

T14

6

auto[1]

2244

1

T8

3

T12

1

T14

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	720	1			T8	2		T12	2		T14	4
read_ops[0x0b]	766	1			T17	6		T31	1		T40	1
read_ops[0x3b]	744	1			T14	4		T17	4		T40	2
read_ops[0x6b]	784	1			T8	4		T14	2		T17	1
read_ops[0xbb]	751	1			T14	2		T17	1		T31	1
read_ops[0xeb]	826	1			T17	3		T31	2		T40	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T14	1		T32	1		T256	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T14	1		T22	1		T217	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T251	1		T166	1		T27	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T163	1		T33	2		T251	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T32	1		T251	1		T165	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T33	1		T251	1		T198	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T44	1		T165	1		T223	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T33	1		T22	2		T51	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T8	1		T12	1		T14	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T8	1		T12	1		T14	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T17	1		T218	2		T166	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T42	1		T33	1		T218	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T51	2		T59	1		T153	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T42	1		T33	1		T185	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T42	1		T191	1		T266	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T163	1		T33	1		T166	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T51	1		T266	1		T211	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T240	1		T180	1		T212	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T17	2		T31	1		T40	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T17	3		T41	2		T43	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T14	1		T234	1		T218	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T14	1		T33	1		T234	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T42	1		T254	1		T267	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T33	1		T254	1		T209	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T14	1		T59	1		T267	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T14	1		T44	1		T33	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T32	1		T166	1		T240	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T32	1		T29	1		T210	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T17	2		T41	4		T207	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T17	2		T40	2		T41	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T42	1		T33	1		T234	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T234	1		T218	1		T22	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T40	1		T33	1		T198	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T29	1		T268	1		T191	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T14	1		T40	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T14	1		T44	1		T22	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T163	1		T33	1		T22	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T22	1		T29	1		T211	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T8	2		T17	1		T40	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T8	2		T31	2		T40	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T40	1		T234	2		T165	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T44	1		T234	2		T29	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T14	1		T42	1		T33	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T14	1		T165	1		T166	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T17	1		T40	2		T32	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T198	1		T59	1		T232	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T45	1		T165	1		T166	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T163	1		T166	1		T191	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T40	1		T41	4		T85	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	264	1			T31	1		T40	1		T41	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T42	1		T234	1		T218	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T44	1		T32	1		T234	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T166	1		T198	1		T223	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T165	1		T266	1		T240	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T33	3		T191	1		T256	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T44	1		T32	1		T59	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T163	2		T241	1		T204	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T33	1		T159	1		T266	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	315	1			T31	2		T40	2		T41	6
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T17	3		T41	1		T168	1