Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3641	1			T17	34		T42	20		T44	40
values[1]	4141	1			T39	12		T31	22		T40	20
values[2]	4333	1			T40	31		T41	23		T168	20
values[3]	3400	1			T13	14		T17	24		T40	79
values[4]	3564	1			T8	18		T17	20		T42	20
values[5]	4099	1			T12	4		T40	33		T85	12
values[6]	2955	1			T14	12		T41	46		T42	20
values[7]	3756	1			T17	20		T31	21		T40	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3511	1			T17	20		T40	79		T41	23
values[1]	4377	1			T17	24		T40	20		T42	80
values[2]	4160	1			T42	20		T207	12		T32	40
values[3]	3514	1			T31	43		T85	12		T44	20
values[4]	3507	1			T39	12		T40	54		T41	45
values[5]	3753	1			T8	18		T41	43		T42	40
values[6]	3224	1			T13	14		T14	12		T17	34
values[7]	3843	1			T12	4		T17	20		T40	33

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29113

1

T8

18

T12

4

T13

14

auto[1]

776

1

T17

6

T31

2

T40

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	387	1			T45	21		T165	19		T59	17
auto[0]	values[0]	values[1]	824	1			T44	20		T246	12		T165	40
auto[0]	values[0]	values[2]	373	1			T163	32		T84	10		T22	36
auto[0]	values[0]	values[3]	481	1			T163	82		T198	80		T191	24
auto[0]	values[0]	values[4]	265	1			T192	14		T238	4		T256	103
auto[0]	values[0]	values[5]	302	1			T42	20		T44	20		T269	10
auto[0]	values[0]	values[6]	427	1			T17	32		T51	47		T240	20
auto[0]	values[0]	values[7]	468	1			T255	2		T191	34		T241	39
auto[0]	values[1]	values[0]	369	1			T41	22		T32	17		T33	20
auto[0]	values[1]	values[1]	651	1			T40	20		T22	44		T209	22
auto[0]	values[1]	values[2]	593	1			T165	20		T160	18		T217	19
auto[0]	values[1]	values[3]	540	1			T31	21		T159	18		T209	19
auto[0]	values[1]	values[4]	665	1			T39	12		T44	38		T249	8
auto[0]	values[1]	values[5]	478	1			T185	20		T29	42		T56	20
auto[0]	values[1]	values[6]	345	1			T250	2		T166	20		T266	20
auto[0]	values[1]	values[7]	395	1			T259	12		T209	20		T59	20
auto[0]	values[2]	values[0]	636	1			T168	20		T163	36		T159	19
auto[0]	values[2]	values[1]	624	1			T42	34		T33	82		T27	21
auto[0]	values[2]	values[2]	635	1			T163	20		T51	141		T59	20
auto[0]	values[2]	values[3]	675	1			T45	20		T166	20		T22	29
auto[0]	values[2]	values[4]	282	1			T40	30		T22	34		T198	20
auto[0]	values[2]	values[5]	525	1			T41	23		T33	100		T166	18
auto[0]	values[2]	values[6]	645	1			T32	19		T165	20		T56	50
auto[0]	values[2]	values[7]	221	1			T32	17		T166	27		T191	20
auto[0]	values[3]	values[0]	465	1			T40	79		T234	16		T166	27
auto[0]	values[3]	values[1]	419	1			T17	24		T162	14		T166	45
auto[0]	values[3]	values[2]	566	1			T247	14		T29	29		T266	20
auto[0]	values[3]	values[3]	498	1			T33	20		T22	22		T155	48
auto[0]	values[3]	values[4]	372	1			T180	20		T270	4		T220	43
auto[0]	values[3]	values[5]	245	1			T42	20		T46	20		T190	14
auto[0]	values[3]	values[6]	344	1			T13	14		T209	20		T191	25
auto[0]	values[3]	values[7]	410	1			T245	2		T59	20		T223	22
auto[0]	values[4]	values[0]	574	1			T17	17		T44	20		T271	4
auto[0]	values[4]	values[1]	462	1			T42	19		T44	19		T206	16
auto[0]	values[4]	values[2]	399	1			T32	19		T163	20		T191	23
auto[0]	values[4]	values[3]	294	1			T32	20		T218	16		T165	25
auto[0]	values[4]	values[4]	278	1			T32	18		T51	42		T262	2
auto[0]	values[4]	values[5]	405	1			T8	18		T44	38		T166	75
auto[0]	values[4]	values[6]	534	1			T258	10		T219	12		T165	21
auto[0]	values[4]	values[7]	523	1			T32	20		T166	22		T155	20
auto[0]	values[5]	values[0]	394	1			T236	10		T29	21		T272	2
auto[0]	values[5]	values[1]	278	1			T42	19		T32	19		T22	20
auto[0]	values[5]	values[2]	603	1			T207	12		T32	18		T226	20
auto[0]	values[5]	values[3]	369	1			T85	12		T32	20		T244	2
auto[0]	values[5]	values[4]	649	1			T223	20		T240	18		T211	19
auto[0]	values[5]	values[5]	858	1			T44	55		T32	20		T257	18
auto[0]	values[5]	values[6]	386	1			T44	54		T33	45		T254	2
auto[0]	values[5]	values[7]	451	1			T12	4		T40	31		T243	2
auto[0]	values[6]	values[0]	264	1			T33	77		T223	23		T208	20
auto[0]	values[6]	values[1]	523	1			T33	35		T166	36		T178	8
auto[0]	values[6]	values[2]	398	1			T42	19		T163	20		T159	20
auto[0]	values[6]	values[3]	245	1			T33	82		T251	4		T273	6
auto[0]	values[6]	values[4]	423	1			T41	25		T248	2		T22	20
auto[0]	values[6]	values[5]	289	1			T29	20		T208	20		T186	30
auto[0]	values[6]	values[6]	285	1			T14	12		T41	21		T29	19
auto[0]	values[6]	values[7]	454	1			T203	20		T274	12		T186	33
auto[0]	values[7]	values[0]	329	1			T44	18		T27	20		T191	18
auto[0]	values[7]	values[1]	502	1			T33	57		T166	19		T227	14
auto[0]	values[7]	values[2]	495	1			T45	16		T155	86		T197	20
auto[0]	values[7]	values[3]	295	1			T31	20		T44	20		T22	20
auto[0]	values[7]	values[4]	504	1			T40	23		T41	20		T33	20
auto[0]	values[7]	values[5]	555	1			T41	20		T44	20		T32	20
auto[0]	values[7]	values[6]	181	1			T28	26		T204	20		T208	20
auto[0]	values[7]	values[7]	789	1			T17	19		T41	20		T43	14
auto[1]	values[0]	values[0]	9	1			T165	1		T59	3		T127	1
auto[1]	values[0]	values[1]	10	1			T185	2		T198	1		T51	1
auto[1]	values[0]	values[2]	18	1			T163	1		T22	3		T186	4
auto[1]	values[0]	values[3]	29	1			T198	7		T191	2		T52	4
auto[1]	values[0]	values[4]	6	1			T256	1		T275	3		T276	1
auto[1]	values[0]	values[5]	6	1			T189	2		T277	2		T278	1
auto[1]	values[0]	values[6]	18	1			T17	2		T153	1		T279	2
auto[1]	values[0]	values[7]	18	1			T241	3		T280	4		T235	2
auto[1]	values[1]	values[0]	12	1			T41	1		T32	3		T164	2
auto[1]	values[1]	values[1]	9	1			T22	2		T52	2		T263	1
auto[1]	values[1]	values[2]	10	1			T165	4		T217	1		T52	1
auto[1]	values[1]	values[3]	33	1			T31	1		T159	2		T209	2
auto[1]	values[1]	values[4]	6	1			T155	3		T263	1		T281	2
auto[1]	values[1]	values[5]	15	1			T29	2		T223	6		T241	1
auto[1]	values[1]	values[6]	9	1			T212	1		T52	3		T151	2
auto[1]	values[1]	values[7]	11	1			T242	3		T186	1		T189	2
auto[1]	values[2]	values[0]	14	1			T159	1		T180	3		T153	1
auto[1]	values[2]	values[1]	13	1			T42	6		T59	1		T52	2
auto[1]	values[2]	values[2]	7	1			T51	1		T256	2		T208	1
auto[1]	values[2]	values[3]	15	1			T180	1		T151	4		T263	1
auto[1]	values[2]	values[4]	4	1			T40	1		T22	1		T116	2
auto[1]	values[2]	values[5]	12	1			T33	3		T166	2		T159	1
auto[1]	values[2]	values[6]	11	1			T32	1		T180	1		T189	3
auto[1]	values[2]	values[7]	14	1			T32	3		T166	6		T52	1
auto[1]	values[3]	values[0]	6	1			T128	1		T278	1		T282	3
auto[1]	values[3]	values[1]	10	1			T198	1		T127	2		T200	3
auto[1]	values[3]	values[2]	15	1			T180	4		T116	2		T283	3
auto[1]	values[3]	values[3]	9	1			T155	1		T189	2		T128	3
auto[1]	values[3]	values[4]	7	1			T220	2		T200	3		T278	1
auto[1]	values[3]	values[5]	9	1			T46	4		T211	2		T284	3
auto[1]	values[3]	values[6]	13	1			T191	1		T240	1		T153	3
auto[1]	values[3]	values[7]	12	1			T223	1		T285	4		T235	1
auto[1]	values[4]	values[0]	18	1			T17	3		T56	1		T220	1
auto[1]	values[4]	values[1]	11	1			T42	1		T44	1		T217	3
auto[1]	values[4]	values[2]	10	1			T32	1		T191	3		T212	1
auto[1]	values[4]	values[3]	10	1			T165	1		T203	1		T51	2
auto[1]	values[4]	values[4]	8	1			T32	2		T51	1		T210	2
auto[1]	values[4]	values[5]	8	1			T198	3		T56	1		T222	2
auto[1]	values[4]	values[6]	11	1			T258	2		T29	1		T191	1
auto[1]	values[4]	values[7]	19	1			T29	2		T153	2		T275	2
auto[1]	values[5]	values[0]	12	1			T29	1		T191	2		T242	2
auto[1]	values[5]	values[1]	7	1			T42	1		T32	1		T223	1
auto[1]	values[5]	values[2]	17	1			T32	2		T165	1		T56	1
auto[1]	values[5]	values[3]	9	1			T198	1		T279	2		T286	2
auto[1]	values[5]	values[4]	11	1			T240	2		T211	1		T153	1
auto[1]	values[5]	values[5]	30	1			T165	3		T22	1		T240	3
auto[1]	values[5]	values[6]	5	1			T33	1		T211	1		T263	1
auto[1]	values[5]	values[7]	20	1			T40	2		T166	2		T22	5
auto[1]	values[6]	values[0]	8	1			T33	3		T220	4		T287	1
auto[1]	values[6]	values[1]	23	1			T33	1		T166	1		T56	1
auto[1]	values[6]	values[2]	9	1			T42	1		T222	5		T154	2
auto[1]	values[6]	values[3]	3	1			T153	1		T288	2		-	-
auto[1]	values[6]	values[4]	8	1			T155	1		T27	1		T29	1
auto[1]	values[6]	values[5]	8	1			T186	1		T275	1		T289	2
auto[1]	values[6]	values[6]	8	1			T29	1		T180	1		T151	4
auto[1]	values[6]	values[7]	7	1			T186	3		T153	1		T235	1
auto[1]	values[7]	values[0]	14	1			T44	2		T27	1		T191	2
auto[1]	values[7]	values[1]	11	1			T33	2		T166	2		T153	2
auto[1]	values[7]	values[2]	12	1			T45	4		T211	4		T279	2
auto[1]	values[7]	values[3]	9	1			T31	1		T208	1		T128	1
auto[1]	values[7]	values[4]	19	1			T183	6		T22	2		T264	2
auto[1]	values[7]	values[5]	8	1			T185	1		T191	3		T235	2
auto[1]	values[7]	values[6]	2	1			T28	1		T290	1		-	-
auto[1]	values[7]	values[7]	31	1			T17	1		T43	2		T27	2