Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	865	1			T10	20		T19	14		T20	24
all_values[1]	865	1			T10	20		T19	14		T20	24
all_values[2]	865	1			T10	20		T19	14		T20	24
all_values[3]	865	1			T10	20		T19	14		T20	24
all_values[4]	865	1			T10	20		T19	14		T20	24
all_values[5]	865	1			T10	20		T19	14		T20	24
all_values[6]	865	1			T10	20		T19	14		T20	24
all_values[7]	865	1			T10	20		T19	14		T20	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3799

1

T10

64

T19

68

T20

99

auto[1]

3121

1

T10

96

T19

44

T20

93

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2811

1

T10

64

T19

51

T20

69

auto[1]

4109

1

T10

96

T19

61

T20

123

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3964

1

T10

90

T19

70

T20

106

auto[1]

2956

1

T10

70

T19

42

T20

86

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	183	1			T10	4		T19	5		T20	8
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T10	1		T21	4		T22	2
all_values[0]	auto[0]	auto[1]	auto[0]	141	1			T10	4		T19	5		T20	4
all_values[0]	auto[0]	auto[1]	auto[1]	86	1			T10	1		T20	3		T21	3
all_values[0]	auto[1]	auto[0]	auto[1]	207	1			T10	7		T19	2		T20	4
all_values[0]	auto[1]	auto[1]	auto[1]	168	1			T10	3		T19	2		T20	5
all_values[1]	auto[0]	auto[0]	auto[0]	209	1			T10	2		T19	2		T20	4
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T10	1		T19	4		T20	3
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T10	6		T20	3		T148	3
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T10	3		T19	3		T20	2
all_values[1]	auto[1]	auto[0]	auto[1]	193	1			T10	2		T19	3		T20	7
all_values[1]	auto[1]	auto[1]	auto[1]	167	1			T10	6		T19	2		T20	5
all_values[2]	auto[0]	auto[0]	auto[0]	187	1			T10	5		T19	4		T20	4
all_values[2]	auto[0]	auto[0]	auto[1]	94	1			T10	1		T19	1		T20	2
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T10	3		T19	1		T20	3
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T10	1		T19	3		T20	2
all_values[2]	auto[1]	auto[0]	auto[1]	197	1			T10	3		T19	2		T20	3
all_values[2]	auto[1]	auto[1]	auto[1]	158	1			T10	7		T19	3		T20	10
all_values[3]	auto[0]	auto[0]	auto[0]	153	1			T10	2		T19	4		T20	2
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T10	2		T19	3		T20	2
all_values[3]	auto[0]	auto[1]	auto[0]	145	1			T10	1		T19	2		T20	4
all_values[3]	auto[0]	auto[1]	auto[1]	95	1			T10	5		T20	5		T21	2
all_values[3]	auto[1]	auto[0]	auto[1]	221	1			T10	3		T19	5		T20	8
all_values[3]	auto[1]	auto[1]	auto[1]	170	1			T10	7		T20	3		T21	5
all_values[4]	auto[0]	auto[0]	auto[0]	194	1			T10	2		T19	7		T20	7
all_values[4]	auto[0]	auto[0]	auto[1]	88	1			T10	1		T20	4		T21	5
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T10	7		T19	2		T20	1
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T10	1		T19	1		T20	1
all_values[4]	auto[1]	auto[0]	auto[1]	201	1			T10	3		T19	2		T20	8
all_values[4]	auto[1]	auto[1]	auto[1]	166	1			T10	6		T19	2		T20	3
all_values[5]	auto[0]	auto[0]	auto[0]	270	1			T10	2		T19	4		T20	5
all_values[5]	auto[0]	auto[1]	auto[0]	228	1			T10	9		T19	3		T20	9
all_values[5]	auto[1]	auto[0]	auto[1]	199	1			T10	3		T19	2		T20	4
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T10	6		T19	5		T20	6
all_values[6]	auto[0]	auto[0]	auto[0]	190	1			T10	3		T19	4		T20	3
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T10	1		T19	3		T20	4
all_values[6]	auto[0]	auto[1]	auto[0]	157	1			T10	7		T19	2		T20	7
all_values[6]	auto[0]	auto[1]	auto[1]	72	1			T10	3		T20	1		T21	3
all_values[6]	auto[1]	auto[0]	auto[1]	206	1			T10	5		T19	3		T20	6
all_values[6]	auto[1]	auto[1]	auto[1]	158	1			T10	1		T19	2		T20	3
all_values[7]	auto[0]	auto[0]	auto[0]	196	1			T10	6		T19	3		T20	3
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T10	3		T19	1		T20	4
all_values[7]	auto[0]	auto[1]	auto[0]	138	1			T10	1		T19	3		T20	2
all_values[7]	auto[0]	auto[1]	auto[1]	84	1			T10	2		T20	4		T21	4
all_values[7]	auto[1]	auto[0]	auto[1]	212	1			T10	2		T19	4		T20	4
all_values[7]	auto[1]	auto[1]	auto[1]	165	1			T10	6		T19	3		T20	7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal