Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1886

1

T2

2

T4

1

T6

3

auto[1]

1839

1

T1

6

T2

2

T6

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1944

1

T1

1

T2

4

T4

1

auto[1]

1781

1

T1

5

T6

3

T7

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3005

1

T1

6

T2

3

T4

1

auto[1]

720

1

T2

1

T10

2

T23

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	759	1			T1	1		T2	1		T4	1
valid[1]	741	1			T1	2		T6	1		T7	2
valid[2]	733	1			T2	1		T6	2		T10	1
valid[3]	752	1			T1	3		T2	2		T6	2
valid[4]	740	1			T7	2		T11	5		T23	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	135	1			T2	1		T4	1		T23	1
auto[0]	auto[0]	valid[0]	auto[1]	193	1			T11	4		T25	1		T50	2
auto[0]	auto[0]	valid[1]	auto[0]	130	1			T23	1		T25	3		T31	2
auto[0]	auto[0]	valid[1]	auto[1]	192	1			T7	2		T11	4		T23	1
auto[0]	auto[0]	valid[2]	auto[0]	105	1			T6	1		T23	1		T41	1
auto[0]	auto[0]	valid[2]	auto[1]	178	1			T11	3		T24	3		T317	1
auto[0]	auto[0]	valid[3]	auto[0]	110	1			T6	1		T25	1		T31	1
auto[0]	auto[0]	valid[3]	auto[1]	182	1			T6	1		T7	3		T11	2
auto[0]	auto[0]	valid[4]	auto[0]	125	1			T25	1		T16	1		T49	1
auto[0]	auto[0]	valid[4]	auto[1]	183	1			T7	2		T11	3		T24	1
auto[0]	auto[1]	valid[0]	auto[0]	130	1			T48	1		T31	1		T41	1
auto[0]	auto[1]	valid[0]	auto[1]	162	1			T1	1		T7	1		T11	5
auto[0]	auto[1]	valid[1]	auto[0]	126	1			T10	1		T48	1		T31	1
auto[0]	auto[1]	valid[1]	auto[1]	152	1			T1	2		T6	1		T11	5
auto[0]	auto[1]	valid[2]	auto[0]	129	1			T2	1		T25	1		T48	1
auto[0]	auto[1]	valid[2]	auto[1]	181	1			T6	1		T11	4		T24	1
auto[0]	auto[1]	valid[3]	auto[0]	130	1			T1	1		T2	1		T10	1
auto[0]	auto[1]	valid[3]	auto[1]	175	1			T1	2		T11	3		T25	1
auto[0]	auto[1]	valid[4]	auto[0]	104	1			T23	1		T48	1		T143	1
auto[0]	auto[1]	valid[4]	auto[1]	183	1			T11	2		T24	2		T301	1
auto[1]	auto[0]	valid[0]	auto[0]	69	1			T25	1		T16	1		T41	1
auto[1]	auto[0]	valid[1]	auto[0]	67	1			T25	1		T16	1		T49	1
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T16	1		T143	1		T45	2
auto[1]	auto[0]	valid[3]	auto[0]	77	1			T2	1		T10	1		T23	1
auto[1]	auto[0]	valid[4]	auto[0]	71	1			T23	1		T25	2		T48	2
auto[1]	auto[1]	valid[0]	auto[0]	70	1			T31	2		T50	1		T143	1
auto[1]	auto[1]	valid[1]	auto[0]	74	1			T25	2		T48	1		T19	1
auto[1]	auto[1]	valid[2]	auto[0]	71	1			T10	1		T23	1		T25	1
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T23	1		T25	2		T16	1
auto[1]	auto[1]	valid[4]	auto[0]	74	1			T25	1		T31	1		T41	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal