Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49920

1

T1

77

T2

212

T4

14

auto[1]

18447

1

T1

38

T6

7

T7

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50300

1

T1

75

T2

142

T4

10

auto[1]

18067

1

T1

40

T2

70

T4

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35461	1			T1	69		T2	126		T4	2
others[1]	5691	1			T1	8		T2	13		T4	1
others[2]	5739	1			T1	9		T2	24		T4	2
others[3]	6461	1			T1	8		T2	10		T4	3
interest[1]	3688	1			T1	6		T2	9		T4	2
interest[4]	23193	1			T1	42		T2	85		T4	1
interest[64]	11327	1			T1	15		T2	30		T4	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16445	1			T1	18		T2	89		T4	1
auto[0]	auto[0]	others[1]	2670	1			T1	3		T2	9		T4	1
auto[0]	auto[0]	others[2]	2665	1			T1	3		T2	12		T4	1
auto[0]	auto[0]	others[3]	3010	1			T1	4		T2	8		T4	2
auto[0]	auto[0]	interest[1]	1774	1			T1	4		T2	7		T4	1
auto[0]	auto[0]	interest[4]	10666	1			T1	10		T2	60		T6	7
auto[0]	auto[0]	interest[64]	5289	1			T1	5		T2	17		T4	4
auto[0]	auto[1]	others[0]	9617	1			T1	28		T6	5		T7	8
auto[0]	auto[1]	others[1]	1542	1			T1	2		T11	49		T23	2
auto[0]	auto[1]	others[2]	1543	1			T1	2		T11	26		T23	2
auto[0]	auto[1]	others[3]	1782	1			T1	2		T6	1		T11	44
auto[0]	auto[1]	interest[1]	976	1			T1	1		T11	27		T23	1
auto[0]	auto[1]	interest[4]	6396	1			T1	17		T6	4		T7	8
auto[0]	auto[1]	interest[64]	2987	1			T1	3		T6	1		T11	76
auto[1]	auto[0]	others[0]	9399	1			T1	23		T2	37		T4	1
auto[1]	auto[0]	others[1]	1479	1			T1	3		T2	4		T10	3
auto[1]	auto[0]	others[2]	1531	1			T1	4		T2	12		T4	1
auto[1]	auto[0]	others[3]	1669	1			T1	2		T2	2		T4	1
auto[1]	auto[0]	interest[1]	938	1			T1	1		T2	2		T4	1
auto[1]	auto[0]	interest[4]	6131	1			T1	15		T2	25		T4	1
auto[1]	auto[0]	interest[64]	3051	1			T1	7		T2	13		T6	4

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal