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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.39 93.99 98.62 89.36 97.21 95.45 99.26


Total test records in report: 1131
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T101 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1259561287 Aug 06 07:48:26 PM PDT 24 Aug 06 07:48:49 PM PDT 24 3916155128 ps
T109 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4189783440 Aug 06 07:48:12 PM PDT 24 Aug 06 07:48:35 PM PDT 24 1267505993 ps
T1023 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2518959948 Aug 06 07:48:11 PM PDT 24 Aug 06 07:48:13 PM PDT 24 209466277 ps
T1024 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2830516477 Aug 06 07:48:08 PM PDT 24 Aug 06 07:48:09 PM PDT 24 48855444 ps
T110 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3506231657 Aug 06 07:48:30 PM PDT 24 Aug 06 07:48:32 PM PDT 24 82101273 ps
T161 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.399825387 Aug 06 07:48:14 PM PDT 24 Aug 06 07:48:17 PM PDT 24 481563815 ps
T1025 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.918985404 Aug 06 07:48:26 PM PDT 24 Aug 06 07:48:29 PM PDT 24 120161564 ps
T1026 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3161067077 Aug 06 07:48:30 PM PDT 24 Aug 06 07:48:31 PM PDT 24 13232703 ps
T111 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1461260252 Aug 06 07:48:07 PM PDT 24 Aug 06 07:48:09 PM PDT 24 39962964 ps
T1027 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2072993420 Aug 06 07:48:10 PM PDT 24 Aug 06 07:48:12 PM PDT 24 32017086 ps
T96 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2209291240 Aug 06 07:48:10 PM PDT 24 Aug 06 07:48:13 PM PDT 24 277900233 ps
T1028 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.777651241 Aug 06 07:48:33 PM PDT 24 Aug 06 07:48:34 PM PDT 24 38949126 ps
T1029 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2759445729 Aug 06 07:48:12 PM PDT 24 Aug 06 07:48:20 PM PDT 24 270109044 ps
T1030 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1398117379 Aug 06 07:48:08 PM PDT 24 Aug 06 07:48:47 PM PDT 24 1809072326 ps
T1031 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3460784520 Aug 06 07:48:09 PM PDT 24 Aug 06 07:48:22 PM PDT 24 2756127976 ps
T91 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.808018999 Aug 06 07:48:36 PM PDT 24 Aug 06 07:48:38 PM PDT 24 53444132 ps
T1032 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3476788835 Aug 06 07:48:44 PM PDT 24 Aug 06 07:48:45 PM PDT 24 18099388 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.48217238 Aug 06 07:48:13 PM PDT 24 Aug 06 07:48:15 PM PDT 24 36569840 ps
T1034 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2998632934 Aug 06 07:48:26 PM PDT 24 Aug 06 07:48:38 PM PDT 24 200382113 ps
T1035 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2450304849 Aug 06 07:48:34 PM PDT 24 Aug 06 07:48:35 PM PDT 24 51191140 ps
T1036 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2925224453 Aug 06 07:48:17 PM PDT 24 Aug 06 07:48:19 PM PDT 24 55815137 ps
T1037 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.554453912 Aug 06 07:48:25 PM PDT 24 Aug 06 07:48:26 PM PDT 24 63641216 ps
T1038 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3638155734 Aug 06 07:48:13 PM PDT 24 Aug 06 07:48:28 PM PDT 24 1423529121 ps
T1039 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1617768579 Aug 06 07:48:25 PM PDT 24 Aug 06 07:48:26 PM PDT 24 53299669 ps
T1040 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3679485556 Aug 06 07:48:13 PM PDT 24 Aug 06 07:48:14 PM PDT 24 10715179 ps
T1041 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2063501758 Aug 06 07:48:25 PM PDT 24 Aug 06 07:48:30 PM PDT 24 217587012 ps
T1042 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3092973271 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:32 PM PDT 24 16661468 ps
T1043 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2620857266 Aug 06 07:48:29 PM PDT 24 Aug 06 07:48:31 PM PDT 24 57025213 ps
T1044 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2766699006 Aug 06 07:48:10 PM PDT 24 Aug 06 07:48:29 PM PDT 24 295369844 ps
T1045 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4189767494 Aug 06 07:48:34 PM PDT 24 Aug 06 07:48:36 PM PDT 24 117169702 ps
T92 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2386171897 Aug 06 07:48:30 PM PDT 24 Aug 06 07:48:34 PM PDT 24 79752846 ps
T1046 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3884697148 Aug 06 07:48:32 PM PDT 24 Aug 06 07:48:36 PM PDT 24 204408149 ps
T78 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2804042296 Aug 06 07:48:08 PM PDT 24 Aug 06 07:48:10 PM PDT 24 74830927 ps
T1047 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1274217398 Aug 06 07:48:39 PM PDT 24 Aug 06 07:48:40 PM PDT 24 41297911 ps
T1048 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.591035208 Aug 06 07:48:11 PM PDT 24 Aug 06 07:48:11 PM PDT 24 19276822 ps
T112 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3657188412 Aug 06 07:48:14 PM PDT 24 Aug 06 07:48:16 PM PDT 24 95196734 ps
T1049 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1749261502 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:28 PM PDT 24 84925435 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.240377264 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:29 PM PDT 24 103455993 ps
T94 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2297867833 Aug 06 07:48:30 PM PDT 24 Aug 06 07:48:35 PM PDT 24 83924775 ps
T1051 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.275414198 Aug 06 07:48:30 PM PDT 24 Aug 06 07:48:32 PM PDT 24 414243360 ps
T1052 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4153095826 Aug 06 07:48:32 PM PDT 24 Aug 06 07:48:35 PM PDT 24 118171522 ps
T1053 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3687080199 Aug 06 07:48:33 PM PDT 24 Aug 06 07:48:34 PM PDT 24 16929733 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3976077890 Aug 06 07:48:23 PM PDT 24 Aug 06 07:48:33 PM PDT 24 1995448557 ps
T1055 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4080705621 Aug 06 07:48:34 PM PDT 24 Aug 06 07:48:36 PM PDT 24 272550978 ps
T1056 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2334737698 Aug 06 07:48:22 PM PDT 24 Aug 06 07:48:25 PM PDT 24 40461270 ps
T1057 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2136423810 Aug 06 07:48:24 PM PDT 24 Aug 06 07:48:27 PM PDT 24 615604186 ps
T95 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2298773516 Aug 06 07:48:12 PM PDT 24 Aug 06 07:48:14 PM PDT 24 289029060 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3625563021 Aug 06 07:48:11 PM PDT 24 Aug 06 07:48:19 PM PDT 24 419282358 ps
T1059 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1372100870 Aug 06 07:48:36 PM PDT 24 Aug 06 07:48:37 PM PDT 24 45360655 ps
T1060 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3953915038 Aug 06 07:48:29 PM PDT 24 Aug 06 07:48:33 PM PDT 24 50957171 ps
T1061 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1168224927 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:32 PM PDT 24 93867993 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2866489214 Aug 06 07:48:24 PM PDT 24 Aug 06 07:48:26 PM PDT 24 50221496 ps
T1063 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3523697464 Aug 06 07:48:20 PM PDT 24 Aug 06 07:48:46 PM PDT 24 5026490887 ps
T113 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2063732724 Aug 06 07:48:30 PM PDT 24 Aug 06 07:48:32 PM PDT 24 37166290 ps
T1064 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3097657313 Aug 06 07:48:26 PM PDT 24 Aug 06 07:48:27 PM PDT 24 27630878 ps
T1065 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1398706907 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:32 PM PDT 24 19261403 ps
T1066 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2371816057 Aug 06 07:48:23 PM PDT 24 Aug 06 07:48:24 PM PDT 24 37616786 ps
T1067 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2787738554 Aug 06 07:48:26 PM PDT 24 Aug 06 07:48:33 PM PDT 24 1332663882 ps
T1068 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3014782386 Aug 06 07:48:23 PM PDT 24 Aug 06 07:48:26 PM PDT 24 39174339 ps
T169 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1603986916 Aug 06 07:48:26 PM PDT 24 Aug 06 07:48:31 PM PDT 24 416698412 ps
T1069 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3560564186 Aug 06 07:48:33 PM PDT 24 Aug 06 07:48:34 PM PDT 24 12342825 ps
T1070 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.579676898 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:35 PM PDT 24 1175187981 ps
T1071 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3178884496 Aug 06 07:48:25 PM PDT 24 Aug 06 07:48:30 PM PDT 24 3331805740 ps
T171 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2432569412 Aug 06 07:48:30 PM PDT 24 Aug 06 07:48:43 PM PDT 24 3860820441 ps
T1072 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1320140741 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:32 PM PDT 24 15501282 ps
T1073 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3135218028 Aug 06 07:48:23 PM PDT 24 Aug 06 07:48:25 PM PDT 24 141635269 ps
T1074 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3967005610 Aug 06 07:48:33 PM PDT 24 Aug 06 07:48:34 PM PDT 24 18709693 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1545014260 Aug 06 07:48:22 PM PDT 24 Aug 06 07:48:23 PM PDT 24 124066360 ps
T114 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1481571368 Aug 06 07:48:11 PM PDT 24 Aug 06 07:48:13 PM PDT 24 528264391 ps
T1076 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1395332475 Aug 06 07:48:12 PM PDT 24 Aug 06 07:48:16 PM PDT 24 603401854 ps
T1077 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4099982695 Aug 06 07:48:30 PM PDT 24 Aug 06 07:48:31 PM PDT 24 14750031 ps
T1078 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.718498562 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:33 PM PDT 24 332187372 ps
T1079 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2350988949 Aug 06 07:48:23 PM PDT 24 Aug 06 07:48:26 PM PDT 24 153202196 ps
T1080 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2510586690 Aug 06 07:48:44 PM PDT 24 Aug 06 07:48:45 PM PDT 24 24412308 ps
T1081 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3082671674 Aug 06 07:48:32 PM PDT 24 Aug 06 07:48:33 PM PDT 24 42446610 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2417772190 Aug 06 07:48:22 PM PDT 24 Aug 06 07:48:24 PM PDT 24 98560102 ps
T1083 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2467640313 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:29 PM PDT 24 130494555 ps
T1084 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4186716400 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:32 PM PDT 24 31882076 ps
T1085 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.505418209 Aug 06 07:48:32 PM PDT 24 Aug 06 07:48:33 PM PDT 24 15188778 ps
T1086 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.537624899 Aug 06 07:48:25 PM PDT 24 Aug 06 07:48:27 PM PDT 24 68469683 ps
T170 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3532227585 Aug 06 07:48:23 PM PDT 24 Aug 06 07:48:25 PM PDT 24 488522325 ps
T173 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.536389843 Aug 06 07:48:11 PM PDT 24 Aug 06 07:48:33 PM PDT 24 3349439325 ps
T1087 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3039205769 Aug 06 07:48:24 PM PDT 24 Aug 06 07:48:31 PM PDT 24 456188220 ps
T1088 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.891995608 Aug 06 07:48:28 PM PDT 24 Aug 06 07:48:28 PM PDT 24 25971276 ps
T115 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.286107164 Aug 06 07:48:25 PM PDT 24 Aug 06 07:48:26 PM PDT 24 32622125 ps
T1089 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3228868098 Aug 06 07:48:29 PM PDT 24 Aug 06 07:48:32 PM PDT 24 238452451 ps
T1090 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3518602999 Aug 06 07:48:33 PM PDT 24 Aug 06 07:48:34 PM PDT 24 38955637 ps
T1091 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3241835258 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:32 PM PDT 24 13979200 ps
T1092 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2937601060 Aug 06 07:48:25 PM PDT 24 Aug 06 07:48:27 PM PDT 24 286837321 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2142908417 Aug 06 07:48:22 PM PDT 24 Aug 06 07:48:25 PM PDT 24 94280601 ps
T1094 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.89044772 Aug 06 07:48:26 PM PDT 24 Aug 06 07:48:27 PM PDT 24 21536764 ps
T1095 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2187826017 Aug 06 07:48:35 PM PDT 24 Aug 06 07:48:36 PM PDT 24 40744882 ps
T1096 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.977075905 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:28 PM PDT 24 41807194 ps
T1097 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3518257586 Aug 06 07:48:28 PM PDT 24 Aug 06 07:48:29 PM PDT 24 31517799 ps
T1098 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1687724804 Aug 06 07:48:10 PM PDT 24 Aug 06 07:48:19 PM PDT 24 414912667 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2586434450 Aug 06 07:48:11 PM PDT 24 Aug 06 07:48:14 PM PDT 24 63486118 ps
T1100 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2546087827 Aug 06 07:48:20 PM PDT 24 Aug 06 07:48:23 PM PDT 24 131340601 ps
T1101 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.785813485 Aug 06 07:48:33 PM PDT 24 Aug 06 07:48:34 PM PDT 24 12062779 ps
T1102 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2490432955 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:32 PM PDT 24 13603182 ps
T1103 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2539895962 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:30 PM PDT 24 212702724 ps
T1104 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.500457941 Aug 06 07:48:13 PM PDT 24 Aug 06 07:48:14 PM PDT 24 17028876 ps
T1105 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1799480042 Aug 06 07:48:29 PM PDT 24 Aug 06 07:48:29 PM PDT 24 16888331 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1170480274 Aug 06 07:48:12 PM PDT 24 Aug 06 07:48:13 PM PDT 24 44113577 ps
T1107 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1605141410 Aug 06 07:48:23 PM PDT 24 Aug 06 07:48:24 PM PDT 24 12512762 ps
T1108 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.469762770 Aug 06 07:48:21 PM PDT 24 Aug 06 07:48:23 PM PDT 24 19852643 ps
T1109 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2682440405 Aug 06 07:48:33 PM PDT 24 Aug 06 07:48:35 PM PDT 24 38890452 ps
T79 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3550924107 Aug 06 07:48:13 PM PDT 24 Aug 06 07:48:15 PM PDT 24 52781298 ps
T80 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.546474755 Aug 06 07:48:20 PM PDT 24 Aug 06 07:48:21 PM PDT 24 16215895 ps
T1110 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1011253480 Aug 06 07:48:14 PM PDT 24 Aug 06 07:48:39 PM PDT 24 1887117618 ps
T1111 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1981133428 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:29 PM PDT 24 306770773 ps
T1112 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.270203660 Aug 06 07:48:23 PM PDT 24 Aug 06 07:48:24 PM PDT 24 13884028 ps
T1113 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2591485842 Aug 06 07:48:09 PM PDT 24 Aug 06 07:48:12 PM PDT 24 73429362 ps
T1114 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1289343248 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:29 PM PDT 24 554293364 ps
T1115 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.386131302 Aug 06 07:48:09 PM PDT 24 Aug 06 07:48:10 PM PDT 24 15698048 ps
T1116 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3414431371 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:27 PM PDT 24 26529881 ps
T1117 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.301934577 Aug 06 07:48:20 PM PDT 24 Aug 06 07:48:22 PM PDT 24 27016793 ps
T1118 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3936890647 Aug 06 07:48:35 PM PDT 24 Aug 06 07:48:38 PM PDT 24 108390393 ps
T1119 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2279663174 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:33 PM PDT 24 74366751 ps
T1120 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4231871365 Aug 06 07:48:35 PM PDT 24 Aug 06 07:48:53 PM PDT 24 820589553 ps
T1121 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2162379664 Aug 06 07:48:24 PM PDT 24 Aug 06 07:48:28 PM PDT 24 171103621 ps
T1122 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4083371878 Aug 06 07:48:25 PM PDT 24 Aug 06 07:48:25 PM PDT 24 14479088 ps
T1123 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.342851930 Aug 06 07:48:13 PM PDT 24 Aug 06 07:48:15 PM PDT 24 337064732 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3940210002 Aug 06 07:48:13 PM PDT 24 Aug 06 07:48:15 PM PDT 24 298209153 ps
T1125 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3586878058 Aug 06 07:48:25 PM PDT 24 Aug 06 07:48:28 PM PDT 24 559958888 ps
T1126 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1635821276 Aug 06 07:48:24 PM PDT 24 Aug 06 07:48:41 PM PDT 24 784422845 ps
T172 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.179277918 Aug 06 07:48:23 PM PDT 24 Aug 06 07:48:38 PM PDT 24 706709432 ps
T1127 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3896825781 Aug 06 07:48:27 PM PDT 24 Aug 06 07:48:29 PM PDT 24 66996186 ps
T1128 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2756427217 Aug 06 07:48:10 PM PDT 24 Aug 06 07:48:11 PM PDT 24 13171980 ps
T1129 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3130378370 Aug 06 07:48:09 PM PDT 24 Aug 06 07:48:10 PM PDT 24 48380520 ps
T1130 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.745875585 Aug 06 07:48:29 PM PDT 24 Aug 06 07:48:32 PM PDT 24 110814878 ps
T1131 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2518836931 Aug 06 07:48:11 PM PDT 24 Aug 06 07:48:13 PM PDT 24 53678012 ps

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4011081105
Short name T6
Test name
Test status
Simulation time 140321585741 ps
CPU time 256.87 seconds
Started Aug 06 07:53:00 PM PDT 24
Finished Aug 06 07:57:16 PM PDT 24
Peak memory 265848 kb
Host smart-77626aaf-ff30-4673-8bc2-77d4edb106f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011081105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.4011081105
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1512611933
Short name T41
Test name
Test status
Simulation time 58821915534 ps
CPU time 236.25 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:56:02 PM PDT 24
Peak memory 250996 kb
Host smart-9d32dfac-62a4-423e-b5d2-7038113887ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512611933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1512611933
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2130583427
Short name T10
Test name
Test status
Simulation time 4170922378 ps
CPU time 87.08 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:54:34 PM PDT 24
Peak memory 257772 kb
Host smart-ef691eb2-ab6b-4f39-9d11-304528328184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130583427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2130583427
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1902938497
Short name T70
Test name
Test status
Simulation time 2672760507 ps
CPU time 15.31 seconds
Started Aug 06 07:48:24 PM PDT 24
Finished Aug 06 07:48:40 PM PDT 24
Peak memory 215352 kb
Host smart-31cf712c-4f86-4294-995b-038fed5ca2a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902938497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1902938497
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.699412140
Short name T22
Test name
Test status
Simulation time 52855095302 ps
CPU time 576.49 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 08:03:24 PM PDT 24
Peak memory 272956 kb
Host smart-53daf088-3962-4d81-9a7b-096fb9b12852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699412140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.699412140
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3293324112
Short name T33
Test name
Test status
Simulation time 13890848213 ps
CPU time 89.36 seconds
Started Aug 06 07:53:19 PM PDT 24
Finished Aug 06 07:54:49 PM PDT 24
Peak memory 254808 kb
Host smart-85711093-de5b-450a-8bfb-96fd6442ab43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293324112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3293324112
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2822738675
Short name T71
Test name
Test status
Simulation time 18266825 ps
CPU time 0.78 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 216392 kb
Host smart-5cd8fb4e-93ef-4dcc-ab5e-cfd3df83a04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822738675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2822738675
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.748095567
Short name T166
Test name
Test status
Simulation time 24881824595 ps
CPU time 176.93 seconds
Started Aug 06 07:53:49 PM PDT 24
Finished Aug 06 07:56:46 PM PDT 24
Peak memory 266488 kb
Host smart-c4165635-e339-4563-b5b7-ff5fc38edc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748095567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.748095567
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2823886326
Short name T69
Test name
Test status
Simulation time 734012846 ps
CPU time 4.68 seconds
Started Aug 06 07:48:29 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 216248 kb
Host smart-7d5c49ec-502e-43b0-8a96-6376a6298a78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823886326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2823886326
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1756735211
Short name T153
Test name
Test status
Simulation time 183023744493 ps
CPU time 431.36 seconds
Started Aug 06 07:54:26 PM PDT 24
Finished Aug 06 08:01:38 PM PDT 24
Peak memory 282092 kb
Host smart-19d3ffc9-1f49-4f82-8ff4-a78e18a6cb9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756735211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1756735211
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3886656281
Short name T27
Test name
Test status
Simulation time 89113326236 ps
CPU time 787.54 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 08:06:05 PM PDT 24
Peak memory 266684 kb
Host smart-b4cc35e3-25ea-4b4f-9c78-21704e98f4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886656281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3886656281
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2673542278
Short name T32
Test name
Test status
Simulation time 73966290768 ps
CPU time 117.15 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:55:42 PM PDT 24
Peak memory 262220 kb
Host smart-3c341b2e-7436-4d4f-bf26-f171fbdee765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673542278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2673542278
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3416602685
Short name T5
Test name
Test status
Simulation time 47754178 ps
CPU time 0.96 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:52:06 PM PDT 24
Peak memory 236348 kb
Host smart-c548d46f-da75-4b58-9f4e-903ae814a878
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416602685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3416602685
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1014068235
Short name T191
Test name
Test status
Simulation time 148821957947 ps
CPU time 706.92 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 08:03:45 PM PDT 24
Peak memory 273924 kb
Host smart-238d960b-64bd-4c98-86b9-31eaa8b1278b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014068235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1014068235
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3098590390
Short name T136
Test name
Test status
Simulation time 6633267629 ps
CPU time 36.09 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:52:34 PM PDT 24
Peak memory 234416 kb
Host smart-a616bd88-02b8-4514-a0f7-55337bc20870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098590390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3098590390
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1415473448
Short name T165
Test name
Test status
Simulation time 235202560684 ps
CPU time 532.2 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 08:01:44 PM PDT 24
Peak memory 257888 kb
Host smart-6e9a06c4-46dc-416c-b422-7ac588102622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415473448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1415473448
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2428412015
Short name T151
Test name
Test status
Simulation time 41584446111 ps
CPU time 133.54 seconds
Started Aug 06 07:52:21 PM PDT 24
Finished Aug 06 07:54:34 PM PDT 24
Peak memory 273676 kb
Host smart-88759d94-3a48-4877-bb86-271b8de15469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428412015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2428412015
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1093724293
Short name T77
Test name
Test status
Simulation time 18832721 ps
CPU time 1.14 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 207012 kb
Host smart-c3c1e1b3-f8c5-4de5-8574-a7112a491fad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093724293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1093724293
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3022524472
Short name T186
Test name
Test status
Simulation time 120539638497 ps
CPU time 121.03 seconds
Started Aug 06 07:52:31 PM PDT 24
Finished Aug 06 07:54:32 PM PDT 24
Peak memory 264008 kb
Host smart-55a316c8-51d3-4243-818c-a2841dbd4797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022524472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3022524472
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2737093397
Short name T128
Test name
Test status
Simulation time 91582184487 ps
CPU time 363.87 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:59:14 PM PDT 24
Peak memory 264772 kb
Host smart-3af7d9de-9ec6-4f11-aa30-921b1393f0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737093397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2737093397
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.775201020
Short name T209
Test name
Test status
Simulation time 5619485355 ps
CPU time 108.95 seconds
Started Aug 06 07:52:15 PM PDT 24
Finished Aug 06 07:54:04 PM PDT 24
Peak memory 254608 kb
Host smart-3eafe41a-dd4f-472b-81c3-8d74b14e6a15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775201020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.775201020
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.110931612
Short name T48
Test name
Test status
Simulation time 23486536937 ps
CPU time 32.22 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:52:38 PM PDT 24
Peak memory 216692 kb
Host smart-f1bf8aaf-f539-4711-9419-9e821de2ea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110931612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.110931612
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.38641131
Short name T200
Test name
Test status
Simulation time 56805636327 ps
CPU time 151.8 seconds
Started Aug 06 07:52:38 PM PDT 24
Finished Aug 06 07:55:10 PM PDT 24
Peak memory 266868 kb
Host smart-1acb5648-c983-4238-9bfc-7ff7024c0353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38641131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.38641131
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.558005697
Short name T189
Test name
Test status
Simulation time 3034718122 ps
CPU time 71.82 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:54:19 PM PDT 24
Peak memory 257768 kb
Host smart-bac396fd-902d-40b5-be6b-26f6ebdfd109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558005697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.558005697
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3268223625
Short name T42
Test name
Test status
Simulation time 6411708114 ps
CPU time 40.37 seconds
Started Aug 06 07:53:31 PM PDT 24
Finished Aug 06 07:54:12 PM PDT 24
Peak memory 249824 kb
Host smart-7719d08d-0b69-422c-b0c3-c4ec4c2af8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268223625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3268223625
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3645348891
Short name T198
Test name
Test status
Simulation time 348557945665 ps
CPU time 452.49 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 08:00:23 PM PDT 24
Peak memory 270272 kb
Host smart-63f8e4e0-41d4-4e40-8dfc-aabfcbe2a3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645348891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3645348891
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3338510031
Short name T2
Test name
Test status
Simulation time 28033428158 ps
CPU time 246.63 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:57:20 PM PDT 24
Peak memory 256816 kb
Host smart-d043e811-7e78-4a5f-8931-bf7134650786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338510031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3338510031
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2967068724
Short name T17
Test name
Test status
Simulation time 28082582132 ps
CPU time 226.19 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:57:52 PM PDT 24
Peak memory 257772 kb
Host smart-3fe4fa9c-0a88-4523-978d-7944bb8a9abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967068724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2967068724
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4292911697
Short name T65
Test name
Test status
Simulation time 23328517 ps
CPU time 0.73 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:52:58 PM PDT 24
Peak memory 205244 kb
Host smart-276c0ee4-70aa-41bb-8e4a-46bb3297c567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292911697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4292911697
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3974954352
Short name T54
Test name
Test status
Simulation time 16577752174 ps
CPU time 176.7 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:55:53 PM PDT 24
Peak memory 257836 kb
Host smart-941b3bab-8436-45ed-b6a4-2f5894c3bac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974954352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3974954352
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.179277918
Short name T172
Test name
Test status
Simulation time 706709432 ps
CPU time 14.85 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:38 PM PDT 24
Peak memory 217736 kb
Host smart-a47fedb4-3457-4799-9d8b-b9fee87f75c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179277918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.179277918
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2052170647
Short name T45
Test name
Test status
Simulation time 37114642837 ps
CPU time 182.51 seconds
Started Aug 06 07:53:51 PM PDT 24
Finished Aug 06 07:56:54 PM PDT 24
Peak memory 255204 kb
Host smart-3e2e82d3-7673-494a-9159-04e49393e937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052170647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2052170647
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2297867833
Short name T94
Test name
Test status
Simulation time 83924775 ps
CPU time 4.87 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 216312 kb
Host smart-e1115cd4-5b1d-42b7-8ff9-c272f8cd6d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297867833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2297867833
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3322808673
Short name T180
Test name
Test status
Simulation time 56045299297 ps
CPU time 381.66 seconds
Started Aug 06 07:52:46 PM PDT 24
Finished Aug 06 07:59:08 PM PDT 24
Peak memory 256296 kb
Host smart-3aa83884-904b-477c-adb7-1cdc853db91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322808673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3322808673
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.4189046996
Short name T204
Test name
Test status
Simulation time 284260571946 ps
CPU time 456.35 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 08:00:29 PM PDT 24
Peak memory 241376 kb
Host smart-e1733f42-812a-4f96-bcd8-ae70b85a7ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189046996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.4189046996
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3273800064
Short name T83
Test name
Test status
Simulation time 21851499738 ps
CPU time 68.89 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:54:16 PM PDT 24
Peak memory 255380 kb
Host smart-384efe46-039d-4d10-af61-2579f48bd8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273800064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3273800064
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3891754775
Short name T235
Test name
Test status
Simulation time 122269856627 ps
CPU time 304.37 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:58:00 PM PDT 24
Peak memory 262656 kb
Host smart-4caf976e-290f-4091-8c65-1065b393f306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891754775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3891754775
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1322495978
Short name T318
Test name
Test status
Simulation time 27173678451 ps
CPU time 14.28 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 216744 kb
Host smart-bd630c88-62f2-43db-95a4-276f295ae8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322495978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1322495978
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1877763151
Short name T211
Test name
Test status
Simulation time 9010657840 ps
CPU time 139.86 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:54:17 PM PDT 24
Peak memory 256344 kb
Host smart-ea6fe397-392a-4b20-b7d6-a897a276365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877763151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1877763151
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.557807879
Short name T298
Test name
Test status
Simulation time 88172597 ps
CPU time 6.45 seconds
Started Aug 06 07:52:04 PM PDT 24
Finished Aug 06 07:52:10 PM PDT 24
Peak memory 225028 kb
Host smart-2a232720-76c5-4d9a-bc09-1f6cfd2f5c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557807879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.557807879
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2766699006
Short name T1044
Test name
Test status
Simulation time 295369844 ps
CPU time 19.05 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 215104 kb
Host smart-65ed9535-98d4-46b1-be45-91999844e7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766699006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2766699006
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2432569412
Short name T171
Test name
Test status
Simulation time 3860820441 ps
CPU time 12.49 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:43 PM PDT 24
Peak memory 215392 kb
Host smart-b19788a4-2c96-42c5-93f7-dd645e3a0eff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432569412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2432569412
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3940210002
Short name T1124
Test name
Test status
Simulation time 298209153 ps
CPU time 2.42 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 215264 kb
Host smart-831bd4de-dbea-4eb4-854e-1a2838d29865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940210002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
940210002
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3640045214
Short name T178
Test name
Test status
Simulation time 263157487 ps
CPU time 2.78 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 233132 kb
Host smart-e4ee2c9d-0a09-4e05-842c-1c702542ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640045214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3640045214
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.575669097
Short name T263
Test name
Test status
Simulation time 14770940197 ps
CPU time 98.69 seconds
Started Aug 06 07:52:03 PM PDT 24
Finished Aug 06 07:53:42 PM PDT 24
Peak memory 256632 kb
Host smart-d40f8d90-61b9-4066-b80a-5ba2686e4733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575669097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.575669097
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3426140932
Short name T294
Test name
Test status
Simulation time 471382519 ps
CPU time 3.79 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 224944 kb
Host smart-17d348d1-aa4f-4a85-a1ad-a767814a05a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426140932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3426140932
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2814886795
Short name T230
Test name
Test status
Simulation time 36679022183 ps
CPU time 296.18 seconds
Started Aug 06 07:52:29 PM PDT 24
Finished Aug 06 07:57:25 PM PDT 24
Peak memory 267288 kb
Host smart-d76adb24-0916-44ae-bd40-549a8754421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814886795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2814886795
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1450193708
Short name T934
Test name
Test status
Simulation time 134974877228 ps
CPU time 319.37 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:58:12 PM PDT 24
Peak memory 257028 kb
Host smart-527e299d-b865-4871-bcea-2b4e57fc99d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450193708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1450193708
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.324968271
Short name T28
Test name
Test status
Simulation time 5758080078 ps
CPU time 34.76 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:53:31 PM PDT 24
Peak memory 237300 kb
Host smart-269ca62b-f9af-426f-af16-6755b1bff0f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324968271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.324968271
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1621663281
Short name T256
Test name
Test status
Simulation time 27386044126 ps
CPU time 122.59 seconds
Started Aug 06 07:52:03 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 265940 kb
Host smart-51b61239-d768-4333-b2c6-c53b9f1a331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621663281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1621663281
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.296452792
Short name T319
Test name
Test status
Simulation time 5810629094 ps
CPU time 89.02 seconds
Started Aug 06 07:53:33 PM PDT 24
Finished Aug 06 07:55:02 PM PDT 24
Peak memory 249736 kb
Host smart-3bedec7c-498e-40cf-9239-1495974c3046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296452792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.296452792
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3594047174
Short name T81
Test name
Test status
Simulation time 851006328 ps
CPU time 8.22 seconds
Started Aug 06 07:52:24 PM PDT 24
Finished Aug 06 07:52:33 PM PDT 24
Peak memory 241096 kb
Host smart-51ddba2d-ddae-4cf7-a8a4-dec544ea5b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594047174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3594047174
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1010501030
Short name T46
Test name
Test status
Simulation time 1774312128 ps
CPU time 8.34 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:01 PM PDT 24
Peak memory 248988 kb
Host smart-b1947efc-2180-4d82-a89f-b746fa76645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010501030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1010501030
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2804042296
Short name T78
Test name
Test status
Simulation time 74830927 ps
CPU time 1.1 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:10 PM PDT 24
Peak memory 206920 kb
Host smart-a12d7346-db44-47fc-9aa0-33702e909a9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804042296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2804042296
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1405675896
Short name T35
Test name
Test status
Simulation time 151611940 ps
CPU time 5.23 seconds
Started Aug 06 07:52:35 PM PDT 24
Finished Aug 06 07:52:40 PM PDT 24
Peak memory 233148 kb
Host smart-bb6a83c3-d686-456e-8e0f-fae19196d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405675896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1405675896
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1687724804
Short name T1098
Test name
Test status
Simulation time 414912667 ps
CPU time 8.74 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:19 PM PDT 24
Peak memory 215200 kb
Host smart-e5f82c9f-5347-42b3-9d17-8593626c55ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687724804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1687724804
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1398117379
Short name T1030
Test name
Test status
Simulation time 1809072326 ps
CPU time 38.81 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:47 PM PDT 24
Peak memory 206944 kb
Host smart-4deccfda-c113-42fe-ae85-1417e7c5d58c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398117379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1398117379
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2518959948
Short name T1023
Test name
Test status
Simulation time 209466277 ps
CPU time 1.78 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 215276 kb
Host smart-b7f28ad5-1ae4-417f-9729-acaa74f193e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518959948 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2518959948
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4036182182
Short name T105
Test name
Test status
Simulation time 96954587 ps
CPU time 2.41 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 215152 kb
Host smart-3ae69925-2c93-4044-8d12-d7c9759c9ece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036182182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
036182182
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.178897726
Short name T1009
Test name
Test status
Simulation time 39909575 ps
CPU time 0.73 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 203676 kb
Host smart-9745caf7-bd76-4bc5-bb92-98ec7d84b4a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178897726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.178897726
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1170480274
Short name T1106
Test name
Test status
Simulation time 44113577 ps
CPU time 1.28 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 215080 kb
Host smart-29f97bc1-28aa-4ec3-b3cc-0fd247b04f87
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170480274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1170480274
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2830516477
Short name T1024
Test name
Test status
Simulation time 48855444 ps
CPU time 0.71 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 203620 kb
Host smart-3737aaab-08de-424d-9347-6e494f602802
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830516477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2830516477
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1957174738
Short name T132
Test name
Test status
Simulation time 268207724 ps
CPU time 4.31 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 215104 kb
Host smart-d0000bab-a3dc-4759-85a7-4ffe40c1b108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957174738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1957174738
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2209291240
Short name T96
Test name
Test status
Simulation time 277900233 ps
CPU time 2.01 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 215280 kb
Host smart-2e9d12c8-1dd4-42e1-a4c0-f8f87610035d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209291240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
209291240
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1516019936
Short name T145
Test name
Test status
Simulation time 2144664718 ps
CPU time 25.4 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 215204 kb
Host smart-8d6fce87-a796-4ef7-9813-aa4a57148b63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516019936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1516019936
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3460784520
Short name T1031
Test name
Test status
Simulation time 2756127976 ps
CPU time 12.03 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:22 PM PDT 24
Peak memory 207064 kb
Host smart-f5daac78-7df3-4008-a866-e384a12fa254
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460784520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3460784520
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1343033790
Short name T76
Test name
Test status
Simulation time 16898684 ps
CPU time 1.02 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 206816 kb
Host smart-55a6f2b3-f7cc-4674-a949-827b34dc0d01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343033790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1343033790
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3119671769
Short name T68
Test name
Test status
Simulation time 140776014 ps
CPU time 2.8 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 216500 kb
Host smart-9e4134f8-bd3c-4e57-b73c-579ea9445f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119671769 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3119671769
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1461260252
Short name T111
Test name
Test status
Simulation time 39962964 ps
CPU time 1.42 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 206932 kb
Host smart-29a89c25-76e0-45ea-a445-4256a068ec48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461260252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
461260252
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3130378370
Short name T1129
Test name
Test status
Simulation time 48380520 ps
CPU time 0.73 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:10 PM PDT 24
Peak memory 203692 kb
Host smart-34802e0b-ae6a-4819-9208-e400e37ebcce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130378370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
130378370
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2072993420
Short name T1027
Test name
Test status
Simulation time 32017086 ps
CPU time 1.33 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 214996 kb
Host smart-0911b341-e6b2-4a72-a705-51b63730e520
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072993420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2072993420
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.386131302
Short name T1115
Test name
Test status
Simulation time 15698048 ps
CPU time 0.67 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:10 PM PDT 24
Peak memory 203496 kb
Host smart-b8ab42cc-322a-4cc4-8ffc-2103a69b9675
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386131302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.386131302
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2591485842
Short name T1113
Test name
Test status
Simulation time 73429362 ps
CPU time 2.87 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 215144 kb
Host smart-df77e881-ccfa-4b70-b496-777ca3f1d2a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591485842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2591485842
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2298773516
Short name T95
Test name
Test status
Simulation time 289029060 ps
CPU time 2.09 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 216300 kb
Host smart-e163676e-7985-45fd-96d6-7dbebcfaeb4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298773516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
298773516
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3366384242
Short name T88
Test name
Test status
Simulation time 3376479295 ps
CPU time 20.15 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:30 PM PDT 24
Peak memory 215340 kb
Host smart-eb956e26-0c2b-4179-9f74-36abfac30f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366384242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3366384242
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3953915038
Short name T1060
Test name
Test status
Simulation time 50957171 ps
CPU time 3.41 seconds
Started Aug 06 07:48:29 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 217804 kb
Host smart-7dd23962-6cf4-418b-9541-27fa26d7d02a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953915038 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3953915038
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3506231657
Short name T110
Test name
Test status
Simulation time 82101273 ps
CPU time 2.12 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 206940 kb
Host smart-c0b47d82-4919-4546-ae1e-fb808ce12f3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506231657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3506231657
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2677277318
Short name T1017
Test name
Test status
Simulation time 35412695 ps
CPU time 0.71 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 203912 kb
Host smart-48210310-3236-4c0c-811a-b88a9f9634a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677277318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2677277318
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1078079345
Short name T131
Test name
Test status
Simulation time 796325686 ps
CPU time 3.75 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 215184 kb
Host smart-90f3b112-21c6-40aa-bcd8-eb64ad1d02f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078079345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1078079345
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1289343248
Short name T1114
Test name
Test status
Simulation time 554293364 ps
CPU time 1.66 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 215104 kb
Host smart-05cfb4e8-4f3c-440f-bb0d-46efe420adec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289343248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1289343248
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.579676898
Short name T1070
Test name
Test status
Simulation time 1175187981 ps
CPU time 8.18 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 215164 kb
Host smart-1a6964ea-e0a0-4d61-9138-48cc8f862996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579676898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.579676898
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4189767494
Short name T1045
Test name
Test status
Simulation time 117169702 ps
CPU time 1.8 seconds
Started Aug 06 07:48:34 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 216160 kb
Host smart-06f381af-6d7b-46a8-ae33-7add444248f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189767494 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4189767494
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2063732724
Short name T113
Test name
Test status
Simulation time 37166290 ps
CPU time 2.32 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 215148 kb
Host smart-16542e4d-1d9c-47f4-9836-6634e21c3ad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063732724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2063732724
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3414431371
Short name T1116
Test name
Test status
Simulation time 26529881 ps
CPU time 0.74 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:27 PM PDT 24
Peak memory 203932 kb
Host smart-bda359d7-ea66-4a15-9748-a8a67e16be0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414431371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3414431371
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1956133072
Short name T1016
Test name
Test status
Simulation time 26055189 ps
CPU time 1.69 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 215188 kb
Host smart-3cc3f0dc-4522-4e3f-91bc-40d292b0913e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956133072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1956133072
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2236690792
Short name T147
Test name
Test status
Simulation time 666128670 ps
CPU time 14.82 seconds
Started Aug 06 07:48:28 PM PDT 24
Finished Aug 06 07:48:43 PM PDT 24
Peak memory 215404 kb
Host smart-61c90989-2d4a-43e5-95c5-99f2728eb4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236690792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2236690792
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.718498562
Short name T1078
Test name
Test status
Simulation time 332187372 ps
CPU time 1.71 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 216228 kb
Host smart-073f057d-62a6-49ef-9e65-6ae9c0c2f456
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718498562 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.718498562
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1003622476
Short name T104
Test name
Test status
Simulation time 21283244 ps
CPU time 1.24 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 206944 kb
Host smart-96b94427-cfb8-4914-bff7-da62fa40cded
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003622476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1003622476
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1706831737
Short name T1007
Test name
Test status
Simulation time 11395464 ps
CPU time 0.69 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:31 PM PDT 24
Peak memory 203660 kb
Host smart-cea1d71d-d674-4b3e-9d5b-d9520651c8d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706831737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1706831737
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.745875585
Short name T1130
Test name
Test status
Simulation time 110814878 ps
CPU time 2.93 seconds
Started Aug 06 07:48:29 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 215200 kb
Host smart-54b15d64-006b-4e22-85df-c698bfa91b2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745875585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.745875585
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1868746523
Short name T87
Test name
Test status
Simulation time 511249010 ps
CPU time 4.01 seconds
Started Aug 06 07:48:24 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 215596 kb
Host smart-4e53167c-2fb2-44d0-959f-1ec5f116e083
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868746523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1868746523
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1259561287
Short name T101
Test name
Test status
Simulation time 3916155128 ps
CPU time 22.56 seconds
Started Aug 06 07:48:26 PM PDT 24
Finished Aug 06 07:48:49 PM PDT 24
Peak memory 215204 kb
Host smart-40568166-5e9d-454a-a8db-11d1d79d48ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259561287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1259561287
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4153095826
Short name T1052
Test name
Test status
Simulation time 118171522 ps
CPU time 2.48 seconds
Started Aug 06 07:48:32 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 216892 kb
Host smart-e27345a3-30f5-4c4e-abe5-e3ea95a33c5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153095826 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4153095826
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2279663174
Short name T1119
Test name
Test status
Simulation time 74366751 ps
CPU time 2.02 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 215124 kb
Host smart-f427ccfa-0399-4b3d-84fe-c3ec9ea1a4b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279663174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2279663174
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3161067077
Short name T1026
Test name
Test status
Simulation time 13232703 ps
CPU time 0.69 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:31 PM PDT 24
Peak memory 203648 kb
Host smart-6356b845-80b1-48ff-bd47-ec8ea48c57a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161067077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3161067077
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2099272225
Short name T133
Test name
Test status
Simulation time 344177685 ps
CPU time 1.93 seconds
Started Aug 06 07:48:40 PM PDT 24
Finished Aug 06 07:48:42 PM PDT 24
Peak memory 207012 kb
Host smart-05217597-a04d-4cf9-8fa4-381548cc283a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099272225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2099272225
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.808018999
Short name T91
Test name
Test status
Simulation time 53444132 ps
CPU time 1.68 seconds
Started Aug 06 07:48:36 PM PDT 24
Finished Aug 06 07:48:38 PM PDT 24
Peak memory 215292 kb
Host smart-8348a996-3a85-46c8-8b67-9ac76db5101a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808018999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.808018999
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3039205769
Short name T1087
Test name
Test status
Simulation time 456188220 ps
CPU time 6.9 seconds
Started Aug 06 07:48:24 PM PDT 24
Finished Aug 06 07:48:31 PM PDT 24
Peak memory 215276 kb
Host smart-06734d87-1fb9-4323-aca4-e38236b1ed29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039205769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3039205769
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2350988949
Short name T1079
Test name
Test status
Simulation time 153202196 ps
CPU time 2.69 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:26 PM PDT 24
Peak memory 216664 kb
Host smart-65ddd167-f5fa-42fb-b0ce-3924da05b9c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350988949 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2350988949
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3228868098
Short name T1089
Test name
Test status
Simulation time 238452451 ps
CPU time 2.44 seconds
Started Aug 06 07:48:29 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 215192 kb
Host smart-ad63745b-20bf-47ff-9b36-4485218fb03e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228868098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3228868098
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.891995608
Short name T1088
Test name
Test status
Simulation time 25971276 ps
CPU time 0.76 seconds
Started Aug 06 07:48:28 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 203668 kb
Host smart-5a82b719-894c-4327-b9f0-7c56efb89a5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891995608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.891995608
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2162379664
Short name T1121
Test name
Test status
Simulation time 171103621 ps
CPU time 3.95 seconds
Started Aug 06 07:48:24 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 215248 kb
Host smart-a49dd932-62fe-426c-908b-9ea19631e682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162379664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2162379664
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4080705621
Short name T1055
Test name
Test status
Simulation time 272550978 ps
CPU time 1.94 seconds
Started Aug 06 07:48:34 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 215256 kb
Host smart-83841a44-30a1-4b8a-8dba-13d85f399d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080705621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4080705621
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4231871365
Short name T1120
Test name
Test status
Simulation time 820589553 ps
CPU time 17.78 seconds
Started Aug 06 07:48:35 PM PDT 24
Finished Aug 06 07:48:53 PM PDT 24
Peak memory 215216 kb
Host smart-38c5b857-8326-4fdb-8768-3860df9a78b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231871365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4231871365
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1012143359
Short name T97
Test name
Test status
Simulation time 115272338 ps
CPU time 3.66 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 217288 kb
Host smart-f8ac12d5-de35-4965-b403-b7b09bdcd977
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012143359 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1012143359
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2866489214
Short name T1062
Test name
Test status
Simulation time 50221496 ps
CPU time 1.35 seconds
Started Aug 06 07:48:24 PM PDT 24
Finished Aug 06 07:48:26 PM PDT 24
Peak memory 215196 kb
Host smart-a9964c59-3385-4e18-a4ff-b643ebc5cac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866489214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2866489214
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.89044772
Short name T1094
Test name
Test status
Simulation time 21536764 ps
CPU time 0.75 seconds
Started Aug 06 07:48:26 PM PDT 24
Finished Aug 06 07:48:27 PM PDT 24
Peak memory 203856 kb
Host smart-0bd49059-fd0f-46c3-bb6f-e65fb3449f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89044772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.89044772
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1257460338
Short name T1021
Test name
Test status
Simulation time 2051606568 ps
CPU time 4.18 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 215180 kb
Host smart-2fc53572-f9d3-473f-8df7-4185195a2586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257460338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1257460338
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.251922629
Short name T93
Test name
Test status
Simulation time 36578112 ps
CPU time 1.81 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 207040 kb
Host smart-8c243de3-2a78-4f6d-b285-908e92cf49c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251922629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.251922629
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2334737698
Short name T1056
Test name
Test status
Simulation time 40461270 ps
CPU time 2.72 seconds
Started Aug 06 07:48:22 PM PDT 24
Finished Aug 06 07:48:25 PM PDT 24
Peak memory 217616 kb
Host smart-6f62fa78-3625-4fbb-a95a-9c6fd18afa38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334737698 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2334737698
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1024912525
Short name T108
Test name
Test status
Simulation time 40099738 ps
CPU time 2.52 seconds
Started Aug 06 07:48:24 PM PDT 24
Finished Aug 06 07:48:27 PM PDT 24
Peak memory 215152 kb
Host smart-3539767b-7f51-403c-b809-9efe17d93b0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024912525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1024912525
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4490425
Short name T1015
Test name
Test status
Simulation time 14228712 ps
CPU time 0.7 seconds
Started Aug 06 07:48:26 PM PDT 24
Finished Aug 06 07:48:27 PM PDT 24
Peak memory 203616 kb
Host smart-93c227c9-78f4-4a5f-866e-e38b223349ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4490425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.4490425
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2539895962
Short name T1103
Test name
Test status
Simulation time 212702724 ps
CPU time 3.28 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:30 PM PDT 24
Peak memory 216240 kb
Host smart-d43da690-7311-402a-ae53-e4cdc95d1c86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539895962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2539895962
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1981133428
Short name T1111
Test name
Test status
Simulation time 306770773 ps
CPU time 2.25 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 215100 kb
Host smart-6163798a-0049-407a-9334-d2645d85f57c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981133428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1981133428
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2787738554
Short name T1067
Test name
Test status
Simulation time 1332663882 ps
CPU time 7.77 seconds
Started Aug 06 07:48:26 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 215564 kb
Host smart-e3633293-c480-4840-b963-eaacf02df7b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787738554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2787738554
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.240377264
Short name T1050
Test name
Test status
Simulation time 103455993 ps
CPU time 2.7 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 216316 kb
Host smart-b8b8d210-7e56-4d54-a6ca-acc848427cda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240377264 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.240377264
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.669814974
Short name T107
Test name
Test status
Simulation time 42110405 ps
CPU time 2.53 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 215184 kb
Host smart-e58bf6f0-200e-45b6-968e-183171a0f207
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669814974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.669814974
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.977075905
Short name T1096
Test name
Test status
Simulation time 41807194 ps
CPU time 0.74 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 203600 kb
Host smart-0480ad6c-d719-4fcb-a7dd-9e1e98adce4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977075905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.977075905
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2532202509
Short name T1012
Test name
Test status
Simulation time 203211187 ps
CPU time 2.86 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 215156 kb
Host smart-a1b8a679-361b-406e-b125-28bdad168302
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532202509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2532202509
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2467640313
Short name T1083
Test name
Test status
Simulation time 130494555 ps
CPU time 1.94 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 215280 kb
Host smart-5759cba7-3803-47cc-810f-692072dfd85e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467640313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2467640313
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1635821276
Short name T1126
Test name
Test status
Simulation time 784422845 ps
CPU time 17 seconds
Started Aug 06 07:48:24 PM PDT 24
Finished Aug 06 07:48:41 PM PDT 24
Peak memory 215272 kb
Host smart-e7c939d7-1dd3-4a60-bf5c-ad14a515d493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635821276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1635821276
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.275414198
Short name T1051
Test name
Test status
Simulation time 414243360 ps
CPU time 2.5 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 216860 kb
Host smart-3fa4ac18-a183-4c83-8109-36441e734e53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275414198 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.275414198
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3896825781
Short name T1127
Test name
Test status
Simulation time 66996186 ps
CPU time 1.82 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 215148 kb
Host smart-1cc67979-2b97-434d-8fec-34beb922c206
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896825781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3896825781
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2704755565
Short name T1006
Test name
Test status
Simulation time 19664993 ps
CPU time 0.69 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:31 PM PDT 24
Peak memory 203696 kb
Host smart-b7618902-6640-4ec7-a018-9df2e1650cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704755565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2704755565
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2620857266
Short name T1043
Test name
Test status
Simulation time 57025213 ps
CPU time 1.86 seconds
Started Aug 06 07:48:29 PM PDT 24
Finished Aug 06 07:48:31 PM PDT 24
Peak memory 215832 kb
Host smart-3a28a3d0-7575-4f0a-9db0-b16bb751bc1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620857266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2620857266
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3861906813
Short name T99
Test name
Test status
Simulation time 273057268 ps
CPU time 7.59 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:38 PM PDT 24
Peak memory 215212 kb
Host smart-f6f2789b-62f8-47d6-a876-951ea10304ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861906813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3861906813
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2925224453
Short name T1036
Test name
Test status
Simulation time 55815137 ps
CPU time 1.69 seconds
Started Aug 06 07:48:17 PM PDT 24
Finished Aug 06 07:48:19 PM PDT 24
Peak memory 216200 kb
Host smart-dcbd7901-5739-49c9-92a8-d047da634c33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925224453 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2925224453
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2682440405
Short name T1109
Test name
Test status
Simulation time 38890452 ps
CPU time 2.51 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 215132 kb
Host smart-adc6e710-824b-4d96-bdef-b4b25b4ea612
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682440405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2682440405
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1605141410
Short name T1107
Test name
Test status
Simulation time 12512762 ps
CPU time 0.71 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:24 PM PDT 24
Peak memory 203668 kb
Host smart-01d11461-8098-4fec-8607-05cdbcb3fdea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605141410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1605141410
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3936890647
Short name T1118
Test name
Test status
Simulation time 108390393 ps
CPU time 2.92 seconds
Started Aug 06 07:48:35 PM PDT 24
Finished Aug 06 07:48:38 PM PDT 24
Peak memory 215252 kb
Host smart-7d826fd1-d51f-433b-84c8-77efefb75e76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936890647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3936890647
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2386171897
Short name T92
Test name
Test status
Simulation time 79752846 ps
CPU time 3.49 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 215384 kb
Host smart-980afa9d-728c-4dd8-93b6-13dfe0a5482b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386171897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2386171897
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3625563021
Short name T1058
Test name
Test status
Simulation time 419282358 ps
CPU time 7.59 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:19 PM PDT 24
Peak memory 215136 kb
Host smart-af05d1d0-be7e-4dd5-9981-82f9c3b61b67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625563021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3625563021
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4189783440
Short name T109
Test name
Test status
Simulation time 1267505993 ps
CPU time 23.67 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 215128 kb
Host smart-6ff0a8ab-5a46-4808-b2d5-276259f27bbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189783440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4189783440
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1395332475
Short name T1076
Test name
Test status
Simulation time 603401854 ps
CPU time 3.64 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:16 PM PDT 24
Peak memory 218408 kb
Host smart-05a01be9-2140-4ea7-804d-afe1be087f9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395332475 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1395332475
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2518836931
Short name T1131
Test name
Test status
Simulation time 53678012 ps
CPU time 1.78 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 215148 kb
Host smart-5eb7fd0e-2e54-444b-bdcc-25c0032c10c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518836931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
518836931
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.500457941
Short name T1104
Test name
Test status
Simulation time 17028876 ps
CPU time 0.81 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 203656 kb
Host smart-847eb5bc-066f-4da8-bea8-cf10e274e83e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500457941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.500457941
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1481571368
Short name T114
Test name
Test status
Simulation time 528264391 ps
CPU time 1.58 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 215160 kb
Host smart-69ee090d-f530-44e0-83e3-231732886691
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481571368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1481571368
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.900711434
Short name T1022
Test name
Test status
Simulation time 50550493 ps
CPU time 0.64 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 203608 kb
Host smart-b0e7f1dd-33a3-4cae-a54a-4b024083104e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900711434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.900711434
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3153155228
Short name T146
Test name
Test status
Simulation time 891771561 ps
CPU time 4.57 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:17 PM PDT 24
Peak memory 215120 kb
Host smart-59da516e-2460-4d89-a6bc-c398fa48ce0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153155228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3153155228
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.536389843
Short name T173
Test name
Test status
Simulation time 3349439325 ps
CPU time 22.55 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 215276 kb
Host smart-b4e937a8-8b07-4d5c-8128-ca77214eb1bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536389843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.536389843
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1799480042
Short name T1105
Test name
Test status
Simulation time 16888331 ps
CPU time 0.75 seconds
Started Aug 06 07:48:29 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 203700 kb
Host smart-c05ae037-ee6a-4bf9-92f9-848b5f5d8c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799480042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1799480042
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3518257586
Short name T1097
Test name
Test status
Simulation time 31517799 ps
CPU time 0.74 seconds
Started Aug 06 07:48:28 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 203996 kb
Host smart-725cee9e-3e8a-4ef3-8811-b9a303ec1f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518257586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3518257586
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4186716400
Short name T1084
Test name
Test status
Simulation time 31882076 ps
CPU time 0.75 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 203668 kb
Host smart-bec13f9d-53d7-4000-a6bd-431cb1c54d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186716400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4186716400
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.458432065
Short name T1011
Test name
Test status
Simulation time 11398400 ps
CPU time 0.7 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:25 PM PDT 24
Peak memory 203640 kb
Host smart-4d1ccae8-cb39-4c5d-9d38-5d01264f11ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458432065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.458432065
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2752286582
Short name T1018
Test name
Test status
Simulation time 73372125 ps
CPU time 0.75 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 203664 kb
Host smart-c6b2a673-a2f2-475a-8763-325f314b6905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752286582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2752286582
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.505418209
Short name T1085
Test name
Test status
Simulation time 15188778 ps
CPU time 0.79 seconds
Started Aug 06 07:48:32 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 203660 kb
Host smart-5864e647-bd29-45a7-b5fa-87fefbe9955b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505418209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.505418209
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1168224927
Short name T1061
Test name
Test status
Simulation time 93867993 ps
CPU time 0.76 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 203660 kb
Host smart-6befbc4e-e816-44fc-8be9-31904da2685b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168224927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1168224927
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1372100870
Short name T1059
Test name
Test status
Simulation time 45360655 ps
CPU time 0.69 seconds
Started Aug 06 07:48:36 PM PDT 24
Finished Aug 06 07:48:37 PM PDT 24
Peak memory 203688 kb
Host smart-38d3a062-3f36-4280-8dd6-63716bb26dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372100870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1372100870
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2526173296
Short name T1008
Test name
Test status
Simulation time 11890640 ps
CPU time 0.72 seconds
Started Aug 06 07:48:35 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 203692 kb
Host smart-c96229f5-8fbf-4852-8d4e-a877036eb376
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526173296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2526173296
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2371816057
Short name T1066
Test name
Test status
Simulation time 37616786 ps
CPU time 0.74 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:24 PM PDT 24
Peak memory 203680 kb
Host smart-04fa9a17-ae9e-4945-83f0-3f49a1795c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371816057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2371816057
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3691989147
Short name T106
Test name
Test status
Simulation time 4467603378 ps
CPU time 23.91 seconds
Started Aug 06 07:48:14 PM PDT 24
Finished Aug 06 07:48:38 PM PDT 24
Peak memory 206968 kb
Host smart-562f3c92-3c71-4359-ae97-2f6d11539b1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691989147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3691989147
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1011253480
Short name T1110
Test name
Test status
Simulation time 1887117618 ps
CPU time 25.47 seconds
Started Aug 06 07:48:14 PM PDT 24
Finished Aug 06 07:48:39 PM PDT 24
Peak memory 215112 kb
Host smart-64b88e8d-ce80-4d75-9f53-9b78fc8e3315
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011253480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1011253480
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3550924107
Short name T79
Test name
Test status
Simulation time 52781298 ps
CPU time 1.49 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 206904 kb
Host smart-29cc2c6a-7577-446f-9564-11c355d09554
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550924107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3550924107
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.48217238
Short name T1033
Test name
Test status
Simulation time 36569840 ps
CPU time 2.24 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 216940 kb
Host smart-9f7deec4-0bf8-48ad-8ac1-47f2b096e2c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48217238 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.48217238
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.342851930
Short name T1123
Test name
Test status
Simulation time 337064732 ps
CPU time 2.54 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 207156 kb
Host smart-781e62df-149d-4636-8f05-c7dbbdf0bce0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342851930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.342851930
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1636989684
Short name T1010
Test name
Test status
Simulation time 11720463 ps
CPU time 0.76 seconds
Started Aug 06 07:48:14 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 204192 kb
Host smart-a01d4972-058b-4751-8e47-d7478d0e3090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636989684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
636989684
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3657188412
Short name T112
Test name
Test status
Simulation time 95196734 ps
CPU time 2.02 seconds
Started Aug 06 07:48:14 PM PDT 24
Finished Aug 06 07:48:16 PM PDT 24
Peak memory 215348 kb
Host smart-bc0f4d52-c0fc-4a5b-9a46-fd1b6459b361
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657188412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3657188412
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3679485556
Short name T1040
Test name
Test status
Simulation time 10715179 ps
CPU time 0.67 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 203916 kb
Host smart-e1e60e99-9ac2-4002-bdbe-dd246eb6918e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679485556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3679485556
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.399825387
Short name T161
Test name
Test status
Simulation time 481563815 ps
CPU time 2.73 seconds
Started Aug 06 07:48:14 PM PDT 24
Finished Aug 06 07:48:17 PM PDT 24
Peak memory 215144 kb
Host smart-0cacd0cd-5c88-46ba-a086-04a9fe748a4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399825387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.399825387
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2586434450
Short name T1099
Test name
Test status
Simulation time 63486118 ps
CPU time 2.22 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 215400 kb
Host smart-f18b7df0-ce97-4964-91da-6c7578e33298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586434450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
586434450
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3638155734
Short name T1038
Test name
Test status
Simulation time 1423529121 ps
CPU time 13.96 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 215564 kb
Host smart-54bbe430-689c-4cf3-8424-d2d6ea941724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638155734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3638155734
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2187826017
Short name T1095
Test name
Test status
Simulation time 40744882 ps
CPU time 0.74 seconds
Started Aug 06 07:48:35 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 203688 kb
Host smart-739da251-ffcd-4c9c-9dd1-7d76bd8922f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187826017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2187826017
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2450304849
Short name T1035
Test name
Test status
Simulation time 51191140 ps
CPU time 0.69 seconds
Started Aug 06 07:48:34 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 203684 kb
Host smart-c028fef0-d6e1-41ea-b885-401d9f2b57e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450304849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2450304849
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2524746900
Short name T1020
Test name
Test status
Simulation time 15404119 ps
CPU time 0.77 seconds
Started Aug 06 07:48:35 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 203688 kb
Host smart-d21b9d36-6b66-47dd-87f7-f7c5f01ffa7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524746900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2524746900
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3518602999
Short name T1090
Test name
Test status
Simulation time 38955637 ps
CPU time 0.74 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 203656 kb
Host smart-d4f837a1-9330-4017-a0ed-e786976a75c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518602999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3518602999
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3687080199
Short name T1053
Test name
Test status
Simulation time 16929733 ps
CPU time 0.77 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 203616 kb
Host smart-2c1b3d24-9575-4af2-a89d-56989df88884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687080199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3687080199
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2510586690
Short name T1080
Test name
Test status
Simulation time 24412308 ps
CPU time 0.74 seconds
Started Aug 06 07:48:44 PM PDT 24
Finished Aug 06 07:48:45 PM PDT 24
Peak memory 203676 kb
Host smart-b7c19440-a401-4fc9-a871-661fbe1198e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510586690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2510586690
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1398706907
Short name T1065
Test name
Test status
Simulation time 19261403 ps
CPU time 0.77 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 203688 kb
Host smart-036d36a8-93ba-45fa-922c-9a42859a4bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398706907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1398706907
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3560564186
Short name T1069
Test name
Test status
Simulation time 12342825 ps
CPU time 0.7 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 203692 kb
Host smart-475a235a-a7c0-472a-8d1e-8fcdfb5f9cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560564186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3560564186
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.785813485
Short name T1101
Test name
Test status
Simulation time 12062779 ps
CPU time 0.72 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 203948 kb
Host smart-4be8991e-3e69-4b2d-9b9f-2a88de661bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785813485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.785813485
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1320140741
Short name T1072
Test name
Test status
Simulation time 15501282 ps
CPU time 0.69 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 203652 kb
Host smart-f7352986-dded-4668-b8b5-954ab2a13133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320140741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1320140741
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3976077890
Short name T1054
Test name
Test status
Simulation time 1995448557 ps
CPU time 9.2 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 206860 kb
Host smart-8df51dad-612e-4a93-ac07-a61a441e53ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976077890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3976077890
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3523697464
Short name T1063
Test name
Test status
Simulation time 5026490887 ps
CPU time 25.78 seconds
Started Aug 06 07:48:20 PM PDT 24
Finished Aug 06 07:48:46 PM PDT 24
Peak memory 206988 kb
Host smart-8d4bde9e-2921-4d74-aaf6-6f4a3d91ac33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523697464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3523697464
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.546474755
Short name T80
Test name
Test status
Simulation time 16215895 ps
CPU time 0.92 seconds
Started Aug 06 07:48:20 PM PDT 24
Finished Aug 06 07:48:21 PM PDT 24
Peak memory 206720 kb
Host smart-4c5096e6-eb19-4cd9-98f5-24a5fce6db3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546474755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.546474755
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2142908417
Short name T1093
Test name
Test status
Simulation time 94280601 ps
CPU time 2.62 seconds
Started Aug 06 07:48:22 PM PDT 24
Finished Aug 06 07:48:25 PM PDT 24
Peak memory 216984 kb
Host smart-a89b97ed-c218-4517-8946-d6c9d2c519f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142908417 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2142908417
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.286107164
Short name T115
Test name
Test status
Simulation time 32622125 ps
CPU time 1.21 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:26 PM PDT 24
Peak memory 206856 kb
Host smart-194b305f-1041-4546-8e0a-c34c13885126
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286107164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.286107164
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2756427217
Short name T1128
Test name
Test status
Simulation time 13171980 ps
CPU time 0.71 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 203904 kb
Host smart-c151b304-acb5-49d6-972c-96eca23f4fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756427217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
756427217
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1545014260
Short name T1075
Test name
Test status
Simulation time 124066360 ps
CPU time 1.26 seconds
Started Aug 06 07:48:22 PM PDT 24
Finished Aug 06 07:48:23 PM PDT 24
Peak memory 215088 kb
Host smart-a9e43ca5-7b57-471a-b5dd-1a87a068e74f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545014260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1545014260
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.591035208
Short name T1048
Test name
Test status
Simulation time 19276822 ps
CPU time 0.67 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 203940 kb
Host smart-36cb3e20-fe76-4cb3-96c5-9ff323915228
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591035208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.591035208
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2417772190
Short name T1082
Test name
Test status
Simulation time 98560102 ps
CPU time 1.61 seconds
Started Aug 06 07:48:22 PM PDT 24
Finished Aug 06 07:48:24 PM PDT 24
Peak memory 215176 kb
Host smart-c60c343a-4423-49bb-94a3-b7572b877e28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417772190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2417772190
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3714671154
Short name T90
Test name
Test status
Simulation time 386456729 ps
CPU time 2.4 seconds
Started Aug 06 07:48:14 PM PDT 24
Finished Aug 06 07:48:16 PM PDT 24
Peak memory 215212 kb
Host smart-191bfb24-5f13-4077-a4df-c6c0a5a467da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714671154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
714671154
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2759445729
Short name T1029
Test name
Test status
Simulation time 270109044 ps
CPU time 7.57 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:20 PM PDT 24
Peak memory 223336 kb
Host smart-1a72d995-37ed-47f1-af59-0bf5af7bddee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759445729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2759445729
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3967005610
Short name T1074
Test name
Test status
Simulation time 18709693 ps
CPU time 0.74 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 204004 kb
Host smart-a5b2b877-3cd0-479a-a9cd-7f5c78ea36d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967005610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3967005610
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.777651241
Short name T1028
Test name
Test status
Simulation time 38949126 ps
CPU time 0.74 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 203680 kb
Host smart-088ce126-925d-41e9-b188-df094337c638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777651241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.777651241
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3082671674
Short name T1081
Test name
Test status
Simulation time 42446610 ps
CPU time 0.79 seconds
Started Aug 06 07:48:32 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 203672 kb
Host smart-020b2dc4-ab39-4fdc-ac0e-7a2cfa995b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082671674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3082671674
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3476788835
Short name T1032
Test name
Test status
Simulation time 18099388 ps
CPU time 0.76 seconds
Started Aug 06 07:48:44 PM PDT 24
Finished Aug 06 07:48:45 PM PDT 24
Peak memory 203984 kb
Host smart-837db4ea-ec05-4dae-bfba-a59784dba7a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476788835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3476788835
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2490432955
Short name T1102
Test name
Test status
Simulation time 13603182 ps
CPU time 0.74 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 203676 kb
Host smart-d1a0313e-1d6f-4ee9-a272-eec7f10f4c77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490432955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2490432955
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4099982695
Short name T1077
Test name
Test status
Simulation time 14750031 ps
CPU time 0.73 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:31 PM PDT 24
Peak memory 203708 kb
Host smart-7b2bbc7b-c37e-4e25-971a-315e8e07eb80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099982695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4099982695
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3241835258
Short name T1091
Test name
Test status
Simulation time 13979200 ps
CPU time 0.7 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 203648 kb
Host smart-c0f9bf31-59f2-401f-b1d9-1d765b7dda1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241835258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3241835258
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1274217398
Short name T1047
Test name
Test status
Simulation time 41297911 ps
CPU time 0.72 seconds
Started Aug 06 07:48:39 PM PDT 24
Finished Aug 06 07:48:40 PM PDT 24
Peak memory 203664 kb
Host smart-0d10ac6a-7b95-4cf6-92b6-779cbe6e666a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274217398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1274217398
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3092973271
Short name T1042
Test name
Test status
Simulation time 16661468 ps
CPU time 0.73 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 204032 kb
Host smart-c2a85ce4-7cf6-46a0-8e63-3c94a8ab0359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092973271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3092973271
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3196698898
Short name T1014
Test name
Test status
Simulation time 73934539 ps
CPU time 0.8 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 203940 kb
Host smart-b5e4cbe6-bce1-4824-afe5-dd48dc71b832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196698898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3196698898
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.301934577
Short name T1117
Test name
Test status
Simulation time 27016793 ps
CPU time 1.69 seconds
Started Aug 06 07:48:20 PM PDT 24
Finished Aug 06 07:48:22 PM PDT 24
Peak memory 215152 kb
Host smart-a3b405ac-7f5e-4014-bfd0-25b246ea005c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301934577 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.301934577
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.469762770
Short name T1108
Test name
Test status
Simulation time 19852643 ps
CPU time 1.34 seconds
Started Aug 06 07:48:21 PM PDT 24
Finished Aug 06 07:48:23 PM PDT 24
Peak memory 206960 kb
Host smart-a330d598-8e4a-4d86-99ef-6bceec9e084d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469762770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.469762770
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.270203660
Short name T1112
Test name
Test status
Simulation time 13884028 ps
CPU time 0.69 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:24 PM PDT 24
Peak memory 203672 kb
Host smart-b57a39a2-c557-404a-b354-8780d2b176ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270203660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.270203660
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2546087827
Short name T1100
Test name
Test status
Simulation time 131340601 ps
CPU time 2.83 seconds
Started Aug 06 07:48:20 PM PDT 24
Finished Aug 06 07:48:23 PM PDT 24
Peak memory 215152 kb
Host smart-a4ef8506-5ac3-49e5-bd34-5ce5cdb59b79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546087827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2546087827
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3532227585
Short name T170
Test name
Test status
Simulation time 488522325 ps
CPU time 2.16 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:25 PM PDT 24
Peak memory 215476 kb
Host smart-8d43eac6-ca29-4e30-ac3e-5d5efc10f689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532227585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
532227585
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2814456442
Short name T98
Test name
Test status
Simulation time 808530445 ps
CPU time 21.82 seconds
Started Aug 06 07:48:19 PM PDT 24
Finished Aug 06 07:48:41 PM PDT 24
Peak memory 215180 kb
Host smart-5cbcb85b-6d51-4668-99f3-5afda4dc01bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814456442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2814456442
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2136423810
Short name T1057
Test name
Test status
Simulation time 615604186 ps
CPU time 3.62 seconds
Started Aug 06 07:48:24 PM PDT 24
Finished Aug 06 07:48:27 PM PDT 24
Peak memory 217304 kb
Host smart-90d20982-da8f-4996-82bf-fec69b920494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136423810 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2136423810
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.537624899
Short name T1086
Test name
Test status
Simulation time 68469683 ps
CPU time 2.02 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:27 PM PDT 24
Peak memory 215240 kb
Host smart-cafc4319-9f5b-4276-a72a-c03c5712c75a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537624899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.537624899
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4083371878
Short name T1122
Test name
Test status
Simulation time 14479088 ps
CPU time 0.74 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:25 PM PDT 24
Peak memory 203652 kb
Host smart-697a2497-06b5-4a13-a3bf-ef886be902a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083371878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
083371878
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2067341127
Short name T1013
Test name
Test status
Simulation time 45355645 ps
CPU time 2.63 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:25 PM PDT 24
Peak memory 215160 kb
Host smart-3366387d-feae-4050-9fb9-1fe94f73bce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067341127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2067341127
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3178884496
Short name T1071
Test name
Test status
Simulation time 3331805740 ps
CPU time 4.85 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:30 PM PDT 24
Peak memory 215440 kb
Host smart-e0cf1224-d50c-4757-9ff8-592f45be7ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178884496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
178884496
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1387002563
Short name T100
Test name
Test status
Simulation time 1151761110 ps
CPU time 20.06 seconds
Started Aug 06 07:48:21 PM PDT 24
Finished Aug 06 07:48:41 PM PDT 24
Peak memory 215888 kb
Host smart-1e53a8e2-c681-4879-a417-6831d13a1402
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387002563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1387002563
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3014782386
Short name T1068
Test name
Test status
Simulation time 39174339 ps
CPU time 2.52 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:26 PM PDT 24
Peak memory 217260 kb
Host smart-179e4f77-9a22-458e-8917-91c4c27f24ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014782386 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3014782386
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.554453912
Short name T1037
Test name
Test status
Simulation time 63641216 ps
CPU time 1.15 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:26 PM PDT 24
Peak memory 206856 kb
Host smart-d2e4b586-c8c8-4855-8dbb-a96bbe262fd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554453912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.554453912
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1617768579
Short name T1039
Test name
Test status
Simulation time 53299669 ps
CPU time 0.68 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:26 PM PDT 24
Peak memory 204188 kb
Host smart-b797b35c-a13f-47e8-af71-b16504ff2c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617768579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
617768579
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2063501758
Short name T1041
Test name
Test status
Simulation time 217587012 ps
CPU time 4.37 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:30 PM PDT 24
Peak memory 215188 kb
Host smart-5b076a1d-eb78-41fa-a65c-ba7dc6f77ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063501758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2063501758
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3135218028
Short name T1073
Test name
Test status
Simulation time 141635269 ps
CPU time 1.87 seconds
Started Aug 06 07:48:23 PM PDT 24
Finished Aug 06 07:48:25 PM PDT 24
Peak memory 215276 kb
Host smart-aa7ef9eb-8f07-4f11-9dcc-fc97a69bbf83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135218028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
135218028
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3586878058
Short name T1125
Test name
Test status
Simulation time 559958888 ps
CPU time 2.67 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 216772 kb
Host smart-eb79bb01-61d6-4060-addb-50ab3139eee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586878058 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3586878058
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.625981025
Short name T103
Test name
Test status
Simulation time 66565772 ps
CPU time 1.79 seconds
Started Aug 06 07:48:29 PM PDT 24
Finished Aug 06 07:48:31 PM PDT 24
Peak memory 215124 kb
Host smart-8831f4c7-7a46-4d9b-a148-6c67966368a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625981025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.625981025
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1749261502
Short name T1049
Test name
Test status
Simulation time 84925435 ps
CPU time 0.69 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 203628 kb
Host smart-846896a7-a7b9-43de-af60-90409c3429ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749261502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
749261502
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.918985404
Short name T1025
Test name
Test status
Simulation time 120161564 ps
CPU time 2.76 seconds
Started Aug 06 07:48:26 PM PDT 24
Finished Aug 06 07:48:29 PM PDT 24
Peak memory 215128 kb
Host smart-d4859946-2dbc-4bf7-82e7-45a35e893b00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918985404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.918985404
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2882383904
Short name T86
Test name
Test status
Simulation time 91179474 ps
CPU time 2.18 seconds
Started Aug 06 07:48:27 PM PDT 24
Finished Aug 06 07:48:30 PM PDT 24
Peak memory 215208 kb
Host smart-81f1f5bf-c8f2-46d4-9bfa-f023b194cd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882383904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
882383904
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2998632934
Short name T1034
Test name
Test status
Simulation time 200382113 ps
CPU time 12.71 seconds
Started Aug 06 07:48:26 PM PDT 24
Finished Aug 06 07:48:38 PM PDT 24
Peak memory 215236 kb
Host smart-e5ffb1cb-0433-4d46-885b-ac9e7edb268e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998632934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2998632934
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3884697148
Short name T1046
Test name
Test status
Simulation time 204408149 ps
CPU time 3.75 seconds
Started Aug 06 07:48:32 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 217556 kb
Host smart-7641a02d-a288-4026-ac58-83660766cccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884697148 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3884697148
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2937601060
Short name T1092
Test name
Test status
Simulation time 286837321 ps
CPU time 1.91 seconds
Started Aug 06 07:48:25 PM PDT 24
Finished Aug 06 07:48:27 PM PDT 24
Peak memory 215108 kb
Host smart-af7cf94f-4e94-4e7f-b4d2-3eed3e35dfb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937601060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
937601060
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.466859650
Short name T1019
Test name
Test status
Simulation time 61562722 ps
CPU time 0.75 seconds
Started Aug 06 07:48:21 PM PDT 24
Finished Aug 06 07:48:22 PM PDT 24
Peak memory 203648 kb
Host smart-6dd92862-c062-4379-a4e4-7992d15aac23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466859650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.466859650
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3097657313
Short name T1064
Test name
Test status
Simulation time 27630878 ps
CPU time 1.78 seconds
Started Aug 06 07:48:26 PM PDT 24
Finished Aug 06 07:48:27 PM PDT 24
Peak memory 215012 kb
Host smart-b2f7a911-67a3-4840-945f-3af3f11c2112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097657313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3097657313
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1603986916
Short name T169
Test name
Test status
Simulation time 416698412 ps
CPU time 4.92 seconds
Started Aug 06 07:48:26 PM PDT 24
Finished Aug 06 07:48:31 PM PDT 24
Peak memory 215236 kb
Host smart-2d642319-b99f-4fe0-bb51-bbf5a943b666
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603986916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
603986916
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2190222862
Short name T89
Test name
Test status
Simulation time 207181691 ps
CPU time 7 seconds
Started Aug 06 07:48:29 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 215136 kb
Host smart-b09e68b2-3f51-494e-b071-c47fab205755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190222862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2190222862
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3143490377
Short name T684
Test name
Test status
Simulation time 79844001 ps
CPU time 0.73 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:51:58 PM PDT 24
Peak memory 206140 kb
Host smart-9b1098d6-edb3-46cb-b990-f4762f9a45fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143490377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
143490377
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3925915017
Short name T836
Test name
Test status
Simulation time 18450556 ps
CPU time 0.81 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 205924 kb
Host smart-ad4f3357-ba8a-4e17-ba11-43d7cd4b8714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925915017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3925915017
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2333865993
Short name T777
Test name
Test status
Simulation time 42641520224 ps
CPU time 418.34 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:58:48 PM PDT 24
Peak memory 249848 kb
Host smart-20cd1b35-a036-4643-917c-832d7a596938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333865993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2333865993
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2865175972
Short name T772
Test name
Test status
Simulation time 1625028012 ps
CPU time 17.24 seconds
Started Aug 06 07:52:10 PM PDT 24
Finished Aug 06 07:52:28 PM PDT 24
Peak memory 233160 kb
Host smart-b7ebb1bb-97e4-4c95-81f6-1139791f97b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865175972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2865175972
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3882734688
Short name T990
Test name
Test status
Simulation time 21807753547 ps
CPU time 54.04 seconds
Started Aug 06 07:52:11 PM PDT 24
Finished Aug 06 07:53:05 PM PDT 24
Peak memory 236096 kb
Host smart-caeefc9d-8cc5-460f-bf7c-26f7e9aac9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882734688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3882734688
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1532736015
Short name T658
Test name
Test status
Simulation time 1931429930 ps
CPU time 17.31 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:52:04 PM PDT 24
Peak memory 232984 kb
Host smart-5a489196-4476-4784-b434-2eb56c9d1922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532736015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1532736015
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.979158433
Short name T870
Test name
Test status
Simulation time 42490186 ps
CPU time 2.51 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:01 PM PDT 24
Peak memory 233172 kb
Host smart-7b874e01-ed70-4ee6-99ef-3718ad2dec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979158433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.979158433
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2942392847
Short name T264
Test name
Test status
Simulation time 81511691 ps
CPU time 2.5 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 224904 kb
Host smart-212d2db1-c847-4251-8db9-dc4576aa937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942392847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2942392847
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3628811974
Short name T774
Test name
Test status
Simulation time 2521088485 ps
CPU time 14.09 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:52:03 PM PDT 24
Peak memory 225052 kb
Host smart-ae910fc0-d4c6-44d0-bea1-724b072cedc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628811974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3628811974
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2628973656
Short name T494
Test name
Test status
Simulation time 237849242 ps
CPU time 5.53 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:54 PM PDT 24
Peak memory 222988 kb
Host smart-577b6a62-cbea-4981-9d9b-6324f2f72c88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2628973656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2628973656
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1048400921
Short name T75
Test name
Test status
Simulation time 63806401 ps
CPU time 1.07 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:01 PM PDT 24
Peak memory 236408 kb
Host smart-4ea61450-4786-40b2-b74d-4d7cb5911d8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048400921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1048400921
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2166513660
Short name T53
Test name
Test status
Simulation time 72934470658 ps
CPU time 510.05 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 08:00:30 PM PDT 24
Peak memory 270820 kb
Host smart-2db0303e-a5b5-4e8c-a8de-2d49d7ea8dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166513660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2166513660
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4155965234
Short name T903
Test name
Test status
Simulation time 2878907514 ps
CPU time 28.15 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:52:17 PM PDT 24
Peak memory 216740 kb
Host smart-8a5670b1-da2a-4e21-a8c1-7a3ae1c7e7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155965234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4155965234
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.103237643
Short name T937
Test name
Test status
Simulation time 2796137082 ps
CPU time 6.63 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:55 PM PDT 24
Peak memory 216732 kb
Host smart-e8aa7ff8-f72d-453d-b10e-cfa145a4a60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103237643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.103237643
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2253873668
Short name T530
Test name
Test status
Simulation time 43525293 ps
CPU time 1.1 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:49 PM PDT 24
Peak memory 216752 kb
Host smart-20a1a062-8794-4f85-bcf3-aeee54b0ce52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253873668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2253873668
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1806083286
Short name T569
Test name
Test status
Simulation time 179671115 ps
CPU time 0.76 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:51:59 PM PDT 24
Peak memory 206708 kb
Host smart-eeb45914-c255-464c-bc53-deeabb6c2de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806083286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1806083286
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.85348834
Short name T840
Test name
Test status
Simulation time 8629588889 ps
CPU time 11.67 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:52:00 PM PDT 24
Peak memory 233224 kb
Host smart-6eb11149-048c-4347-b010-caef1ed78884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85348834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.85348834
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2415521618
Short name T347
Test name
Test status
Simulation time 36444363 ps
CPU time 0.68 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:54 PM PDT 24
Peak memory 205824 kb
Host smart-356f569f-fbbf-4f2c-be7b-cc093767fbb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415521618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
415521618
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2065977339
Short name T734
Test name
Test status
Simulation time 162271827 ps
CPU time 2.58 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 224720 kb
Host smart-01f2162e-43fb-4d30-95c5-b7bec4ade2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065977339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2065977339
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.499137092
Short name T770
Test name
Test status
Simulation time 16798892 ps
CPU time 0.77 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 207004 kb
Host smart-cb0ae4e6-2a35-4664-9eac-53197f70dc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499137092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.499137092
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4219570078
Short name T242
Test name
Test status
Simulation time 5489717167 ps
CPU time 52.86 seconds
Started Aug 06 07:52:07 PM PDT 24
Finished Aug 06 07:53:00 PM PDT 24
Peak memory 252508 kb
Host smart-c974ed82-ee31-4249-8532-6b1b8653691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219570078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4219570078
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.438614321
Short name T989
Test name
Test status
Simulation time 87051208 ps
CPU time 0.82 seconds
Started Aug 06 07:51:54 PM PDT 24
Finished Aug 06 07:51:55 PM PDT 24
Peak memory 217744 kb
Host smart-7b3e09df-194e-47e8-b24c-6fd174e706ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438614321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.438614321
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2595530930
Short name T587
Test name
Test status
Simulation time 29655329204 ps
CPU time 56.22 seconds
Started Aug 06 07:51:54 PM PDT 24
Finished Aug 06 07:52:50 PM PDT 24
Peak memory 233280 kb
Host smart-43028d51-6b46-463a-b4aa-669652e943b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595530930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2595530930
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3225981778
Short name T595
Test name
Test status
Simulation time 3342355822 ps
CPU time 46.04 seconds
Started Aug 06 07:51:46 PM PDT 24
Finished Aug 06 07:52:32 PM PDT 24
Peak memory 241464 kb
Host smart-ad597e8f-dc8b-47ca-a05d-6a67f2efa910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225981778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3225981778
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1668890233
Short name T567
Test name
Test status
Simulation time 4112542675 ps
CPU time 21.08 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:52:15 PM PDT 24
Peak memory 235780 kb
Host smart-fa0dd49a-79cd-4b66-8bb3-bbfb1726c5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668890233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1668890233
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2699801013
Short name T426
Test name
Test status
Simulation time 677123981 ps
CPU time 8.07 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:52:06 PM PDT 24
Peak memory 233132 kb
Host smart-17ecfa25-4606-4181-8ce0-839a559dd81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699801013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2699801013
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3788759325
Short name T781
Test name
Test status
Simulation time 11148566691 ps
CPU time 79.79 seconds
Started Aug 06 07:52:03 PM PDT 24
Finished Aug 06 07:53:22 PM PDT 24
Peak memory 234356 kb
Host smart-ef96d43c-b627-45d4-afa9-a6760e874cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788759325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3788759325
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1831214637
Short name T696
Test name
Test status
Simulation time 23472165526 ps
CPU time 11.02 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:52:17 PM PDT 24
Peak memory 233152 kb
Host smart-223f6c9a-248a-4826-a674-5d1074b5448d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831214637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1831214637
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1452775224
Short name T497
Test name
Test status
Simulation time 168706605 ps
CPU time 2.37 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:53 PM PDT 24
Peak memory 224956 kb
Host smart-2d8222f8-43bd-4fd2-85e2-2d55cdbbbb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452775224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1452775224
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3701169943
Short name T825
Test name
Test status
Simulation time 204365863 ps
CPU time 5.3 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:58 PM PDT 24
Peak memory 223592 kb
Host smart-5086e97d-d869-493a-8017-402a77a18883
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3701169943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3701169943
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1539198827
Short name T613
Test name
Test status
Simulation time 120868179 ps
CPU time 1.15 seconds
Started Aug 06 07:52:07 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 207656 kb
Host smart-9a82369d-7d25-484b-9bf7-50be51de5677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539198827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1539198827
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3588387195
Short name T378
Test name
Test status
Simulation time 23538287 ps
CPU time 0.73 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:51:59 PM PDT 24
Peak memory 206452 kb
Host smart-793409d7-5619-4d1d-974a-9615d541b963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588387195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3588387195
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2939767965
Short name T369
Test name
Test status
Simulation time 23188292062 ps
CPU time 16.46 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:52:07 PM PDT 24
Peak memory 216648 kb
Host smart-32aa33ac-8249-4110-9408-4748fe5fc21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939767965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2939767965
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2176290185
Short name T835
Test name
Test status
Simulation time 188777008 ps
CPU time 1.7 seconds
Started Aug 06 07:52:03 PM PDT 24
Finished Aug 06 07:52:04 PM PDT 24
Peak memory 216600 kb
Host smart-8fbef4ff-3187-4f9f-b3c6-fe7c56386a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176290185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2176290185
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.525018658
Short name T865
Test name
Test status
Simulation time 92704393 ps
CPU time 0.93 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:54 PM PDT 24
Peak memory 206376 kb
Host smart-33377c10-03ac-46fe-850b-fd9a8b4b8880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525018658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.525018658
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.272418805
Short name T761
Test name
Test status
Simulation time 3709888904 ps
CPU time 6.65 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:58 PM PDT 24
Peak memory 225044 kb
Host smart-efd0a328-f0d2-46c0-bc27-913c2a152eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272418805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.272418805
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4002742014
Short name T757
Test name
Test status
Simulation time 13641268 ps
CPU time 0.72 seconds
Started Aug 06 07:52:15 PM PDT 24
Finished Aug 06 07:52:16 PM PDT 24
Peak memory 205744 kb
Host smart-9b9a6f75-391d-473b-bdbf-e5158a981135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002742014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4002742014
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1249568373
Short name T244
Test name
Test status
Simulation time 83021021 ps
CPU time 2.3 seconds
Started Aug 06 07:52:10 PM PDT 24
Finished Aug 06 07:52:13 PM PDT 24
Peak memory 224972 kb
Host smart-2952610b-ff39-4e4a-8a32-8f273e2b9603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249568373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1249568373
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4188428429
Short name T484
Test name
Test status
Simulation time 14535073 ps
CPU time 0.73 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:52:05 PM PDT 24
Peak memory 206288 kb
Host smart-7deecef2-b22b-441a-aaa5-ce133aa1f25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188428429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4188428429
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1087758370
Short name T288
Test name
Test status
Simulation time 252857948999 ps
CPU time 496.17 seconds
Started Aug 06 07:52:12 PM PDT 24
Finished Aug 06 08:00:29 PM PDT 24
Peak memory 252236 kb
Host smart-03319005-dc0f-49d7-b9e4-d5ee160fe31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087758370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1087758370
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.84704597
Short name T679
Test name
Test status
Simulation time 3097923055 ps
CPU time 16.29 seconds
Started Aug 06 07:52:11 PM PDT 24
Finished Aug 06 07:52:28 PM PDT 24
Peak memory 225048 kb
Host smart-af014d50-8b0b-4be1-b46b-67fde762fa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84704597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.84704597
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3438806878
Short name T702
Test name
Test status
Simulation time 83770219687 ps
CPU time 732.89 seconds
Started Aug 06 07:52:09 PM PDT 24
Finished Aug 06 08:04:22 PM PDT 24
Peak memory 268016 kb
Host smart-0b7585c2-eb43-4422-b1c9-0d0495fae6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438806878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3438806878
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3266536378
Short name T623
Test name
Test status
Simulation time 535362244 ps
CPU time 11.57 seconds
Started Aug 06 07:52:01 PM PDT 24
Finished Aug 06 07:52:13 PM PDT 24
Peak memory 224964 kb
Host smart-acb710bb-d4d3-49ac-aa65-a6c118f841e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266536378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3266536378
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.194931501
Short name T527
Test name
Test status
Simulation time 3499645731 ps
CPU time 62.63 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:53:05 PM PDT 24
Peak memory 265808 kb
Host smart-7c6727c3-0991-40c0-bcca-86fa17d9905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194931501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.194931501
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.148234781
Short name T205
Test name
Test status
Simulation time 269835295 ps
CPU time 4.44 seconds
Started Aug 06 07:52:22 PM PDT 24
Finished Aug 06 07:52:26 PM PDT 24
Peak memory 224900 kb
Host smart-b494024d-822d-4770-b02a-b47f4f9c9fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148234781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.148234781
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1405524681
Short name T657
Test name
Test status
Simulation time 4305783581 ps
CPU time 46.73 seconds
Started Aug 06 07:52:10 PM PDT 24
Finished Aug 06 07:52:57 PM PDT 24
Peak memory 241192 kb
Host smart-afe52605-c266-41ec-ad96-afcd1c92d5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405524681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1405524681
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.590942093
Short name T882
Test name
Test status
Simulation time 732030036 ps
CPU time 3.17 seconds
Started Aug 06 07:52:09 PM PDT 24
Finished Aug 06 07:52:12 PM PDT 24
Peak memory 224984 kb
Host smart-0b38b2a1-393d-426c-99fd-51c44c19bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590942093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.590942093
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.722367827
Short name T802
Test name
Test status
Simulation time 3918803322 ps
CPU time 11.18 seconds
Started Aug 06 07:52:07 PM PDT 24
Finished Aug 06 07:52:18 PM PDT 24
Peak memory 238776 kb
Host smart-8bf5d8c6-a3e9-461c-9e7e-ec325e78990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722367827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.722367827
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1823900528
Short name T537
Test name
Test status
Simulation time 515095394 ps
CPU time 4.54 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:20 PM PDT 24
Peak memory 223616 kb
Host smart-889d1292-5785-44dc-a202-d5cbdd8bc9e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1823900528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1823900528
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3761145144
Short name T374
Test name
Test status
Simulation time 6251697487 ps
CPU time 18.84 seconds
Started Aug 06 07:52:13 PM PDT 24
Finished Aug 06 07:52:32 PM PDT 24
Peak memory 216812 kb
Host smart-11c8ba37-ff61-4b37-bfba-c0328b21d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761145144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3761145144
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3606755905
Short name T405
Test name
Test status
Simulation time 3047187505 ps
CPU time 6.66 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:06 PM PDT 24
Peak memory 216760 kb
Host smart-2c2b4dae-ac72-4447-a755-479e359a873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606755905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3606755905
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3705411936
Short name T892
Test name
Test status
Simulation time 224719251 ps
CPU time 5.19 seconds
Started Aug 06 07:52:08 PM PDT 24
Finished Aug 06 07:52:13 PM PDT 24
Peak memory 216620 kb
Host smart-342bc13d-3469-44b1-8fb7-b4d100620ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705411936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3705411936
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3189601594
Short name T348
Test name
Test status
Simulation time 15319695 ps
CPU time 0.66 seconds
Started Aug 06 07:52:12 PM PDT 24
Finished Aug 06 07:52:12 PM PDT 24
Peak memory 205948 kb
Host smart-b033987b-4c84-4824-980e-e08bf1c80fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189601594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3189601594
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2477440562
Short name T856
Test name
Test status
Simulation time 18900426030 ps
CPU time 30.34 seconds
Started Aug 06 07:52:14 PM PDT 24
Finished Aug 06 07:52:45 PM PDT 24
Peak memory 240976 kb
Host smart-2d360899-d228-4b4d-8eea-f5ba2af9a443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477440562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2477440562
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4058960367
Short name T686
Test name
Test status
Simulation time 44911661 ps
CPU time 0.71 seconds
Started Aug 06 07:52:30 PM PDT 24
Finished Aug 06 07:52:31 PM PDT 24
Peak memory 206192 kb
Host smart-becf4e35-7b34-4705-b198-4a19eb368ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058960367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4058960367
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2999217634
Short name T730
Test name
Test status
Simulation time 118736882 ps
CPU time 3.67 seconds
Started Aug 06 07:52:30 PM PDT 24
Finished Aug 06 07:52:34 PM PDT 24
Peak memory 224960 kb
Host smart-d8498112-babd-4b4f-a59d-568b86e69eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999217634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2999217634
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.265275055
Short name T601
Test name
Test status
Simulation time 67515961 ps
CPU time 0.73 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:17 PM PDT 24
Peak memory 205872 kb
Host smart-08017846-b3a5-47a4-9172-3e51258b88fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265275055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.265275055
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2956815674
Short name T40
Test name
Test status
Simulation time 93802797666 ps
CPU time 170.24 seconds
Started Aug 06 07:52:31 PM PDT 24
Finished Aug 06 07:55:22 PM PDT 24
Peak memory 252448 kb
Host smart-2f4050ee-7941-4b67-bbe9-cd81d68fc568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956815674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2956815674
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2279029322
Short name T310
Test name
Test status
Simulation time 6596452045 ps
CPU time 55.64 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:53:19 PM PDT 24
Peak memory 249860 kb
Host smart-a01ec29f-1808-4e64-947e-83fd2cd7c04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279029322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2279029322
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.787644956
Short name T368
Test name
Test status
Simulation time 30776301124 ps
CPU time 331.74 seconds
Started Aug 06 07:52:21 PM PDT 24
Finished Aug 06 07:57:52 PM PDT 24
Peak memory 263344 kb
Host smart-60718ad8-abb8-4002-9708-5ce119b256bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787644956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.787644956
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.22468766
Short name T652
Test name
Test status
Simulation time 2283353342 ps
CPU time 5.36 seconds
Started Aug 06 07:52:35 PM PDT 24
Finished Aug 06 07:52:40 PM PDT 24
Peak memory 235476 kb
Host smart-0c703dba-9a9e-4667-949a-0875ac73826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22468766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.22468766
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1756490431
Short name T592
Test name
Test status
Simulation time 12356900920 ps
CPU time 52.88 seconds
Started Aug 06 07:52:24 PM PDT 24
Finished Aug 06 07:53:17 PM PDT 24
Peak memory 256712 kb
Host smart-624a75a7-c6a8-4001-84d3-827c61580d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756490431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1756490431
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2285582946
Short name T388
Test name
Test status
Simulation time 72390123 ps
CPU time 2.34 seconds
Started Aug 06 07:52:01 PM PDT 24
Finished Aug 06 07:52:04 PM PDT 24
Peak memory 224692 kb
Host smart-b17d0b95-e555-421e-9468-fc25befc18f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285582946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2285582946
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1931140353
Short name T897
Test name
Test status
Simulation time 9439013178 ps
CPU time 28.05 seconds
Started Aug 06 07:52:11 PM PDT 24
Finished Aug 06 07:52:39 PM PDT 24
Peak memory 241340 kb
Host smart-6802628e-14be-4298-97a6-e63ccbc9b64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931140353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1931140353
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3586946073
Short name T799
Test name
Test status
Simulation time 10905643434 ps
CPU time 11.55 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:28 PM PDT 24
Peak memory 224972 kb
Host smart-9a0e55c7-70da-4148-bf5b-7bdd61b919e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586946073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3586946073
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.707606609
Short name T383
Test name
Test status
Simulation time 233385002 ps
CPU time 4.86 seconds
Started Aug 06 07:52:29 PM PDT 24
Finished Aug 06 07:52:35 PM PDT 24
Peak memory 223520 kb
Host smart-ceb413f0-bc51-4a60-9d26-f42f9416f3c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=707606609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.707606609
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.94626572
Short name T936
Test name
Test status
Simulation time 56723303134 ps
CPU time 259.17 seconds
Started Aug 06 07:52:29 PM PDT 24
Finished Aug 06 07:56:49 PM PDT 24
Peak memory 249672 kb
Host smart-454309ff-08df-44d7-a990-8b211a459203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94626572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress
_all.94626572
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.842838554
Short name T307
Test name
Test status
Simulation time 15804364016 ps
CPU time 43 seconds
Started Aug 06 07:52:30 PM PDT 24
Finished Aug 06 07:53:13 PM PDT 24
Peak memory 216616 kb
Host smart-da9b95b8-f7af-4598-8f43-6407a8653191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842838554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.842838554
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2220012262
Short name T469
Test name
Test status
Simulation time 3010005543 ps
CPU time 8.21 seconds
Started Aug 06 07:52:09 PM PDT 24
Finished Aug 06 07:52:18 PM PDT 24
Peak memory 216616 kb
Host smart-f2fa183d-6abf-4325-b743-1218a8c7f965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220012262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2220012262
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3979405219
Short name T354
Test name
Test status
Simulation time 49831533 ps
CPU time 0.66 seconds
Started Aug 06 07:52:09 PM PDT 24
Finished Aug 06 07:52:10 PM PDT 24
Peak memory 206048 kb
Host smart-d19c3271-121a-4260-bb5d-39c1d7a271b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979405219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3979405219
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2885004632
Short name T468
Test name
Test status
Simulation time 157963516 ps
CPU time 0.88 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:01 PM PDT 24
Peak memory 207340 kb
Host smart-e5361d06-f805-4a69-96d7-be3db0e32909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885004632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2885004632
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4188126946
Short name T700
Test name
Test status
Simulation time 333029752 ps
CPU time 4.27 seconds
Started Aug 06 07:52:30 PM PDT 24
Finished Aug 06 07:52:34 PM PDT 24
Peak memory 233124 kb
Host smart-04f1b185-3063-4de5-986b-2b2341503370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188126946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4188126946
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2115893672
Short name T857
Test name
Test status
Simulation time 55177052 ps
CPU time 0.76 seconds
Started Aug 06 07:52:22 PM PDT 24
Finished Aug 06 07:52:23 PM PDT 24
Peak memory 205240 kb
Host smart-85f9c9b2-1e68-4299-baac-367fb82b23a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115893672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2115893672
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2961095358
Short name T709
Test name
Test status
Simulation time 78410922 ps
CPU time 2.4 seconds
Started Aug 06 07:52:28 PM PDT 24
Finished Aug 06 07:52:31 PM PDT 24
Peak memory 224460 kb
Host smart-c3e91124-437f-4c26-b01d-c152ca879b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961095358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2961095358
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3932158580
Short name T64
Test name
Test status
Simulation time 28566624 ps
CPU time 0.83 seconds
Started Aug 06 07:52:32 PM PDT 24
Finished Aug 06 07:52:33 PM PDT 24
Peak memory 207328 kb
Host smart-108e01eb-7263-4539-92fd-9ca41410b45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932158580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3932158580
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3477980723
Short name T440
Test name
Test status
Simulation time 11712235 ps
CPU time 0.76 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:52:24 PM PDT 24
Peak memory 216156 kb
Host smart-2ea73218-7b53-4677-a04d-284f842fe198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477980723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3477980723
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1946822265
Short name T282
Test name
Test status
Simulation time 4896353649 ps
CPU time 109.11 seconds
Started Aug 06 07:52:30 PM PDT 24
Finished Aug 06 07:54:20 PM PDT 24
Peak memory 273588 kb
Host smart-2c119143-af34-4ecc-9ad6-82ec6622d9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946822265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1946822265
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3648297796
Short name T185
Test name
Test status
Simulation time 31286203322 ps
CPU time 112.45 seconds
Started Aug 06 07:52:22 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 241364 kb
Host smart-42941240-1157-45b7-a9df-e0bb467ba105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648297796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3648297796
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1052371550
Short name T216
Test name
Test status
Simulation time 1943391610 ps
CPU time 16.9 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:52:40 PM PDT 24
Peak memory 224880 kb
Host smart-cbdfda92-34bf-41b6-8b25-53e9232af4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052371550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1052371550
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1871812413
Short name T633
Test name
Test status
Simulation time 1375545103 ps
CPU time 9.7 seconds
Started Aug 06 07:52:29 PM PDT 24
Finished Aug 06 07:52:39 PM PDT 24
Peak memory 235452 kb
Host smart-13361e76-5071-4b68-a41d-feb91cbb02ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871812413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1871812413
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3109145934
Short name T236
Test name
Test status
Simulation time 759129883 ps
CPU time 5.41 seconds
Started Aug 06 07:52:24 PM PDT 24
Finished Aug 06 07:52:29 PM PDT 24
Peak memory 240572 kb
Host smart-293e5183-dcd9-4e06-a2c3-b039df15445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109145934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3109145934
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2108022740
Short name T246
Test name
Test status
Simulation time 1338715920 ps
CPU time 3.52 seconds
Started Aug 06 07:52:30 PM PDT 24
Finished Aug 06 07:52:33 PM PDT 24
Peak memory 224884 kb
Host smart-74c0a69c-f332-4d6c-887a-a806ecec7abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108022740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2108022740
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2718733447
Short name T361
Test name
Test status
Simulation time 1924156285 ps
CPU time 17.67 seconds
Started Aug 06 07:52:35 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 219696 kb
Host smart-132a69da-3f4e-43fc-8b43-f865e86bd4d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2718733447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2718733447
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1070029635
Short name T21
Test name
Test status
Simulation time 117356585 ps
CPU time 1.1 seconds
Started Aug 06 07:52:20 PM PDT 24
Finished Aug 06 07:52:21 PM PDT 24
Peak memory 207616 kb
Host smart-b277cdbb-a185-4228-b514-d61b8aac020a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070029635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1070029635
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3063573816
Short name T367
Test name
Test status
Simulation time 388632077 ps
CPU time 5.41 seconds
Started Aug 06 07:52:24 PM PDT 24
Finished Aug 06 07:52:29 PM PDT 24
Peak memory 216680 kb
Host smart-5e5c171e-f3fb-4dda-b54a-8d63c6bfc1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063573816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3063573816
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.148139268
Short name T431
Test name
Test status
Simulation time 11370858349 ps
CPU time 11.03 seconds
Started Aug 06 07:52:30 PM PDT 24
Finished Aug 06 07:52:42 PM PDT 24
Peak memory 216724 kb
Host smart-48dd04a9-60af-478b-a429-58284808d319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148139268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.148139268
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3704608693
Short name T738
Test name
Test status
Simulation time 24898319 ps
CPU time 0.9 seconds
Started Aug 06 07:52:21 PM PDT 24
Finished Aug 06 07:52:22 PM PDT 24
Peak memory 207104 kb
Host smart-37e94e82-e94e-46d7-ab8e-f85778567f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704608693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3704608693
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2194364022
Short name T749
Test name
Test status
Simulation time 134077106 ps
CPU time 0.72 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:52:24 PM PDT 24
Peak memory 206372 kb
Host smart-959c66f4-5eb4-4cb5-8186-bd9018264204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194364022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2194364022
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1709148271
Short name T8
Test name
Test status
Simulation time 7712580549 ps
CPU time 8.47 seconds
Started Aug 06 07:52:27 PM PDT 24
Finished Aug 06 07:52:36 PM PDT 24
Peak memory 224836 kb
Host smart-58f3ac03-d22b-45bb-84df-3a9960818cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709148271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1709148271
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3635899670
Short name T935
Test name
Test status
Simulation time 42135072 ps
CPU time 0.73 seconds
Started Aug 06 07:52:38 PM PDT 24
Finished Aug 06 07:52:39 PM PDT 24
Peak memory 205252 kb
Host smart-6703d3f2-1ebf-42e9-a00d-b5d3d0c05944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635899670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3635899670
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2455165337
Short name T826
Test name
Test status
Simulation time 10635822598 ps
CPU time 27.3 seconds
Started Aug 06 07:52:25 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 233056 kb
Host smart-2a7e5069-6cff-4fa3-acf8-1b5d5fd18b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455165337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2455165337
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.878580096
Short name T552
Test name
Test status
Simulation time 67193887 ps
CPU time 0.84 seconds
Started Aug 06 07:52:34 PM PDT 24
Finished Aug 06 07:52:34 PM PDT 24
Peak memory 207044 kb
Host smart-4f0547a5-ed3e-4f81-aa14-5b3ae588a10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878580096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.878580096
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2199573910
Short name T163
Test name
Test status
Simulation time 26694475942 ps
CPU time 104.15 seconds
Started Aug 06 07:52:36 PM PDT 24
Finished Aug 06 07:54:20 PM PDT 24
Peak memory 254676 kb
Host smart-4a8f4873-f9b4-416d-8c35-377c4110e05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199573910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2199573910
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4112690888
Short name T800
Test name
Test status
Simulation time 30219516207 ps
CPU time 271.34 seconds
Started Aug 06 07:52:32 PM PDT 24
Finished Aug 06 07:57:04 PM PDT 24
Peak memory 256048 kb
Host smart-5c7b270f-c24d-483c-b282-d9e8f3bca367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112690888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4112690888
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2685315264
Short name T47
Test name
Test status
Simulation time 1066171040 ps
CPU time 7.62 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:52:31 PM PDT 24
Peak memory 233124 kb
Host smart-74e34be6-db67-4f24-9a90-f8dbf5ddc080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685315264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2685315264
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.4275877677
Short name T521
Test name
Test status
Simulation time 3082047860 ps
CPU time 52.61 seconds
Started Aug 06 07:52:33 PM PDT 24
Finished Aug 06 07:53:25 PM PDT 24
Peak memory 251616 kb
Host smart-99f4edc4-d094-422e-95a6-369bc82ff41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275877677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.4275877677
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3359373929
Short name T866
Test name
Test status
Simulation time 302829170 ps
CPU time 5.49 seconds
Started Aug 06 07:52:28 PM PDT 24
Finished Aug 06 07:52:34 PM PDT 24
Peak memory 224840 kb
Host smart-bf0d4b75-aef9-4bee-a2ed-baeeca063d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359373929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3359373929
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.9789498
Short name T812
Test name
Test status
Simulation time 30438921189 ps
CPU time 35.56 seconds
Started Aug 06 07:52:36 PM PDT 24
Finished Aug 06 07:53:11 PM PDT 24
Peak memory 237260 kb
Host smart-f2c130f9-b778-4015-a599-4bb5d1fcde9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9789498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.9789498
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2658918690
Short name T703
Test name
Test status
Simulation time 1992181657 ps
CPU time 5.22 seconds
Started Aug 06 07:52:30 PM PDT 24
Finished Aug 06 07:52:36 PM PDT 24
Peak memory 241232 kb
Host smart-2b7e73cd-5a18-4a43-8e1e-917b79c7ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658918690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2658918690
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3544729341
Short name T247
Test name
Test status
Simulation time 25702310774 ps
CPU time 25.3 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:52:49 PM PDT 24
Peak memory 224976 kb
Host smart-110a30db-b1af-4abd-b001-854d18ad2620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544729341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3544729341
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.911623742
Short name T489
Test name
Test status
Simulation time 2272207796 ps
CPU time 12.39 seconds
Started Aug 06 07:52:32 PM PDT 24
Finished Aug 06 07:52:44 PM PDT 24
Peak memory 222572 kb
Host smart-469eb635-937b-4793-9f60-10324d5c0936
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=911623742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.911623742
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1979351825
Short name T466
Test name
Test status
Simulation time 273275240 ps
CPU time 1.02 seconds
Started Aug 06 07:52:42 PM PDT 24
Finished Aug 06 07:52:43 PM PDT 24
Peak memory 207448 kb
Host smart-0f307a40-a659-4366-a2f8-1d917549195a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979351825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1979351825
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3596550199
Short name T667
Test name
Test status
Simulation time 720812870 ps
CPU time 4.3 seconds
Started Aug 06 07:52:32 PM PDT 24
Finished Aug 06 07:52:37 PM PDT 24
Peak memory 216572 kb
Host smart-d434e6bb-005d-4f4d-b7a9-f467f060419a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596550199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3596550199
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.754257669
Short name T352
Test name
Test status
Simulation time 2809542823 ps
CPU time 5.2 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:52:28 PM PDT 24
Peak memory 216628 kb
Host smart-f1a2653d-c179-4e0e-90b8-0d25c566f237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754257669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.754257669
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3433319680
Short name T586
Test name
Test status
Simulation time 10626700 ps
CPU time 0.69 seconds
Started Aug 06 07:52:31 PM PDT 24
Finished Aug 06 07:52:31 PM PDT 24
Peak memory 206048 kb
Host smart-99452206-3a64-42e5-aaf6-affe8185cadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433319680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3433319680
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.27800783
Short name T474
Test name
Test status
Simulation time 49214030 ps
CPU time 0.85 seconds
Started Aug 06 07:52:34 PM PDT 24
Finished Aug 06 07:52:35 PM PDT 24
Peak memory 206412 kb
Host smart-77689f0d-a454-40bb-b444-a4432caf4d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27800783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.27800783
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4037308449
Short name T459
Test name
Test status
Simulation time 8950915995 ps
CPU time 10.34 seconds
Started Aug 06 07:52:34 PM PDT 24
Finished Aug 06 07:52:44 PM PDT 24
Peak memory 233196 kb
Host smart-7fe84ffd-246d-47d7-82e6-97e17e129f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037308449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4037308449
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1777179381
Short name T653
Test name
Test status
Simulation time 44897129 ps
CPU time 0.71 seconds
Started Aug 06 07:52:22 PM PDT 24
Finished Aug 06 07:52:23 PM PDT 24
Peak memory 205848 kb
Host smart-cd478e32-c041-471f-88e1-154cae0c8afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777179381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1777179381
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3414492165
Short name T636
Test name
Test status
Simulation time 77977621 ps
CPU time 2.25 seconds
Started Aug 06 07:52:31 PM PDT 24
Finished Aug 06 07:52:33 PM PDT 24
Peak memory 224792 kb
Host smart-71131a32-2125-414f-b062-3227d8b3e820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414492165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3414492165
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2892172068
Short name T960
Test name
Test status
Simulation time 44087276 ps
CPU time 0.71 seconds
Started Aug 06 07:52:39 PM PDT 24
Finished Aug 06 07:52:39 PM PDT 24
Peak memory 206268 kb
Host smart-4a034720-a515-4b5d-a0ba-be37e743cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892172068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2892172068
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3302221372
Short name T640
Test name
Test status
Simulation time 10917996044 ps
CPU time 72.46 seconds
Started Aug 06 07:52:26 PM PDT 24
Finished Aug 06 07:53:39 PM PDT 24
Peak memory 251932 kb
Host smart-212391e2-1536-4f16-a490-d296ee621c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302221372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3302221372
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1278031854
Short name T706
Test name
Test status
Simulation time 7734661703 ps
CPU time 78.08 seconds
Started Aug 06 07:52:34 PM PDT 24
Finished Aug 06 07:53:53 PM PDT 24
Peak memory 257824 kb
Host smart-61defda8-eb0d-47b4-adc3-078f03e10759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278031854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1278031854
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2126438336
Short name T444
Test name
Test status
Simulation time 231305794 ps
CPU time 2.88 seconds
Started Aug 06 07:52:34 PM PDT 24
Finished Aug 06 07:52:37 PM PDT 24
Peak memory 224832 kb
Host smart-83964fe0-0917-459d-9c50-dc01f2b44f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126438336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2126438336
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1881329638
Short name T648
Test name
Test status
Simulation time 36432710883 ps
CPU time 283.89 seconds
Started Aug 06 07:52:36 PM PDT 24
Finished Aug 06 07:57:20 PM PDT 24
Peak memory 260128 kb
Host smart-e02c0fe2-dd0d-4677-bc5b-cb8255e57188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881329638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1881329638
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.224774623
Short name T243
Test name
Test status
Simulation time 177070297 ps
CPU time 2.8 seconds
Started Aug 06 07:52:29 PM PDT 24
Finished Aug 06 07:52:32 PM PDT 24
Peak memory 233100 kb
Host smart-1638e546-f405-41a7-89d1-21e68b8dc37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224774623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.224774623
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.834672644
Short name T758
Test name
Test status
Simulation time 1647395302 ps
CPU time 13.2 seconds
Started Aug 06 07:52:34 PM PDT 24
Finished Aug 06 07:52:47 PM PDT 24
Peak memory 233032 kb
Host smart-f39554ba-d74b-412d-acd2-53fe48883d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834672644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.834672644
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.552296194
Short name T972
Test name
Test status
Simulation time 3469728158 ps
CPU time 8.88 seconds
Started Aug 06 07:52:28 PM PDT 24
Finished Aug 06 07:52:37 PM PDT 24
Peak memory 224916 kb
Host smart-6a13fb72-bc78-4d26-b4fe-d2fe6e8ba493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552296194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.552296194
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.731724684
Short name T534
Test name
Test status
Simulation time 449002075 ps
CPU time 3.39 seconds
Started Aug 06 07:52:29 PM PDT 24
Finished Aug 06 07:52:32 PM PDT 24
Peak memory 233108 kb
Host smart-83b0b72f-e6e9-4d05-bd29-755ead597279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731724684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.731724684
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3219940639
Short name T460
Test name
Test status
Simulation time 3354623031 ps
CPU time 17.24 seconds
Started Aug 06 07:52:27 PM PDT 24
Finished Aug 06 07:52:44 PM PDT 24
Peak memory 220660 kb
Host smart-7562d871-8c79-4839-b0d3-2179806ea851
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3219940639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3219940639
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.473028507
Short name T479
Test name
Test status
Simulation time 145218085 ps
CPU time 0.9 seconds
Started Aug 06 07:52:34 PM PDT 24
Finished Aug 06 07:52:35 PM PDT 24
Peak memory 207960 kb
Host smart-06887539-d589-4581-aa61-b3539b4e3cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473028507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.473028507
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2005198359
Short name T755
Test name
Test status
Simulation time 17629891704 ps
CPU time 39.06 seconds
Started Aug 06 07:52:27 PM PDT 24
Finished Aug 06 07:53:06 PM PDT 24
Peak memory 221720 kb
Host smart-e248499f-e0f7-4c42-a4ad-292fb48949cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005198359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2005198359
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3898438112
Short name T495
Test name
Test status
Simulation time 4957262857 ps
CPU time 8.85 seconds
Started Aug 06 07:52:31 PM PDT 24
Finished Aug 06 07:52:39 PM PDT 24
Peak memory 216740 kb
Host smart-f4fe6ebc-47d8-46a1-87be-ebdd9acf6149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898438112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3898438112
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3011699114
Short name T838
Test name
Test status
Simulation time 534633995 ps
CPU time 6.83 seconds
Started Aug 06 07:52:22 PM PDT 24
Finished Aug 06 07:52:29 PM PDT 24
Peak memory 216680 kb
Host smart-5b5afadd-acec-4147-9745-2fe66898d21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011699114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3011699114
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1073619186
Short name T874
Test name
Test status
Simulation time 68939963 ps
CPU time 0.91 seconds
Started Aug 06 07:52:32 PM PDT 24
Finished Aug 06 07:52:33 PM PDT 24
Peak memory 206376 kb
Host smart-40b43bb2-76c9-448a-9957-49e89eebf8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073619186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1073619186
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2453711700
Short name T796
Test name
Test status
Simulation time 2106443924 ps
CPU time 9.14 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:52:32 PM PDT 24
Peak memory 249180 kb
Host smart-4e73b031-8cc0-4bde-9317-8ca902d8822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453711700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2453711700
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2598658955
Short name T510
Test name
Test status
Simulation time 14073518 ps
CPU time 0.72 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 206240 kb
Host smart-f39c2ff2-d75f-47d1-8320-acf9832e7b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598658955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2598658955
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.111962757
Short name T628
Test name
Test status
Simulation time 2112675218 ps
CPU time 5.52 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 233056 kb
Host smart-ff27c9ef-65d2-4cf9-86e5-76a70183ad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111962757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.111962757
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3359842020
Short name T384
Test name
Test status
Simulation time 15934741 ps
CPU time 0.77 seconds
Started Aug 06 07:52:33 PM PDT 24
Finished Aug 06 07:52:34 PM PDT 24
Peak memory 206944 kb
Host smart-b3f2edfc-d887-47a3-95c7-020c749f28cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359842020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3359842020
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.296636016
Short name T1003
Test name
Test status
Simulation time 28917528170 ps
CPU time 67.02 seconds
Started Aug 06 07:52:39 PM PDT 24
Finished Aug 06 07:53:46 PM PDT 24
Peak memory 225552 kb
Host smart-2f3dda43-a33d-4ad3-af24-319843370b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296636016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.296636016
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4012607926
Short name T156
Test name
Test status
Simulation time 618951264 ps
CPU time 7.04 seconds
Started Aug 06 07:52:42 PM PDT 24
Finished Aug 06 07:52:49 PM PDT 24
Peak memory 218192 kb
Host smart-b8467d47-e301-4983-98ff-148e9b248596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012607926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4012607926
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1830039199
Short name T341
Test name
Test status
Simulation time 334112373 ps
CPU time 2.95 seconds
Started Aug 06 07:52:47 PM PDT 24
Finished Aug 06 07:52:50 PM PDT 24
Peak memory 224956 kb
Host smart-ab51fbbe-639c-4f2c-837b-d8a6167da8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830039199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1830039199
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2430708816
Short name T286
Test name
Test status
Simulation time 24710619971 ps
CPU time 194.64 seconds
Started Aug 06 07:52:38 PM PDT 24
Finished Aug 06 07:55:52 PM PDT 24
Peak memory 256784 kb
Host smart-767d8947-33ef-49c6-b449-110c159568e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430708816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2430708816
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3180741465
Short name T201
Test name
Test status
Simulation time 265022573 ps
CPU time 4.01 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 233104 kb
Host smart-d053afef-0d2c-46d1-b25f-4f43e52504a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180741465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3180741465
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1525885421
Short name T39
Test name
Test status
Simulation time 54269753661 ps
CPU time 97.87 seconds
Started Aug 06 07:52:44 PM PDT 24
Finished Aug 06 07:54:22 PM PDT 24
Peak memory 249592 kb
Host smart-e75db113-aa27-4242-a7fe-4bea3f0bff9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525885421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1525885421
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3164427606
Short name T280
Test name
Test status
Simulation time 5787806809 ps
CPU time 21.73 seconds
Started Aug 06 07:52:37 PM PDT 24
Finished Aug 06 07:52:59 PM PDT 24
Peak memory 237316 kb
Host smart-50508a11-6a9c-4d4a-90ff-ed8bf5c7a424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164427606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3164427606
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3940894597
Short name T248
Test name
Test status
Simulation time 880498911 ps
CPU time 4.81 seconds
Started Aug 06 07:52:38 PM PDT 24
Finished Aug 06 07:52:43 PM PDT 24
Peak memory 224928 kb
Host smart-b8f92d75-a855-4412-9330-6e0b4ba80613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940894597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3940894597
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2778016007
Short name T879
Test name
Test status
Simulation time 469458299 ps
CPU time 7.09 seconds
Started Aug 06 07:52:42 PM PDT 24
Finished Aug 06 07:52:49 PM PDT 24
Peak memory 219388 kb
Host smart-5aa131f6-4f2b-448d-a072-bc00da5cd53f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2778016007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2778016007
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2122296379
Short name T970
Test name
Test status
Simulation time 100942975434 ps
CPU time 258.51 seconds
Started Aug 06 07:52:46 PM PDT 24
Finished Aug 06 07:57:05 PM PDT 24
Peak memory 262564 kb
Host smart-4c5c3539-a68a-4390-a254-23906d5615b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122296379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2122296379
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4137497994
Short name T674
Test name
Test status
Simulation time 4643605313 ps
CPU time 13.09 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:52:36 PM PDT 24
Peak memory 220816 kb
Host smart-826272dc-ab16-43fa-b5c3-08d651d26510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137497994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4137497994
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.28071226
Short name T375
Test name
Test status
Simulation time 3229446533 ps
CPU time 4.71 seconds
Started Aug 06 07:52:28 PM PDT 24
Finished Aug 06 07:52:33 PM PDT 24
Peak memory 216740 kb
Host smart-034e3d4b-3432-405a-a197-cc810b3ef9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28071226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.28071226
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2169289665
Short name T759
Test name
Test status
Simulation time 344907582 ps
CPU time 1.66 seconds
Started Aug 06 07:52:21 PM PDT 24
Finished Aug 06 07:52:23 PM PDT 24
Peak memory 216572 kb
Host smart-86a65e94-1b31-4f20-aded-82fd9e07e3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169289665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2169289665
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.32434776
Short name T344
Test name
Test status
Simulation time 80284387 ps
CPU time 0.83 seconds
Started Aug 06 07:52:22 PM PDT 24
Finished Aug 06 07:52:23 PM PDT 24
Peak memory 206308 kb
Host smart-e3b0c988-5e23-4b1e-9389-7e8e7c0411e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32434776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.32434776
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3027147540
Short name T517
Test name
Test status
Simulation time 17579588729 ps
CPU time 27.32 seconds
Started Aug 06 07:52:40 PM PDT 24
Finished Aug 06 07:53:08 PM PDT 24
Peak memory 224924 kb
Host smart-622832b5-4cd3-410e-ad60-9b9b6c8a0687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027147540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3027147540
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2139081093
Short name T753
Test name
Test status
Simulation time 26713268 ps
CPU time 0.72 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:50 PM PDT 24
Peak memory 205200 kb
Host smart-71b5fe73-8f1f-4847-a709-3f860fe3acb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139081093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2139081093
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1979179308
Short name T321
Test name
Test status
Simulation time 1788388631 ps
CPU time 6.89 seconds
Started Aug 06 07:52:42 PM PDT 24
Finished Aug 06 07:52:49 PM PDT 24
Peak memory 233056 kb
Host smart-3d38ff95-2483-4bbc-bf0e-a732097d04f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979179308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1979179308
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1955593718
Short name T793
Test name
Test status
Simulation time 46868397 ps
CPU time 0.78 seconds
Started Aug 06 07:52:48 PM PDT 24
Finished Aug 06 07:52:49 PM PDT 24
Peak memory 205936 kb
Host smart-7eb18a3d-6a82-4a0f-8516-55134f4eecb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955593718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1955593718
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2642492677
Short name T212
Test name
Test status
Simulation time 20433330532 ps
CPU time 111.81 seconds
Started Aug 06 07:52:47 PM PDT 24
Finished Aug 06 07:54:39 PM PDT 24
Peak memory 252280 kb
Host smart-0370525d-53ac-4a52-8287-8ea7fa384ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642492677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2642492677
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2182251245
Short name T824
Test name
Test status
Simulation time 87702547212 ps
CPU time 191.02 seconds
Started Aug 06 07:52:42 PM PDT 24
Finished Aug 06 07:55:53 PM PDT 24
Peak memory 264776 kb
Host smart-47ad38f0-650d-47c5-9af1-90d8acf9bf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182251245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2182251245
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2999864134
Short name T223
Test name
Test status
Simulation time 12807664934 ps
CPU time 103.81 seconds
Started Aug 06 07:52:47 PM PDT 24
Finished Aug 06 07:54:30 PM PDT 24
Peak memory 257768 kb
Host smart-779606d7-272f-44a1-a401-5ac0d12e287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999864134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2999864134
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1918582020
Short name T974
Test name
Test status
Simulation time 834840800 ps
CPU time 9.42 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:00 PM PDT 24
Peak memory 224972 kb
Host smart-768a77b6-65ed-4513-a475-e3b04b7ded6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918582020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1918582020
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1430667805
Short name T174
Test name
Test status
Simulation time 18993771130 ps
CPU time 33.87 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:53:24 PM PDT 24
Peak memory 251476 kb
Host smart-8aaf5298-248e-4423-8363-58ec5a3224e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430667805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1430667805
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1042989185
Short name T921
Test name
Test status
Simulation time 1763352025 ps
CPU time 8.24 seconds
Started Aug 06 07:52:47 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 233180 kb
Host smart-16ef2dc0-1d15-4792-9659-64ee143629ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042989185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1042989185
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2444083320
Short name T584
Test name
Test status
Simulation time 417625331 ps
CPU time 8.81 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:01 PM PDT 24
Peak memory 233156 kb
Host smart-690e4031-8a03-4456-93c5-0dd7a18fe070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444083320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2444083320
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3727534840
Short name T238
Test name
Test status
Simulation time 1174457885 ps
CPU time 3.37 seconds
Started Aug 06 07:52:59 PM PDT 24
Finished Aug 06 07:53:03 PM PDT 24
Peak memory 224980 kb
Host smart-4bcfceac-e9ee-421b-a34b-eb56001dc540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727534840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3727534840
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2992464019
Short name T920
Test name
Test status
Simulation time 1090296052 ps
CPU time 5.36 seconds
Started Aug 06 07:52:48 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 233116 kb
Host smart-a4d2f125-8ef9-4f7a-b804-fc39df4d6683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992464019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2992464019
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4120299389
Short name T118
Test name
Test status
Simulation time 293494949 ps
CPU time 5.08 seconds
Started Aug 06 07:52:49 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 219648 kb
Host smart-e2e685c3-19a9-43a5-a166-66561f6a3807
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4120299389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4120299389
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2685320497
Short name T928
Test name
Test status
Simulation time 38697739047 ps
CPU time 174.86 seconds
Started Aug 06 07:52:42 PM PDT 24
Finished Aug 06 07:55:37 PM PDT 24
Peak memory 274228 kb
Host smart-b9c5185d-dbb9-4cb8-8e59-016dfe3c1e6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685320497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2685320497
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2367830073
Short name T355
Test name
Test status
Simulation time 1466128574 ps
CPU time 4.51 seconds
Started Aug 06 07:52:47 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 216656 kb
Host smart-fb99347c-d05c-4374-bbf2-c0b556fa39cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367830073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2367830073
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2105793525
Short name T524
Test name
Test status
Simulation time 50946055981 ps
CPU time 14.93 seconds
Started Aug 06 07:52:48 PM PDT 24
Finished Aug 06 07:53:03 PM PDT 24
Peak memory 216700 kb
Host smart-22ed03ad-ce00-4a1e-a6d2-1b583362693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105793525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2105793525
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3757197472
Short name T682
Test name
Test status
Simulation time 47660650 ps
CPU time 1.48 seconds
Started Aug 06 07:52:48 PM PDT 24
Finished Aug 06 07:52:50 PM PDT 24
Peak memory 216660 kb
Host smart-025e265a-5b58-4a45-99f0-cad9088488bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757197472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3757197472
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2816668008
Short name T343
Test name
Test status
Simulation time 121755297 ps
CPU time 1.07 seconds
Started Aug 06 07:52:45 PM PDT 24
Finished Aug 06 07:52:46 PM PDT 24
Peak memory 206376 kb
Host smart-5def7dee-f584-4e8c-8d76-20a793e6b491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816668008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2816668008
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2090782823
Short name T413
Test name
Test status
Simulation time 488543216 ps
CPU time 8.85 seconds
Started Aug 06 07:52:45 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 240264 kb
Host smart-4ddd0370-6c55-4fe0-83cc-4c707ab9957d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090782823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2090782823
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3293757799
Short name T430
Test name
Test status
Simulation time 11082816 ps
CPU time 0.71 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 205248 kb
Host smart-524e60ad-429f-41fb-a919-aa582a3e1333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293757799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3293757799
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2591437376
Short name T626
Test name
Test status
Simulation time 131175003 ps
CPU time 2.81 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 224896 kb
Host smart-b896991f-ff43-4c71-80b9-256a764d467a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591437376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2591437376
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.861392260
Short name T402
Test name
Test status
Simulation time 16586772 ps
CPU time 0.72 seconds
Started Aug 06 07:52:48 PM PDT 24
Finished Aug 06 07:52:49 PM PDT 24
Peak memory 206000 kb
Host smart-50b15af5-f1b6-4077-a8e7-3132a140877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861392260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.861392260
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.694352259
Short name T542
Test name
Test status
Simulation time 18746913626 ps
CPU time 54.2 seconds
Started Aug 06 07:53:00 PM PDT 24
Finished Aug 06 07:53:54 PM PDT 24
Peak memory 249636 kb
Host smart-3ebac08b-7578-451c-8bf8-5206d2a76118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694352259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.694352259
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2103487392
Short name T704
Test name
Test status
Simulation time 50275644284 ps
CPU time 191.2 seconds
Started Aug 06 07:53:01 PM PDT 24
Finished Aug 06 07:56:12 PM PDT 24
Peak memory 249852 kb
Host smart-94b424f7-0102-450d-a79d-a106cb062e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103487392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2103487392
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1554703229
Short name T443
Test name
Test status
Simulation time 14188275391 ps
CPU time 76.04 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:54:09 PM PDT 24
Peak memory 257760 kb
Host smart-e7ae1bdf-9f94-4dc3-9893-733b42468ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554703229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1554703229
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.903381957
Short name T493
Test name
Test status
Simulation time 3174094054 ps
CPU time 25.93 seconds
Started Aug 06 07:52:59 PM PDT 24
Finished Aug 06 07:53:25 PM PDT 24
Peak memory 233244 kb
Host smart-08bd77eb-e237-4343-a745-7fb44969752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903381957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.903381957
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2033576011
Short name T751
Test name
Test status
Simulation time 15285265937 ps
CPU time 18 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:53:11 PM PDT 24
Peak memory 233132 kb
Host smart-c8e99712-a54b-4010-8132-3213f41a38f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033576011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2033576011
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.996627302
Short name T885
Test name
Test status
Simulation time 110317251 ps
CPU time 1.92 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 224048 kb
Host smart-b5aff35e-5f2c-4f5b-8fb4-7e51b1b10ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996627302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.996627302
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2621210903
Short name T828
Test name
Test status
Simulation time 15336758979 ps
CPU time 13.57 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:06 PM PDT 24
Peak memory 225008 kb
Host smart-08815a57-8fef-4be5-b0d8-0c407fa122a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621210903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2621210903
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1149716246
Short name T265
Test name
Test status
Simulation time 237699683 ps
CPU time 3.21 seconds
Started Aug 06 07:52:59 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 233004 kb
Host smart-03d8d389-e1da-4346-af02-e65eec616c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149716246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1149716246
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3010683937
Short name T138
Test name
Test status
Simulation time 398676242 ps
CPU time 3.23 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 219612 kb
Host smart-172a0e2c-3510-464d-b2df-07b45e07c4e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3010683937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3010683937
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3539935907
Short name T366
Test name
Test status
Simulation time 4175634698 ps
CPU time 18.04 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:53:08 PM PDT 24
Peak memory 216808 kb
Host smart-3fac109e-9942-4ea1-8785-74f45aca5465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539935907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3539935907
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3470788043
Short name T607
Test name
Test status
Simulation time 3291693829 ps
CPU time 10.52 seconds
Started Aug 06 07:52:49 PM PDT 24
Finished Aug 06 07:52:59 PM PDT 24
Peak memory 216752 kb
Host smart-5688ce16-c223-4fc0-8fa1-8313744edb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470788043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3470788043
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3749762831
Short name T729
Test name
Test status
Simulation time 99387266 ps
CPU time 1.95 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 216580 kb
Host smart-3957bcc6-f677-4765-9ee2-45f3842683dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749762831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3749762831
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1331509750
Short name T677
Test name
Test status
Simulation time 174193887 ps
CPU time 0.84 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 206324 kb
Host smart-ab1ebea0-57f3-4d8b-aae5-de4befd22a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331509750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1331509750
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1620480542
Short name T783
Test name
Test status
Simulation time 4355074023 ps
CPU time 5.79 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:52:59 PM PDT 24
Peak memory 233180 kb
Host smart-fb2ca1b6-fd93-4bdc-b3bc-136e25e1e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620480542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1620480542
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3211007819
Short name T917
Test name
Test status
Simulation time 52055691 ps
CPU time 0.7 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 205856 kb
Host smart-45e2de58-51a2-4650-827e-35aaff051504
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211007819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3211007819
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.839478565
Short name T571
Test name
Test status
Simulation time 1112229900 ps
CPU time 5.25 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 233184 kb
Host smart-c2309381-6955-4a06-9d23-fde52456fd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839478565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.839478565
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2436451176
Short name T698
Test name
Test status
Simulation time 21935649 ps
CPU time 0.8 seconds
Started Aug 06 07:52:54 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 207324 kb
Host smart-9ee88090-289e-408e-914d-279199f39a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436451176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2436451176
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1422488908
Short name T651
Test name
Test status
Simulation time 14739080576 ps
CPU time 126.69 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:55:03 PM PDT 24
Peak memory 257016 kb
Host smart-fd8e0314-4b7d-4d93-933a-fa7803992a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422488908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1422488908
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3211770563
Short name T830
Test name
Test status
Simulation time 708403874 ps
CPU time 13.13 seconds
Started Aug 06 07:53:02 PM PDT 24
Finished Aug 06 07:53:15 PM PDT 24
Peak memory 234420 kb
Host smart-3a6c4364-c004-4aa4-b649-84aea4fc4c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211770563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3211770563
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.987873105
Short name T639
Test name
Test status
Simulation time 2064448239 ps
CPU time 18.3 seconds
Started Aug 06 07:53:05 PM PDT 24
Finished Aug 06 07:53:23 PM PDT 24
Peak memory 224892 kb
Host smart-5673f5a6-1075-4ade-83d9-58c1b518c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987873105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.987873105
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1173389385
Short name T250
Test name
Test status
Simulation time 4477344364 ps
CPU time 10.59 seconds
Started Aug 06 07:52:59 PM PDT 24
Finished Aug 06 07:53:09 PM PDT 24
Peak memory 233252 kb
Host smart-66ef81f9-b1f0-43bc-b9fb-85a66a54dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173389385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1173389385
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.743964275
Short name T258
Test name
Test status
Simulation time 553979055 ps
CPU time 3.22 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:52:59 PM PDT 24
Peak memory 224892 kb
Host smart-0b32e41a-4eff-4e3e-8d4f-da4a134ea8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743964275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.743964275
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3040941222
Short name T909
Test name
Test status
Simulation time 8896634377 ps
CPU time 32.5 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:53:29 PM PDT 24
Peak memory 240276 kb
Host smart-7c84ad0d-cbd3-4884-8d63-e047aa1d9c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040941222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3040941222
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2010409089
Short name T499
Test name
Test status
Simulation time 180152155 ps
CPU time 3.45 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:52:59 PM PDT 24
Peak memory 223504 kb
Host smart-b55647a7-1038-4d2a-8764-df2dc6c94461
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2010409089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2010409089
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3374653239
Short name T23
Test name
Test status
Simulation time 3018328087 ps
CPU time 12.32 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:05 PM PDT 24
Peak memory 217048 kb
Host smart-8b3ea587-f169-4eda-85fe-0b401f09aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374653239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3374653239
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3879678575
Short name T944
Test name
Test status
Simulation time 1525430063 ps
CPU time 8.85 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 216700 kb
Host smart-4c4652f7-015e-419a-aed9-410085168fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879678575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3879678575
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.810608843
Short name T311
Test name
Test status
Simulation time 256682256 ps
CPU time 1.66 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 216644 kb
Host smart-8f3e7790-e3fe-4b9b-8fa3-8b0f18462a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810608843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.810608843
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3441740187
Short name T424
Test name
Test status
Simulation time 33034279 ps
CPU time 0.76 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 206396 kb
Host smart-5d95c798-f771-431e-b203-20b7513d3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441740187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3441740187
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.854595942
Short name T206
Test name
Test status
Simulation time 3800740466 ps
CPU time 12.42 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:04 PM PDT 24
Peak memory 251032 kb
Host smart-0936cf51-a63c-4e66-8f44-1c554699ba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854595942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.854595942
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1947670880
Short name T656
Test name
Test status
Simulation time 40141293 ps
CPU time 0.75 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 206036 kb
Host smart-0296137f-7ed3-4e6f-a5d4-aad33f6dafa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947670880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1947670880
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2881404789
Short name T507
Test name
Test status
Simulation time 143800801 ps
CPU time 2.31 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 224432 kb
Host smart-0fa3f4ed-5ec3-485a-8023-4f3c453a4f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881404789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2881404789
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4159454538
Short name T467
Test name
Test status
Simulation time 60145925 ps
CPU time 0.77 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:52:58 PM PDT 24
Peak memory 206812 kb
Host smart-cbe3a9f0-c7c4-4e07-ab44-5f25d32b9277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159454538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4159454538
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2939018314
Short name T556
Test name
Test status
Simulation time 1038168889 ps
CPU time 20.2 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 249524 kb
Host smart-6cd27262-21e2-4846-b59d-12f2f35721af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939018314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2939018314
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2311499826
Short name T486
Test name
Test status
Simulation time 11755264067 ps
CPU time 97.79 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:54:34 PM PDT 24
Peak memory 249836 kb
Host smart-15ea4b52-aaaf-40cf-9d77-f64519b24214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311499826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2311499826
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2578320175
Short name T308
Test name
Test status
Simulation time 19177593403 ps
CPU time 85.16 seconds
Started Aug 06 07:52:48 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 266016 kb
Host smart-4763b757-7faf-4fc0-ad62-cde4c00a3455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578320175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2578320175
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2299848664
Short name T946
Test name
Test status
Simulation time 171830297 ps
CPU time 7.03 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:58 PM PDT 24
Peak memory 224928 kb
Host smart-ce692f4a-cb15-4061-8024-5c8d787e910f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299848664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2299848664
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3657707748
Short name T604
Test name
Test status
Simulation time 33344585637 ps
CPU time 240.46 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:56:56 PM PDT 24
Peak memory 252032 kb
Host smart-b1c62bc4-c8c7-4ec4-8512-eedb75b776e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657707748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3657707748
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2614896419
Short name T408
Test name
Test status
Simulation time 412194879 ps
CPU time 5.94 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:53:03 PM PDT 24
Peak memory 220148 kb
Host smart-c235ba88-8466-42e4-9559-cc6bbf6ab7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614896419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2614896419
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3364031834
Short name T199
Test name
Test status
Simulation time 29662631 ps
CPU time 2.1 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 224768 kb
Host smart-d29c4960-42b6-4e03-9dc8-43e1ecffdc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364031834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3364031834
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2108069383
Short name T776
Test name
Test status
Simulation time 33259616 ps
CPU time 2.3 seconds
Started Aug 06 07:53:06 PM PDT 24
Finished Aug 06 07:53:08 PM PDT 24
Peak memory 232832 kb
Host smart-78d7bac5-e40d-40d4-a0e5-847bbc83bee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108069383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2108069383
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3750855823
Short name T140
Test name
Test status
Simulation time 490512875 ps
CPU time 5.62 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:57 PM PDT 24
Peak memory 223128 kb
Host smart-b5302d76-011a-497a-a61b-9fd7ec69c4b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3750855823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3750855823
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3018053857
Short name T578
Test name
Test status
Simulation time 36831852 ps
CPU time 0.92 seconds
Started Aug 06 07:52:54 PM PDT 24
Finished Aug 06 07:52:55 PM PDT 24
Peak memory 207244 kb
Host smart-b1786500-436a-4784-93d9-400f905e231d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018053857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3018053857
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3476692424
Short name T933
Test name
Test status
Simulation time 10526354737 ps
CPU time 26.67 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:53:24 PM PDT 24
Peak memory 216568 kb
Host smart-a2059c0b-bb0d-4772-aabd-997800ebc4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476692424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3476692424
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.271675291
Short name T810
Test name
Test status
Simulation time 301429030 ps
CPU time 2.21 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 216684 kb
Host smart-38459d16-cb33-4e9a-9b99-fe8a1ada6170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271675291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.271675291
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2341479041
Short name T943
Test name
Test status
Simulation time 440786333 ps
CPU time 1.98 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:52:57 PM PDT 24
Peak memory 216664 kb
Host smart-e71d0e44-085a-436f-962c-f955022a5f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341479041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2341479041
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4263066223
Short name T7
Test name
Test status
Simulation time 221032272 ps
CPU time 0.87 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:52:58 PM PDT 24
Peak memory 206184 kb
Host smart-766d9f4e-de09-4476-9e68-992a594a8185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263066223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4263066223
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.506491973
Short name T728
Test name
Test status
Simulation time 341071202 ps
CPU time 2.24 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:52:55 PM PDT 24
Peak memory 224844 kb
Host smart-fd7cb2f2-c051-4168-974c-afaa2e710789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506491973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.506491973
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.354596705
Short name T955
Test name
Test status
Simulation time 23460018 ps
CPU time 0.71 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:52:02 PM PDT 24
Peak memory 205236 kb
Host smart-d0ddb00c-220b-4a0c-a55d-2026ccc0546e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354596705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.354596705
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.877087208
Short name T693
Test name
Test status
Simulation time 196671912 ps
CPU time 4.58 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:55 PM PDT 24
Peak memory 233124 kb
Host smart-52fcff4c-afc0-48be-a0fd-33e9388894f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877087208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.877087208
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3437256341
Short name T668
Test name
Test status
Simulation time 15449923 ps
CPU time 0.74 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:52:03 PM PDT 24
Peak memory 206296 kb
Host smart-3b8c870e-9867-40f1-bb22-3a411bdf73f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437256341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3437256341
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3024376367
Short name T433
Test name
Test status
Simulation time 328180997715 ps
CPU time 244.47 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:56:04 PM PDT 24
Peak memory 249624 kb
Host smart-df0bb498-54d8-4328-acaf-6f9d2f9bf05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024376367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3024376367
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.28958264
Short name T816
Test name
Test status
Simulation time 18497200159 ps
CPU time 53.59 seconds
Started Aug 06 07:52:08 PM PDT 24
Finished Aug 06 07:53:01 PM PDT 24
Peak memory 234872 kb
Host smart-00fc3b44-ac3b-4c01-b100-804c6075f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28958264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.28958264
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.745170125
Short name T134
Test name
Test status
Simulation time 141279348 ps
CPU time 2.46 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 224980 kb
Host smart-078c0684-ff02-45da-81f5-372f73f3e39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745170125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.745170125
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3407453654
Short name T839
Test name
Test status
Simulation time 7334642826 ps
CPU time 34.29 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:33 PM PDT 24
Peak memory 241312 kb
Host smart-fbf5c3bc-4722-4a4c-ae25-9748065b9661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407453654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3407453654
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3674028747
Short name T999
Test name
Test status
Simulation time 1629710663 ps
CPU time 12.69 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:52:06 PM PDT 24
Peak memory 233100 kb
Host smart-bcd05cb5-c33d-412c-8d02-5bedb10bd479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674028747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3674028747
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3778539439
Short name T732
Test name
Test status
Simulation time 4554527603 ps
CPU time 42.71 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:52:41 PM PDT 24
Peak memory 241264 kb
Host smart-8f30ef84-3e65-44cc-8f18-96c2bc456fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778539439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3778539439
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2931586276
Short name T226
Test name
Test status
Simulation time 589643290 ps
CPU time 5.18 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:54 PM PDT 24
Peak memory 224888 kb
Host smart-994f38b9-1e11-4c3d-9d1f-5c81728b5fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931586276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2931586276
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3190952241
Short name T829
Test name
Test status
Simulation time 273304628 ps
CPU time 2.29 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:50 PM PDT 24
Peak memory 223456 kb
Host smart-aeb311ec-5e44-468c-addf-8294507ee6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190952241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3190952241
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.380788753
Short name T645
Test name
Test status
Simulation time 2742782352 ps
CPU time 5.28 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:05 PM PDT 24
Peak memory 220936 kb
Host smart-89b84082-4818-4c48-a656-5dc165edbbb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=380788753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.380788753
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.258343311
Short name T73
Test name
Test status
Simulation time 130986370 ps
CPU time 0.96 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 236780 kb
Host smart-de0d125e-b64f-4260-afc6-4a377f3e33ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258343311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.258343311
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4017644183
Short name T913
Test name
Test status
Simulation time 182169090 ps
CPU time 0.94 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 207120 kb
Host smart-508d7e13-cbce-4e8a-be61-4f07c293b763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017644183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4017644183
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3214151664
Short name T805
Test name
Test status
Simulation time 1788620751 ps
CPU time 26.87 seconds
Started Aug 06 07:51:54 PM PDT 24
Finished Aug 06 07:52:21 PM PDT 24
Peak memory 216824 kb
Host smart-9d71e547-b2a9-42ca-9bfd-8be3baacd555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214151664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3214151664
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2286520403
Short name T831
Test name
Test status
Simulation time 1806809109 ps
CPU time 5.31 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:55 PM PDT 24
Peak memory 216604 kb
Host smart-690c2090-5bbf-4a61-a12e-b3725ec1d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286520403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2286520403
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3232520548
Short name T541
Test name
Test status
Simulation time 75350318 ps
CPU time 0.98 seconds
Started Aug 06 07:51:47 PM PDT 24
Finished Aug 06 07:51:48 PM PDT 24
Peak memory 207656 kb
Host smart-439c475d-cb05-4ba9-b74c-b0b1d5901682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232520548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3232520548
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3245024306
Short name T512
Test name
Test status
Simulation time 162877238 ps
CPU time 0.87 seconds
Started Aug 06 07:51:51 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 206368 kb
Host smart-62376514-5568-467d-a260-46b08905ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245024306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3245024306
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2231830470
Short name T719
Test name
Test status
Simulation time 4940239393 ps
CPU time 17.38 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:52:06 PM PDT 24
Peak memory 230096 kb
Host smart-cf8c1e87-8aeb-4555-a493-13c2e1cc4827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231830470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2231830470
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3574085543
Short name T386
Test name
Test status
Simulation time 1852383873 ps
CPU time 5.76 seconds
Started Aug 06 07:52:58 PM PDT 24
Finished Aug 06 07:53:04 PM PDT 24
Peak memory 224916 kb
Host smart-76aa1f11-45b6-4fab-93d1-fe2890bbcb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574085543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3574085543
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.648265881
Short name T320
Test name
Test status
Simulation time 12999717 ps
CPU time 0.75 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 206312 kb
Host smart-639ee9f8-6866-416a-8c8d-c308a4e05d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648265881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.648265881
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1015380343
Short name T56
Test name
Test status
Simulation time 10768107605 ps
CPU time 65.49 seconds
Started Aug 06 07:52:49 PM PDT 24
Finished Aug 06 07:53:55 PM PDT 24
Peak memory 256008 kb
Host smart-ef0a28c7-937a-498d-8432-bc177a726243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015380343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1015380343
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1073390037
Short name T289
Test name
Test status
Simulation time 89351593726 ps
CPU time 194.72 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:56:06 PM PDT 24
Peak memory 252948 kb
Host smart-06a228aa-cef6-4bdc-97cf-771a4405f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073390037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1073390037
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.717423523
Short name T16
Test name
Test status
Simulation time 22872980105 ps
CPU time 108.94 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:54:41 PM PDT 24
Peak memory 257400 kb
Host smart-3e62dc89-4f9c-4e31-8597-38d9fee8707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717423523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.717423523
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.4210969374
Short name T291
Test name
Test status
Simulation time 412500747 ps
CPU time 6.46 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:57 PM PDT 24
Peak memory 233108 kb
Host smart-dc1ba040-f1e6-4212-8b51-df260505a959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210969374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4210969374
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.349809576
Short name T650
Test name
Test status
Simulation time 6429068755 ps
CPU time 21.72 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:14 PM PDT 24
Peak memory 224948 kb
Host smart-080d29d3-c657-457c-bec6-f445af03d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349809576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.349809576
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3762448167
Short name T62
Test name
Test status
Simulation time 5940201130 ps
CPU time 14.34 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:53:10 PM PDT 24
Peak memory 225040 kb
Host smart-a967e47f-2514-474b-8da2-a0e8e48858ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762448167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3762448167
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.111816979
Short name T268
Test name
Test status
Simulation time 10762541408 ps
CPU time 46.96 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:53:37 PM PDT 24
Peak memory 240372 kb
Host smart-4131edcf-f91b-4394-9d1e-2f1b68bea33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111816979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.111816979
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3059674096
Short name T196
Test name
Test status
Simulation time 21741913121 ps
CPU time 14.19 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:06 PM PDT 24
Peak memory 233164 kb
Host smart-b9bb6f36-9717-465b-9a30-5aa8ee1578ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059674096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3059674096
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2542585144
Short name T716
Test name
Test status
Simulation time 488484840 ps
CPU time 3.04 seconds
Started Aug 06 07:52:49 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 233072 kb
Host smart-5c48a5ff-1a7f-4f18-a212-d7db32b31b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542585144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2542585144
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2403544314
Short name T117
Test name
Test status
Simulation time 789770578 ps
CPU time 10.99 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 222460 kb
Host smart-c292df7a-c579-4151-aa80-6e545eb87546
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2403544314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2403544314
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3910173002
Short name T203
Test name
Test status
Simulation time 15983245964 ps
CPU time 109.51 seconds
Started Aug 06 07:52:54 PM PDT 24
Finished Aug 06 07:54:44 PM PDT 24
Peak memory 265056 kb
Host smart-f8943e2c-14e6-4bc4-b0c4-ba8727dd75f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910173002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3910173002
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1603771734
Short name T393
Test name
Test status
Simulation time 3203869847 ps
CPU time 14.47 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:05 PM PDT 24
Peak memory 216808 kb
Host smart-368b59d1-df64-4676-be95-f36076396bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603771734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1603771734
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.363439230
Short name T518
Test name
Test status
Simulation time 17219247644 ps
CPU time 14.09 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:06 PM PDT 24
Peak memory 216740 kb
Host smart-f403e2b7-92da-40c3-af6c-c4b082561162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363439230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.363439230
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2482217993
Short name T665
Test name
Test status
Simulation time 13430074 ps
CPU time 0.71 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 205912 kb
Host smart-96d47fdd-14d1-464d-92ab-bc6562983af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482217993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2482217993
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4167866384
Short name T591
Test name
Test status
Simulation time 535304127 ps
CPU time 0.91 seconds
Started Aug 06 07:53:01 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 207436 kb
Host smart-2449a39a-489e-4458-842f-c437963ddf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167866384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4167866384
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3666855523
Short name T485
Test name
Test status
Simulation time 1087784327 ps
CPU time 4.4 seconds
Started Aug 06 07:52:47 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 238060 kb
Host smart-b0dc00a5-097d-47f3-b935-25c1f797abff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666855523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3666855523
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2378464103
Short name T442
Test name
Test status
Simulation time 48249958 ps
CPU time 0.72 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:51 PM PDT 24
Peak memory 206128 kb
Host smart-c18aea6e-3d67-4723-ab1b-e21e75bb0732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378464103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2378464103
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2925929417
Short name T515
Test name
Test status
Simulation time 136107466 ps
CPU time 2.52 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 224768 kb
Host smart-c29fdf55-96f0-4073-96ed-28493dd3004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925929417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2925929417
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3898874085
Short name T894
Test name
Test status
Simulation time 55067653 ps
CPU time 0.81 seconds
Started Aug 06 07:53:02 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 207204 kb
Host smart-1f3edbbe-32d1-4cfb-a936-7ef44d5e47af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898874085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3898874085
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3964777667
Short name T194
Test name
Test status
Simulation time 4280932924 ps
CPU time 17.78 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:09 PM PDT 24
Peak memory 239792 kb
Host smart-d3172cdc-5f5c-4bf8-bde8-7ee4294e2c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964777667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3964777667
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1825272004
Short name T722
Test name
Test status
Simulation time 2598968957 ps
CPU time 58.05 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:49 PM PDT 24
Peak memory 257292 kb
Host smart-1ff8a1de-7077-4ece-9403-797a7237fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825272004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1825272004
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3571361239
Short name T323
Test name
Test status
Simulation time 93914325 ps
CPU time 3.42 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 224852 kb
Host smart-cc274ecb-2a2e-443c-b207-5808704f78a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571361239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3571361239
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.933341507
Short name T535
Test name
Test status
Simulation time 16561390017 ps
CPU time 47.89 seconds
Started Aug 06 07:52:54 PM PDT 24
Finished Aug 06 07:53:42 PM PDT 24
Peak memory 237000 kb
Host smart-d428cb24-50a5-421b-8adf-db2c428e3450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933341507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.933341507
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2210531961
Short name T523
Test name
Test status
Simulation time 1962480238 ps
CPU time 19.29 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 224880 kb
Host smart-11ccd6fd-993b-4431-b760-c690c424dcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210531961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2210531961
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3794355861
Short name T338
Test name
Test status
Simulation time 13609596700 ps
CPU time 15.54 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 233112 kb
Host smart-2471ece3-9f9e-4f78-8800-f3d2e8c02fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794355861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3794355861
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2960417538
Short name T260
Test name
Test status
Simulation time 3908402218 ps
CPU time 13.41 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:53:07 PM PDT 24
Peak memory 224932 kb
Host smart-6a115c05-2e57-40fb-af8d-943b5cac9a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960417538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2960417538
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4094520005
Short name T863
Test name
Test status
Simulation time 158003212 ps
CPU time 4.31 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:52:59 PM PDT 24
Peak memory 233084 kb
Host smart-ec6df447-09e4-408f-a023-d74159e239b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094520005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4094520005
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1356092651
Short name T942
Test name
Test status
Simulation time 3138488563 ps
CPU time 10.09 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 219996 kb
Host smart-cdb77796-2527-43b3-833f-bfdb274adaf0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1356092651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1356092651
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2935856084
Short name T718
Test name
Test status
Simulation time 239366512 ps
CPU time 1.09 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:52:57 PM PDT 24
Peak memory 208120 kb
Host smart-e7032b5b-5785-43a1-97f0-dc3a2a23e8b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935856084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2935856084
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4081965205
Short name T533
Test name
Test status
Simulation time 21610870154 ps
CPU time 11.35 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 216872 kb
Host smart-f0c3d279-9236-4a07-8480-4faaaa4945d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081965205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4081965205
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1617234511
Short name T888
Test name
Test status
Simulation time 112762689 ps
CPU time 1.21 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 216672 kb
Host smart-7db3d240-204a-42ef-a542-210f372614f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617234511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1617234511
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.269007660
Short name T659
Test name
Test status
Simulation time 160577988 ps
CPU time 0.8 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:51 PM PDT 24
Peak memory 206240 kb
Host smart-6373c489-ceb5-40f9-a345-6acc0d67de3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269007660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.269007660
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1952630205
Short name T380
Test name
Test status
Simulation time 1042209200 ps
CPU time 5.33 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:52:58 PM PDT 24
Peak memory 233208 kb
Host smart-d3ac26c2-89b3-4401-abe4-64b6ca6d117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952630205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1952630205
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.791847791
Short name T900
Test name
Test status
Simulation time 12679910 ps
CPU time 0.77 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:52:57 PM PDT 24
Peak memory 205304 kb
Host smart-8e7a3ec7-00c4-4728-aa15-6683d36bcfe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791847791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.791847791
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.850125644
Short name T605
Test name
Test status
Simulation time 2552076511 ps
CPU time 8.8 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:00 PM PDT 24
Peak memory 224992 kb
Host smart-92cea3d1-5715-494c-a037-0e57a9c964dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850125644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.850125644
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1551649585
Short name T360
Test name
Test status
Simulation time 31416001 ps
CPU time 0.79 seconds
Started Aug 06 07:52:54 PM PDT 24
Finished Aug 06 07:52:55 PM PDT 24
Peak memory 206976 kb
Host smart-47524362-c32f-4f7e-8c27-2992162d88c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551649585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1551649585
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1065484006
Short name T385
Test name
Test status
Simulation time 2445175804 ps
CPU time 26.06 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:17 PM PDT 24
Peak memory 238524 kb
Host smart-1e6472aa-d948-40a4-866b-38a7cfab1dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065484006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1065484006
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.781286224
Short name T31
Test name
Test status
Simulation time 2794808452 ps
CPU time 44.42 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:37 PM PDT 24
Peak memory 240620 kb
Host smart-ccff1eb5-ae9c-4215-a976-15bc4c235dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781286224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.781286224
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2980366182
Short name T210
Test name
Test status
Simulation time 4345012679 ps
CPU time 102.64 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:54:34 PM PDT 24
Peak memory 265576 kb
Host smart-15304620-d491-4cfd-bd6f-7b2d77c58348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980366182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2980366182
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1417108070
Short name T532
Test name
Test status
Simulation time 7144381884 ps
CPU time 44.1 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:36 PM PDT 24
Peak memory 249584 kb
Host smart-e49a5551-0ffb-4ebb-b819-757ad3afb427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417108070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1417108070
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4216049587
Short name T907
Test name
Test status
Simulation time 6453800506 ps
CPU time 20 seconds
Started Aug 06 07:52:54 PM PDT 24
Finished Aug 06 07:53:14 PM PDT 24
Peak memory 241340 kb
Host smart-c91f7f71-f656-4f12-bc03-db6d7ba21877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216049587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4216049587
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.406708907
Short name T516
Test name
Test status
Simulation time 201732856 ps
CPU time 2.66 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 233096 kb
Host smart-afa6b4b1-b581-4dc3-9883-56b0e5be5d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406708907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.406708907
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3517017446
Short name T340
Test name
Test status
Simulation time 2980965011 ps
CPU time 19.2 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:10 PM PDT 24
Peak memory 233088 kb
Host smart-587db0cf-c7aa-42fe-a124-f493d5e44d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517017446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3517017446
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1869080836
Short name T372
Test name
Test status
Simulation time 117074455 ps
CPU time 2.46 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:52:59 PM PDT 24
Peak memory 232712 kb
Host smart-bea1539e-147c-42ba-a4f6-c5a818266e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869080836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1869080836
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.365465472
Short name T436
Test name
Test status
Simulation time 770529710 ps
CPU time 5.55 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 233092 kb
Host smart-0d970321-dc07-40fc-92ee-a64582f7c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365465472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.365465472
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.841594675
Short name T141
Test name
Test status
Simulation time 983329892 ps
CPU time 5.69 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:52:58 PM PDT 24
Peak memory 223548 kb
Host smart-fd14ea90-82d4-44be-a043-3433905f4eca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=841594675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.841594675
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2892490552
Short name T975
Test name
Test status
Simulation time 148412444988 ps
CPU time 386.03 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:59:19 PM PDT 24
Peak memory 265604 kb
Host smart-ee6f8461-e83d-4b7a-9699-f75843735689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892490552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2892490552
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3445009489
Short name T304
Test name
Test status
Simulation time 5035227743 ps
CPU time 13.86 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:05 PM PDT 24
Peak memory 217020 kb
Host smart-635a56da-cd13-4cc3-b880-75ec673fe674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445009489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3445009489
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.878428487
Short name T364
Test name
Test status
Simulation time 1191997801 ps
CPU time 3.27 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 216664 kb
Host smart-2ea2881e-a4cf-4f44-bfe3-b8bbf5ef02ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878428487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.878428487
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.524573883
Short name T61
Test name
Test status
Simulation time 310321582 ps
CPU time 4.27 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:53:00 PM PDT 24
Peak memory 216496 kb
Host smart-efba67de-8bcc-4236-93f8-739f740cb12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524573883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.524573883
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1629595313
Short name T470
Test name
Test status
Simulation time 84973451 ps
CPU time 0.97 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:51 PM PDT 24
Peak memory 206344 kb
Host smart-c272997f-9c8f-4a7b-a684-df4d8f5a56c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629595313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1629595313
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.152785670
Short name T441
Test name
Test status
Simulation time 206858486 ps
CPU time 2.46 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:52:59 PM PDT 24
Peak memory 224400 kb
Host smart-10ddc821-6400-43c4-bafe-b4f80593dbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152785670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.152785670
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.762842160
Short name T351
Test name
Test status
Simulation time 20176656 ps
CPU time 0.73 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 205268 kb
Host smart-31c66c44-69cb-4d90-ab80-9147a70233fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762842160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.762842160
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1022476940
Short name T508
Test name
Test status
Simulation time 133458976 ps
CPU time 2.95 seconds
Started Aug 06 07:53:01 PM PDT 24
Finished Aug 06 07:53:04 PM PDT 24
Peak memory 233152 kb
Host smart-337dda34-9d95-4f49-84a0-31cb64fc8037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022476940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1022476940
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.529939391
Short name T334
Test name
Test status
Simulation time 26261421 ps
CPU time 0.79 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:51 PM PDT 24
Peak memory 205972 kb
Host smart-b95dc944-6bd2-4223-b5a2-98e266cc93d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529939391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.529939391
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.754645744
Short name T953
Test name
Test status
Simulation time 7409305135 ps
CPU time 62.1 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:53:55 PM PDT 24
Peak memory 254776 kb
Host smart-4063c039-e811-406f-87ec-31b72cba30a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754645744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.754645744
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1447173123
Short name T699
Test name
Test status
Simulation time 1828273143 ps
CPU time 37.32 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:28 PM PDT 24
Peak memory 249580 kb
Host smart-81fc2ea4-34f2-4934-b09e-9f8a28bee672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447173123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1447173123
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1969078493
Short name T557
Test name
Test status
Simulation time 274029390 ps
CPU time 6.72 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:52:59 PM PDT 24
Peak memory 224892 kb
Host smart-2b768b4f-78a3-4b4b-aa37-9203dff211cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969078493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1969078493
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.4134070877
Short name T195
Test name
Test status
Simulation time 81238927857 ps
CPU time 62.98 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:55 PM PDT 24
Peak memory 224984 kb
Host smart-9bfa498a-1411-4631-98b7-a83923135bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134070877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.4134070877
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2728591301
Short name T997
Test name
Test status
Simulation time 821983327 ps
CPU time 12.73 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:53:04 PM PDT 24
Peak memory 224980 kb
Host smart-11a1e7d8-8be0-4fd9-aafc-56be1594911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728591301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2728591301
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4129045286
Short name T540
Test name
Test status
Simulation time 396402500 ps
CPU time 2.61 seconds
Started Aug 06 07:52:58 PM PDT 24
Finished Aug 06 07:53:00 PM PDT 24
Peak memory 224932 kb
Host smart-2066e320-f2b6-4b2a-a27f-a9f7b6a30e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129045286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4129045286
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.853349678
Short name T675
Test name
Test status
Simulation time 945766185 ps
CPU time 2.95 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:52:58 PM PDT 24
Peak memory 233092 kb
Host smart-ee8c3745-46b9-4666-9478-4e6e08010c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853349678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.853349678
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3266812275
Short name T979
Test name
Test status
Simulation time 8399201630 ps
CPU time 13.58 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:53:09 PM PDT 24
Peak memory 232956 kb
Host smart-238502f0-d4e4-4d75-a524-3bd6ac1d3183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266812275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3266812275
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3624642186
Short name T581
Test name
Test status
Simulation time 236876946 ps
CPU time 4.04 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:55 PM PDT 24
Peak memory 224024 kb
Host smart-553e1afe-f7fe-4773-b302-a2da695800eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3624642186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3624642186
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1827484183
Short name T152
Test name
Test status
Simulation time 3958477150 ps
CPU time 85.56 seconds
Started Aug 06 07:53:00 PM PDT 24
Finished Aug 06 07:54:25 PM PDT 24
Peak memory 249692 kb
Host smart-d0679bbc-2b0a-4afe-88e9-f48fac4cdd32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827484183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1827484183
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.344290382
Short name T598
Test name
Test status
Simulation time 4189670269 ps
CPU time 11.04 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:53:07 PM PDT 24
Peak memory 216796 kb
Host smart-4c0be6a8-3f3d-4c77-b9ff-8a019585d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344290382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.344290382
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3579364320
Short name T629
Test name
Test status
Simulation time 1687716248 ps
CPU time 6.18 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:58 PM PDT 24
Peak memory 216660 kb
Host smart-48bda3e7-cdf8-428d-8029-7c13341b43fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579364320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3579364320
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2332074924
Short name T795
Test name
Test status
Simulation time 19018582 ps
CPU time 0.88 seconds
Started Aug 06 07:52:51 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 207368 kb
Host smart-d39ae688-71ea-4fbe-a7f4-1231b42d65ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332074924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2332074924
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.55288865
Short name T573
Test name
Test status
Simulation time 531478745 ps
CPU time 0.88 seconds
Started Aug 06 07:52:50 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 206372 kb
Host smart-d90929e5-3986-446d-8475-5f82b77385d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55288865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.55288865
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1662034249
Short name T881
Test name
Test status
Simulation time 1972091546 ps
CPU time 4.16 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:52:57 PM PDT 24
Peak memory 237376 kb
Host smart-9b872fa0-1bc5-4941-aec7-3331efe3f8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662034249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1662034249
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1893619550
Short name T9
Test name
Test status
Simulation time 53829128 ps
CPU time 0.71 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:52:55 PM PDT 24
Peak memory 206188 kb
Host smart-63ef33b5-b2f4-4a9f-9923-8c141298ac71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893619550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1893619550
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.135379283
Short name T918
Test name
Test status
Simulation time 41063679 ps
CPU time 2.76 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 233120 kb
Host smart-14d8a53d-b1b7-41a1-adfb-1d64c8adffd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135379283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.135379283
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2092938306
Short name T779
Test name
Test status
Simulation time 14332992 ps
CPU time 0.81 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:52:57 PM PDT 24
Peak memory 207008 kb
Host smart-10ae190b-164f-48bf-b1eb-21b57a154061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092938306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2092938306
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.306962657
Short name T701
Test name
Test status
Simulation time 2462114432 ps
CPU time 54 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:53:50 PM PDT 24
Peak memory 256976 kb
Host smart-73afe070-6d5f-494a-92d1-c9e3023df1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306962657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.306962657
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2573951701
Short name T281
Test name
Test status
Simulation time 2902012949 ps
CPU time 66.77 seconds
Started Aug 06 07:52:59 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 255964 kb
Host smart-2d3f60c3-470e-43e9-a60b-87c05a784317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573951701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2573951701
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4117736362
Short name T912
Test name
Test status
Simulation time 41257779798 ps
CPU time 70.94 seconds
Started Aug 06 07:52:54 PM PDT 24
Finished Aug 06 07:54:05 PM PDT 24
Peak memory 241492 kb
Host smart-a28c0678-5416-4075-a3d4-7d095fec3b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117736362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4117736362
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.92970129
Short name T867
Test name
Test status
Simulation time 183183302 ps
CPU time 3.92 seconds
Started Aug 06 07:52:49 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 224932 kb
Host smart-67ea1939-494c-45b9-ae99-f79bb7b7c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92970129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.92970129
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2415599466
Short name T905
Test name
Test status
Simulation time 1774471256 ps
CPU time 20.07 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:53:13 PM PDT 24
Peak memory 230048 kb
Host smart-53682e3a-9ea6-414f-b7e3-f9f52ccc1af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415599466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2415599466
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4021198208
Short name T254
Test name
Test status
Simulation time 315561940 ps
CPU time 3.93 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:53:01 PM PDT 24
Peak memory 224940 kb
Host smart-f7f79ba2-d6e3-4189-96dd-edcb82113f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021198208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4021198208
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3425530062
Short name T962
Test name
Test status
Simulation time 1399890863 ps
CPU time 9.51 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:53:04 PM PDT 24
Peak memory 251188 kb
Host smart-24ca7cba-8dcf-4171-ba15-fc018aee3e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425530062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3425530062
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1123902677
Short name T13
Test name
Test status
Simulation time 764915610 ps
CPU time 6.91 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 233148 kb
Host smart-022c2d98-81c8-49c8-bcb2-888162d4e16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123902677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1123902677
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3586563158
Short name T461
Test name
Test status
Simulation time 2351742671 ps
CPU time 13.69 seconds
Started Aug 06 07:52:56 PM PDT 24
Finished Aug 06 07:53:10 PM PDT 24
Peak memory 219920 kb
Host smart-f05ffc5c-e162-4d9d-acc8-b3c1587c5948
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3586563158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3586563158
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2234656513
Short name T711
Test name
Test status
Simulation time 3923352645 ps
CPU time 11.84 seconds
Started Aug 06 07:52:52 PM PDT 24
Finished Aug 06 07:53:04 PM PDT 24
Peak memory 216740 kb
Host smart-5385e753-6e02-46d9-89d2-9cbeae5e52fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234656513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2234656513
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.347640453
Short name T370
Test name
Test status
Simulation time 4882037276 ps
CPU time 7.78 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:53:04 PM PDT 24
Peak memory 216924 kb
Host smart-f183a2eb-a358-425f-bb76-c97f5ef1a3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347640453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.347640453
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3216845554
Short name T363
Test name
Test status
Simulation time 25684283 ps
CPU time 0.9 seconds
Started Aug 06 07:52:53 PM PDT 24
Finished Aug 06 07:52:54 PM PDT 24
Peak memory 207324 kb
Host smart-8d9e4ec9-e07b-4dd8-b99b-8f49c7667c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216845554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3216845554
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1509505180
Short name T414
Test name
Test status
Simulation time 44826549 ps
CPU time 0.86 seconds
Started Aug 06 07:53:02 PM PDT 24
Finished Aug 06 07:53:03 PM PDT 24
Peak memory 206288 kb
Host smart-95c3abf5-d8cd-4522-8cc1-595c4c823a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509505180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1509505180
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1483690206
Short name T120
Test name
Test status
Simulation time 9614452548 ps
CPU time 11.7 seconds
Started Aug 06 07:52:57 PM PDT 24
Finished Aug 06 07:53:09 PM PDT 24
Peak memory 233228 kb
Host smart-337a767f-ba5b-4cb4-b2bd-f9e8eea469eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483690206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1483690206
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1808402527
Short name T359
Test name
Test status
Simulation time 13407877 ps
CPU time 0.75 seconds
Started Aug 06 07:53:05 PM PDT 24
Finished Aug 06 07:53:06 PM PDT 24
Peak memory 204792 kb
Host smart-841bdbbc-0692-4a1c-bc33-3001f3aa33a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808402527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1808402527
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1284003102
Short name T878
Test name
Test status
Simulation time 361818379 ps
CPU time 3.12 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:13 PM PDT 24
Peak memory 233132 kb
Host smart-fef50fd2-18e0-4dd2-9489-33a97b75273e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284003102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1284003102
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2356226629
Short name T15
Test name
Test status
Simulation time 16570924 ps
CPU time 0.8 seconds
Started Aug 06 07:52:54 PM PDT 24
Finished Aug 06 07:52:55 PM PDT 24
Peak memory 207004 kb
Host smart-fa37d66a-8e4d-42fb-8e51-0842085df3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356226629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2356226629
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.399983421
Short name T846
Test name
Test status
Simulation time 93657773042 ps
CPU time 252.5 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:57:22 PM PDT 24
Peak memory 253216 kb
Host smart-64a0e641-1af8-4463-9e2f-4609f143aef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399983421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.399983421
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2048888344
Short name T261
Test name
Test status
Simulation time 5880128391 ps
CPU time 23.88 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:32 PM PDT 24
Peak memory 225064 kb
Host smart-0d11ec35-d896-455e-a7dc-6b19ca27fd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048888344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2048888344
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2213760659
Short name T980
Test name
Test status
Simulation time 50545845574 ps
CPU time 126.46 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:55:14 PM PDT 24
Peak memory 241368 kb
Host smart-f56746c6-7a69-4681-9979-065a1c1ea15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213760659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2213760659
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2669855413
Short name T579
Test name
Test status
Simulation time 852711205 ps
CPU time 4.36 seconds
Started Aug 06 07:53:06 PM PDT 24
Finished Aug 06 07:53:10 PM PDT 24
Peak memory 224924 kb
Host smart-2aceeaed-fad4-4563-9b70-b81ab96a63d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669855413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2669855413
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3900400501
Short name T844
Test name
Test status
Simulation time 2624505727 ps
CPU time 49.41 seconds
Started Aug 06 07:52:59 PM PDT 24
Finished Aug 06 07:53:48 PM PDT 24
Peak memory 249956 kb
Host smart-5ee53f4b-0426-4399-88ca-4f9c43001b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900400501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3900400501
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3143123492
Short name T622
Test name
Test status
Simulation time 533760235 ps
CPU time 8.75 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:53:16 PM PDT 24
Peak memory 224944 kb
Host smart-4bbbb541-6682-4714-ac4b-8a9278d2aee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143123492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3143123492
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.772547427
Short name T871
Test name
Test status
Simulation time 1277417365 ps
CPU time 13.93 seconds
Started Aug 06 07:53:03 PM PDT 24
Finished Aug 06 07:53:17 PM PDT 24
Peak memory 224864 kb
Host smart-edef83ca-cea8-4728-9183-75810bf5301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772547427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.772547427
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1438970089
Short name T453
Test name
Test status
Simulation time 634351697 ps
CPU time 6.36 seconds
Started Aug 06 07:53:03 PM PDT 24
Finished Aug 06 07:53:09 PM PDT 24
Peak memory 240192 kb
Host smart-b6ec5217-52c7-49ac-af8a-7194ddc30308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438970089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1438970089
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1076087307
Short name T664
Test name
Test status
Simulation time 27955509457 ps
CPU time 8.75 seconds
Started Aug 06 07:53:06 PM PDT 24
Finished Aug 06 07:53:14 PM PDT 24
Peak memory 224936 kb
Host smart-ddf92139-6d59-49df-8f46-0a79b3433a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076087307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1076087307
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2899062959
Short name T480
Test name
Test status
Simulation time 74037879 ps
CPU time 3.34 seconds
Started Aug 06 07:52:59 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 220456 kb
Host smart-a73c7143-7aac-4a15-ab4c-73011cc4bb0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2899062959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2899062959
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.768305682
Short name T305
Test name
Test status
Simulation time 6795017620 ps
CPU time 42.2 seconds
Started Aug 06 07:53:01 PM PDT 24
Finished Aug 06 07:53:44 PM PDT 24
Peak memory 216968 kb
Host smart-c74ffee1-7bfb-4c26-b4b7-909e372b3d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768305682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.768305682
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3488722081
Short name T11
Test name
Test status
Simulation time 17498761476 ps
CPU time 13.14 seconds
Started Aug 06 07:53:04 PM PDT 24
Finished Aug 06 07:53:17 PM PDT 24
Peak memory 216676 kb
Host smart-f896eb67-475a-4ed7-996a-11590d2430f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488722081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3488722081
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2320165362
Short name T583
Test name
Test status
Simulation time 33278980 ps
CPU time 1.12 seconds
Started Aug 06 07:53:01 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 208236 kb
Host smart-2a9a396c-b105-4920-9bbf-6c07a1eeea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320165362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2320165362
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3554335023
Short name T930
Test name
Test status
Simulation time 84335535 ps
CPU time 0.95 seconds
Started Aug 06 07:52:55 PM PDT 24
Finished Aug 06 07:52:56 PM PDT 24
Peak memory 206404 kb
Host smart-4ce4367c-e469-4016-a7d5-72fa1b44696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554335023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3554335023
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3500560750
Short name T233
Test name
Test status
Simulation time 25131405873 ps
CPU time 13.33 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:23 PM PDT 24
Peak memory 225020 kb
Host smart-b972ad11-f8ac-4022-86ac-34b59b204522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500560750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3500560750
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2067721972
Short name T807
Test name
Test status
Simulation time 14119865 ps
CPU time 0.75 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:10 PM PDT 24
Peak memory 206196 kb
Host smart-b44b4828-3437-4c0f-aa7a-3702d50f9fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067721972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2067721972
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3067964743
Short name T853
Test name
Test status
Simulation time 172576568 ps
CPU time 2.21 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 224884 kb
Host smart-5a5f5502-46be-4220-8833-610dc10e6dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067964743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3067964743
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2328103074
Short name T589
Test name
Test status
Simulation time 19584827 ps
CPU time 0.78 seconds
Started Aug 06 07:53:05 PM PDT 24
Finished Aug 06 07:53:06 PM PDT 24
Peak memory 206544 kb
Host smart-e27015e9-a3bf-4f8e-b938-18d08085431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328103074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2328103074
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.723885978
Short name T237
Test name
Test status
Simulation time 10531181913 ps
CPU time 68.79 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:54:17 PM PDT 24
Peak memory 249628 kb
Host smart-b1fbe17a-9ffe-48b9-9409-b3fc89ba448b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723885978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.723885978
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2955893256
Short name T563
Test name
Test status
Simulation time 549116290784 ps
CPU time 253.17 seconds
Started Aug 06 07:53:11 PM PDT 24
Finished Aug 06 07:57:24 PM PDT 24
Peak memory 249660 kb
Host smart-095b3cae-280e-4365-84c2-5c4b094a9c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955893256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2955893256
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.593382032
Short name T224
Test name
Test status
Simulation time 1415067484 ps
CPU time 6.26 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:14 PM PDT 24
Peak memory 224884 kb
Host smart-fea3b60f-57b7-4734-a34f-e330af5fe759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593382032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.593382032
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2321167895
Short name T984
Test name
Test status
Simulation time 29694193 ps
CPU time 0.77 seconds
Started Aug 06 07:53:03 PM PDT 24
Finished Aug 06 07:53:04 PM PDT 24
Peak memory 216140 kb
Host smart-e2e4937e-5cfb-47d4-a461-fe947b87da40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321167895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2321167895
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3759373337
Short name T602
Test name
Test status
Simulation time 2888061427 ps
CPU time 16.73 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:26 PM PDT 24
Peak memory 225012 kb
Host smart-92e9032e-5a23-41bd-a553-534f8d1b827a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759373337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3759373337
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.69294989
Short name T190
Test name
Test status
Simulation time 306251123 ps
CPU time 6.99 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:16 PM PDT 24
Peak memory 233132 kb
Host smart-b1effe0c-c2c9-4bb7-bcdd-af98207f8673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69294989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.69294989
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.858164730
Short name T43
Test name
Test status
Simulation time 2235280645 ps
CPU time 10.13 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:20 PM PDT 24
Peak memory 233132 kb
Host smart-10016f61-a0dd-433c-9241-6f45ad4d748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858164730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.858164730
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3254749869
Short name T988
Test name
Test status
Simulation time 2031175002 ps
CPU time 7.51 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:17 PM PDT 24
Peak memory 234748 kb
Host smart-02744dfa-67aa-42f7-9f5a-d7ee7cdb098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254749869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3254749869
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3300743783
Short name T764
Test name
Test status
Simulation time 2404999755 ps
CPU time 9.16 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:19 PM PDT 24
Peak memory 222584 kb
Host smart-32e63223-caa2-4f48-9647-bd65d0b37d33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3300743783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3300743783
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.4225153977
Short name T993
Test name
Test status
Simulation time 47840266482 ps
CPU time 187.45 seconds
Started Aug 06 07:53:11 PM PDT 24
Finished Aug 06 07:56:19 PM PDT 24
Peak memory 264896 kb
Host smart-5f59f562-c83b-4299-9d68-a1ce9ca66ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225153977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.4225153977
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2707910896
Short name T754
Test name
Test status
Simulation time 5048819448 ps
CPU time 19.74 seconds
Started Aug 06 07:53:03 PM PDT 24
Finished Aug 06 07:53:23 PM PDT 24
Peak memory 220528 kb
Host smart-aefc2879-cef9-41f2-b2d5-f2a135a5f1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707910896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2707910896
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.51588221
Short name T328
Test name
Test status
Simulation time 1182316397 ps
CPU time 3.83 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 216600 kb
Host smart-0fa8b72a-69e8-46a2-83e3-310163390382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51588221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.51588221
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.307723822
Short name T49
Test name
Test status
Simulation time 228389092 ps
CPU time 3.55 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:13 PM PDT 24
Peak memory 216680 kb
Host smart-b23636b5-36ff-429d-9a3f-f1ca4542571c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307723822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.307723822
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2284492725
Short name T797
Test name
Test status
Simulation time 282757010 ps
CPU time 0.96 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:09 PM PDT 24
Peak memory 207320 kb
Host smart-4618a788-1219-42ca-b5fd-cba423041a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284492725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2284492725
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1098758194
Short name T125
Test name
Test status
Simulation time 358205902 ps
CPU time 5.1 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:13 PM PDT 24
Peak memory 233092 kb
Host smart-87a20d50-0b33-442d-960a-ac5bf8250020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098758194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1098758194
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.856339621
Short name T931
Test name
Test status
Simulation time 80564307 ps
CPU time 0.72 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:11 PM PDT 24
Peak memory 205276 kb
Host smart-c65a0b86-6b8f-42dc-ac3f-85cde95d1ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856339621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.856339621
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3330833832
Short name T908
Test name
Test status
Simulation time 34968322 ps
CPU time 2.23 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:11 PM PDT 24
Peak memory 233052 kb
Host smart-8b8b8379-1b6f-4122-a798-acd6e49579c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330833832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3330833832
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3330248325
Short name T618
Test name
Test status
Simulation time 14760718 ps
CPU time 0.78 seconds
Started Aug 06 07:53:02 PM PDT 24
Finished Aug 06 07:53:03 PM PDT 24
Peak memory 205988 kb
Host smart-4ee2c272-ef5d-471e-b528-bb381aae83c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330248325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3330248325
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2081175053
Short name T1005
Test name
Test status
Simulation time 95063353740 ps
CPU time 158.28 seconds
Started Aug 06 07:53:06 PM PDT 24
Finished Aug 06 07:55:44 PM PDT 24
Peak memory 251692 kb
Host smart-ed79fc55-bfad-4641-a014-875f8f8ba7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081175053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2081175053
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2547911809
Short name T30
Test name
Test status
Simulation time 2105110434 ps
CPU time 55.56 seconds
Started Aug 06 07:53:00 PM PDT 24
Finished Aug 06 07:53:56 PM PDT 24
Peak memory 253024 kb
Host smart-32763039-dc47-41ad-bcca-7520287434e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547911809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2547911809
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4067399212
Short name T765
Test name
Test status
Simulation time 35512924728 ps
CPU time 323.29 seconds
Started Aug 06 07:53:06 PM PDT 24
Finished Aug 06 07:58:29 PM PDT 24
Peak memory 266008 kb
Host smart-2ba11d61-c6d9-4ace-a825-71ee1de6db3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067399212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4067399212
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3091551747
Short name T817
Test name
Test status
Simulation time 1510720083 ps
CPU time 5.23 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 233068 kb
Host smart-8f68a234-607f-4726-a811-2e86911b6ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091551747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3091551747
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2868109950
Short name T266
Test name
Test status
Simulation time 17733205760 ps
CPU time 29.19 seconds
Started Aug 06 07:53:01 PM PDT 24
Finished Aug 06 07:53:30 PM PDT 24
Peak memory 250136 kb
Host smart-f8bf964d-ecf9-4b22-9519-3a6be6015bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868109950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2868109950
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3689833610
Short name T739
Test name
Test status
Simulation time 1552119975 ps
CPU time 7.62 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:53:21 PM PDT 24
Peak memory 229956 kb
Host smart-00e2c697-3189-4925-ab4e-678b03d5fee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689833610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3689833610
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1868774929
Short name T546
Test name
Test status
Simulation time 47999930577 ps
CPU time 81.18 seconds
Started Aug 06 07:53:06 PM PDT 24
Finished Aug 06 07:54:27 PM PDT 24
Peak memory 251184 kb
Host smart-a2097ebc-2549-4da9-a132-2bcac61099cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868774929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1868774929
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3860990034
Short name T259
Test name
Test status
Simulation time 16158728670 ps
CPU time 17.38 seconds
Started Aug 06 07:53:04 PM PDT 24
Finished Aug 06 07:53:22 PM PDT 24
Peak memory 240604 kb
Host smart-d5fd81f2-6adb-40d8-ab5b-200efa281c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860990034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3860990034
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2685256832
Short name T562
Test name
Test status
Simulation time 659220978 ps
CPU time 5.56 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:15 PM PDT 24
Peak memory 224964 kb
Host smart-ac48fb7f-c3a0-4b43-b8ec-df3347fcbea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685256832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2685256832
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1440513218
Short name T135
Test name
Test status
Simulation time 1106073888 ps
CPU time 6.49 seconds
Started Aug 06 07:53:04 PM PDT 24
Finished Aug 06 07:53:11 PM PDT 24
Peak memory 222476 kb
Host smart-29966cbc-097b-4f79-ab1c-dba2cae1c58b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1440513218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1440513218
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.36628204
Short name T365
Test name
Test status
Simulation time 45153727 ps
CPU time 0.99 seconds
Started Aug 06 07:53:03 PM PDT 24
Finished Aug 06 07:53:04 PM PDT 24
Peak memory 207240 kb
Host smart-35329829-9a86-46cd-a770-b649b9656bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36628204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress
_all.36628204
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.32603914
Short name T958
Test name
Test status
Simulation time 1831455366 ps
CPU time 17.44 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:26 PM PDT 24
Peak memory 216660 kb
Host smart-edfa50c1-9e2a-4d89-854a-25c014daa71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32603914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.32603914
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.349135031
Short name T336
Test name
Test status
Simulation time 6141456041 ps
CPU time 11.58 seconds
Started Aug 06 07:53:04 PM PDT 24
Finished Aug 06 07:53:16 PM PDT 24
Peak memory 216628 kb
Host smart-6ab25110-8684-4357-bdf9-6d3879cd7c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349135031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.349135031
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1047110202
Short name T705
Test name
Test status
Simulation time 265522334 ps
CPU time 7.74 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:16 PM PDT 24
Peak memory 216712 kb
Host smart-0cc7cbdd-04ee-4c40-b459-3a14119a99e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047110202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1047110202
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3193915047
Short name T520
Test name
Test status
Simulation time 59131587 ps
CPU time 0.72 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:09 PM PDT 24
Peak memory 206340 kb
Host smart-c7ff4285-cecd-4569-855a-11e03e65d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193915047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3193915047
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.80359470
Short name T956
Test name
Test status
Simulation time 92936402 ps
CPU time 2.52 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 224964 kb
Host smart-2cd7cca7-b15e-4ab6-8de3-0607c08913a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80359470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.80359470
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.840998792
Short name T400
Test name
Test status
Simulation time 14777619 ps
CPU time 0.77 seconds
Started Aug 06 07:53:02 PM PDT 24
Finished Aug 06 07:53:03 PM PDT 24
Peak memory 206040 kb
Host smart-6ff66161-549f-45f6-a1ab-95bf94cc6229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840998792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.840998792
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3886423769
Short name T647
Test name
Test status
Simulation time 344667400 ps
CPU time 3.52 seconds
Started Aug 06 07:53:06 PM PDT 24
Finished Aug 06 07:53:10 PM PDT 24
Peak memory 233040 kb
Host smart-b46108ca-9c5e-4d35-9d09-aa9420e448c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886423769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3886423769
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3457880485
Short name T438
Test name
Test status
Simulation time 51720572 ps
CPU time 0.76 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:09 PM PDT 24
Peak memory 206984 kb
Host smart-08afa7d3-242d-4da7-a8af-4017db5c80a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457880485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3457880485
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3782232452
Short name T786
Test name
Test status
Simulation time 1553974758 ps
CPU time 15.23 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:53:28 PM PDT 24
Peak memory 234656 kb
Host smart-1ddb2abb-9cf3-4db6-bc98-8b9a6425c02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782232452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3782232452
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1790337790
Short name T278
Test name
Test status
Simulation time 218466032809 ps
CPU time 675.57 seconds
Started Aug 06 07:53:04 PM PDT 24
Finished Aug 06 08:04:20 PM PDT 24
Peak memory 281940 kb
Host smart-a8c21668-c867-4eae-9bb7-60abce692b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790337790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1790337790
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2528264776
Short name T279
Test name
Test status
Simulation time 273919562691 ps
CPU time 563 seconds
Started Aug 06 07:53:04 PM PDT 24
Finished Aug 06 08:02:27 PM PDT 24
Peak memory 272624 kb
Host smart-9c272dee-8bdd-4b3d-a8f8-30eb60df5873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528264776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2528264776
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2895574431
Short name T300
Test name
Test status
Simulation time 985516846 ps
CPU time 14.73 seconds
Started Aug 06 07:53:06 PM PDT 24
Finished Aug 06 07:53:21 PM PDT 24
Peak memory 224784 kb
Host smart-ca5b0d9c-b829-44b0-8cf6-91a24639db91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895574431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2895574431
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3490852085
Short name T982
Test name
Test status
Simulation time 1447955655 ps
CPU time 33.23 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:53:40 PM PDT 24
Peak memory 240364 kb
Host smart-a2d511cc-d171-4cd7-8689-b62c6503468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490852085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3490852085
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4192475335
Short name T688
Test name
Test status
Simulation time 34594729 ps
CPU time 2.17 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 232832 kb
Host smart-9caa02a0-c2b5-4d28-9dcc-d4d5d4c5e5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192475335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4192475335
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2996316607
Short name T791
Test name
Test status
Simulation time 20207244551 ps
CPU time 74.81 seconds
Started Aug 06 07:53:02 PM PDT 24
Finished Aug 06 07:54:17 PM PDT 24
Peak memory 252996 kb
Host smart-c09275e2-78c1-4c48-a838-39c0eb6135b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996316607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2996316607
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1105088307
Short name T285
Test name
Test status
Simulation time 1326897580 ps
CPU time 9.78 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:53:17 PM PDT 24
Peak memory 233160 kb
Host smart-dad5f67a-94dd-410f-85ea-8477598de6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105088307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1105088307
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2928302838
Short name T449
Test name
Test status
Simulation time 16884303906 ps
CPU time 12.92 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:53:20 PM PDT 24
Peak memory 233184 kb
Host smart-b581d14f-c211-4625-ac1b-6955351bc769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928302838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2928302838
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2634664884
Short name T763
Test name
Test status
Simulation time 1607016911 ps
CPU time 6.47 seconds
Started Aug 06 07:53:04 PM PDT 24
Finished Aug 06 07:53:10 PM PDT 24
Peak memory 223620 kb
Host smart-cf56db2c-87f0-4268-885b-a1968138b53b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2634664884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2634664884
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3869972211
Short name T102
Test name
Test status
Simulation time 14994932 ps
CPU time 0.72 seconds
Started Aug 06 07:53:06 PM PDT 24
Finished Aug 06 07:53:07 PM PDT 24
Peak memory 206048 kb
Host smart-a7b0045e-09da-452e-8a63-6c14b970f9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869972211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3869972211
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3950481425
Short name T409
Test name
Test status
Simulation time 1654936880 ps
CPU time 2.09 seconds
Started Aug 06 07:53:03 PM PDT 24
Finished Aug 06 07:53:05 PM PDT 24
Peak memory 216464 kb
Host smart-b3eb3182-bc4e-42ec-8a49-be27994f89d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950481425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3950481425
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1465343972
Short name T634
Test name
Test status
Simulation time 239246347 ps
CPU time 1.2 seconds
Started Aug 06 07:53:01 PM PDT 24
Finished Aug 06 07:53:02 PM PDT 24
Peak memory 208228 kb
Host smart-243cbf0e-ffd5-4f66-a633-ca1e7e80b826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465343972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1465343972
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3299207055
Short name T477
Test name
Test status
Simulation time 26939003 ps
CPU time 0.74 seconds
Started Aug 06 07:53:00 PM PDT 24
Finished Aug 06 07:53:01 PM PDT 24
Peak memory 206340 kb
Host smart-4cd0be4e-81be-48d5-a5ce-489504a88250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299207055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3299207055
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3471083498
Short name T617
Test name
Test status
Simulation time 8546843347 ps
CPU time 8.77 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:19 PM PDT 24
Peak memory 233224 kb
Host smart-52cb6e5a-1f54-47cd-bf8d-61a08dd59cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471083498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3471083498
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2514742815
Short name T644
Test name
Test status
Simulation time 13419461 ps
CPU time 0.72 seconds
Started Aug 06 07:53:30 PM PDT 24
Finished Aug 06 07:53:31 PM PDT 24
Peak memory 205180 kb
Host smart-b2ff37c0-8d47-4abe-af14-82442793c210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514742815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2514742815
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2513939295
Short name T713
Test name
Test status
Simulation time 125122344 ps
CPU time 3.95 seconds
Started Aug 06 07:53:11 PM PDT 24
Finished Aug 06 07:53:15 PM PDT 24
Peak memory 224896 kb
Host smart-faa2729b-2afa-4195-aa06-7c79a4b5257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513939295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2513939295
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2082881611
Short name T553
Test name
Test status
Simulation time 53927096 ps
CPU time 0.75 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:10 PM PDT 24
Peak memory 206956 kb
Host smart-d1bb0006-436b-41ae-957d-ce5d0dd9d9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082881611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2082881611
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2850959763
Short name T155
Test name
Test status
Simulation time 4422181493 ps
CPU time 62.62 seconds
Started Aug 06 07:53:16 PM PDT 24
Finished Aug 06 07:54:19 PM PDT 24
Peak memory 257088 kb
Host smart-9c70e24c-1fbf-4d8f-8c20-cf31176c3bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850959763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2850959763
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1802598566
Short name T167
Test name
Test status
Simulation time 6654215226 ps
CPU time 104.32 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:54:57 PM PDT 24
Peak memory 254276 kb
Host smart-2a0fedc2-11ae-4263-b6b4-ce911c547af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802598566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1802598566
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3427338851
Short name T325
Test name
Test status
Simulation time 1427341122 ps
CPU time 6.31 seconds
Started Aug 06 07:53:21 PM PDT 24
Finished Aug 06 07:53:28 PM PDT 24
Peak memory 234188 kb
Host smart-aebe6bda-cff1-44ef-b4c7-46f1ccede667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427338851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3427338851
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3301748994
Short name T669
Test name
Test status
Simulation time 5122245356 ps
CPU time 46.31 seconds
Started Aug 06 07:53:12 PM PDT 24
Finished Aug 06 07:53:59 PM PDT 24
Peak memory 251680 kb
Host smart-b6f86d7d-6bc6-448e-a37f-b1b4c3b2e45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301748994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3301748994
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2715403993
Short name T916
Test name
Test status
Simulation time 263052525 ps
CPU time 3.39 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:53:11 PM PDT 24
Peak memory 224888 kb
Host smart-b19096da-18ec-43c4-9987-c21a5d21c713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715403993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2715403993
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1982944901
Short name T157
Test name
Test status
Simulation time 1560670425 ps
CPU time 15.27 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:24 PM PDT 24
Peak memory 224936 kb
Host smart-03128089-89ac-4b83-b686-c19b7ba4d9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982944901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1982944901
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.302622588
Short name T603
Test name
Test status
Simulation time 43383711132 ps
CPU time 23.99 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:53:31 PM PDT 24
Peak memory 224960 kb
Host smart-c711c016-b762-4a67-a6ed-66897459a4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302622588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.302622588
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2202048939
Short name T202
Test name
Test status
Simulation time 309242967 ps
CPU time 4.79 seconds
Started Aug 06 07:53:11 PM PDT 24
Finished Aug 06 07:53:16 PM PDT 24
Peak memory 233132 kb
Host smart-3463edc7-71f9-4d06-9d71-02eb55b486bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202048939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2202048939
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1079915292
Short name T919
Test name
Test status
Simulation time 2749540587 ps
CPU time 7.23 seconds
Started Aug 06 07:53:12 PM PDT 24
Finished Aug 06 07:53:19 PM PDT 24
Peak memory 220964 kb
Host smart-65b1572c-dd54-4397-bc76-a2a4bef79961
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1079915292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1079915292
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.197372296
Short name T525
Test name
Test status
Simulation time 149602420 ps
CPU time 1.05 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:11 PM PDT 24
Peak memory 207440 kb
Host smart-f115ddd2-9955-4db6-8056-cab3a2c9eddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197372296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.197372296
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1040536536
Short name T143
Test name
Test status
Simulation time 7754242342 ps
CPU time 13.41 seconds
Started Aug 06 07:53:09 PM PDT 24
Finished Aug 06 07:53:22 PM PDT 24
Peak memory 216676 kb
Host smart-7c9fdc9c-7e12-4477-956d-8ebf82d560cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040536536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1040536536
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.750033349
Short name T471
Test name
Test status
Simulation time 3829510482 ps
CPU time 14.79 seconds
Started Aug 06 07:53:08 PM PDT 24
Finished Aug 06 07:53:23 PM PDT 24
Peak memory 216716 kb
Host smart-6e62681c-778b-4193-9cb9-a38eef2d5dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750033349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.750033349
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1970627716
Short name T403
Test name
Test status
Simulation time 1515028276 ps
CPU time 6.1 seconds
Started Aug 06 07:53:10 PM PDT 24
Finished Aug 06 07:53:16 PM PDT 24
Peak memory 216580 kb
Host smart-be3ac259-e2af-43a0-a7de-97dc018084af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970627716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1970627716
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1176274901
Short name T123
Test name
Test status
Simulation time 29748135 ps
CPU time 0.82 seconds
Started Aug 06 07:53:07 PM PDT 24
Finished Aug 06 07:53:08 PM PDT 24
Peak memory 206372 kb
Host smart-9747a924-7830-4e27-9205-2d1e9cc8845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176274901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1176274901
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.802623598
Short name T849
Test name
Test status
Simulation time 13961480280 ps
CPU time 14.78 seconds
Started Aug 06 07:53:00 PM PDT 24
Finished Aug 06 07:53:15 PM PDT 24
Peak memory 233124 kb
Host smart-fe8cad78-1c78-4740-b332-772e187d9ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802623598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.802623598
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2059982958
Short name T950
Test name
Test status
Simulation time 13110521 ps
CPU time 0.71 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:51:58 PM PDT 24
Peak memory 204972 kb
Host smart-d0079a8e-3a29-46d3-ba33-aa47710077d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059982958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
059982958
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3444591974
Short name T124
Test name
Test status
Simulation time 227806879 ps
CPU time 2.83 seconds
Started Aug 06 07:51:54 PM PDT 24
Finished Aug 06 07:51:57 PM PDT 24
Peak memory 224912 kb
Host smart-5d6cc194-a0b9-499a-8b34-3ca29f9ca85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444591974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3444591974
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.17770405
Short name T503
Test name
Test status
Simulation time 16229033 ps
CPU time 0.77 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 207188 kb
Host smart-cc25cd1a-a277-4d5a-a53f-26318a40d0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17770405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.17770405
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2683765237
Short name T407
Test name
Test status
Simulation time 43373339846 ps
CPU time 47.12 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:52:36 PM PDT 24
Peak memory 218352 kb
Host smart-beb2424f-7865-44c4-9e28-1ae9391874a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683765237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2683765237
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3545089376
Short name T945
Test name
Test status
Simulation time 4077459142 ps
CPU time 34.01 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:52:32 PM PDT 24
Peak memory 252984 kb
Host smart-9f674c55-8ea6-4c41-8899-59e6a7814766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545089376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3545089376
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3960426153
Short name T889
Test name
Test status
Simulation time 398780847 ps
CPU time 3.45 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:52:10 PM PDT 24
Peak memory 224928 kb
Host smart-16d5d302-023d-4937-a59b-4b09d6aced9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960426153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3960426153
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.573475976
Short name T925
Test name
Test status
Simulation time 19320334931 ps
CPU time 22.41 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:52:24 PM PDT 24
Peak memory 236268 kb
Host smart-581935b1-eb02-400c-9fec-e2109014c6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573475976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
573475976
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1561727843
Short name T596
Test name
Test status
Simulation time 35098960 ps
CPU time 2.52 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:56 PM PDT 24
Peak memory 232808 kb
Host smart-dd17a99f-3f21-4515-8fdd-f22e02dac01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561727843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1561727843
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2878213696
Short name T231
Test name
Test status
Simulation time 1421611957 ps
CPU time 5.75 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:51:59 PM PDT 24
Peak memory 234088 kb
Host smart-0034bb57-b7dc-40d3-8f36-99c74eb0bd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878213696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2878213696
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.82264220
Short name T585
Test name
Test status
Simulation time 4204199605 ps
CPU time 7.76 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:57 PM PDT 24
Peak memory 224972 kb
Host smart-92e5ad0f-bfaf-444d-8a55-19f55183cd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82264220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.82264220
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1626097405
Short name T789
Test name
Test status
Simulation time 8215799271 ps
CPU time 7.83 seconds
Started Aug 06 07:51:48 PM PDT 24
Finished Aug 06 07:51:56 PM PDT 24
Peak memory 233204 kb
Host smart-9e0cd1f4-3f9a-46ea-b4d8-8e553177c844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626097405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1626097405
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2545372261
Short name T767
Test name
Test status
Simulation time 768224542 ps
CPU time 6.35 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:05 PM PDT 24
Peak memory 219744 kb
Host smart-52a58948-ff0b-417a-b307-d639eee7e930
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2545372261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2545372261
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3840206637
Short name T74
Test name
Test status
Simulation time 42692185 ps
CPU time 0.94 seconds
Started Aug 06 07:52:10 PM PDT 24
Finished Aug 06 07:52:11 PM PDT 24
Peak memory 236268 kb
Host smart-bf98b5eb-32cc-4742-bc3b-eea3305899c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840206637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3840206637
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3511505038
Short name T914
Test name
Test status
Simulation time 137651382750 ps
CPU time 236.33 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:55:59 PM PDT 24
Peak memory 257800 kb
Host smart-cc92c46a-bfca-4f35-ae63-e1d4ba46e19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511505038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3511505038
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3967809893
Short name T526
Test name
Test status
Simulation time 2712911248 ps
CPU time 27.59 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:52:25 PM PDT 24
Peak memory 216688 kb
Host smart-137b7ce0-1608-476b-a1c7-d68c812a4ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967809893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3967809893
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2524543597
Short name T559
Test name
Test status
Simulation time 273797153 ps
CPU time 2.56 seconds
Started Aug 06 07:51:49 PM PDT 24
Finished Aug 06 07:51:51 PM PDT 24
Peak memory 216600 kb
Host smart-6a67e73f-72ed-4369-9bb6-22a8fd6aff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524543597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2524543597
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3414197847
Short name T324
Test name
Test status
Simulation time 22929675 ps
CPU time 0.87 seconds
Started Aug 06 07:51:54 PM PDT 24
Finished Aug 06 07:51:55 PM PDT 24
Peak memory 207684 kb
Host smart-842b4617-4e36-4f6e-8d8c-7bee175c4acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414197847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3414197847
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.201336450
Short name T851
Test name
Test status
Simulation time 245022397 ps
CPU time 0.94 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:51:58 PM PDT 24
Peak memory 206340 kb
Host smart-06aaea87-a526-4c97-b50e-0ea6ef697e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201336450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.201336450
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1365091139
Short name T121
Test name
Test status
Simulation time 22902475552 ps
CPU time 14.6 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:52:13 PM PDT 24
Peak memory 241148 kb
Host smart-e2563b74-93fa-414f-b303-83d15e2262e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365091139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1365091139
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1802395593
Short name T371
Test name
Test status
Simulation time 17196278 ps
CPU time 0.72 seconds
Started Aug 06 07:53:15 PM PDT 24
Finished Aug 06 07:53:16 PM PDT 24
Peak memory 205840 kb
Host smart-63b9cda1-42f9-4724-b7ed-9d5ad22d10ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802395593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1802395593
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2699687375
Short name T731
Test name
Test status
Simulation time 335707635 ps
CPU time 3.4 seconds
Started Aug 06 07:53:11 PM PDT 24
Finished Aug 06 07:53:14 PM PDT 24
Peak memory 224940 kb
Host smart-5fdef679-cc24-4c6a-9147-1b76e3568cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699687375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2699687375
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3528599299
Short name T760
Test name
Test status
Simulation time 59221420 ps
CPU time 0.76 seconds
Started Aug 06 07:53:21 PM PDT 24
Finished Aug 06 07:53:22 PM PDT 24
Peak memory 206964 kb
Host smart-54515c48-e819-4e79-95ca-75f6568543c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528599299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3528599299
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2369030734
Short name T600
Test name
Test status
Simulation time 6514433236 ps
CPU time 58.81 seconds
Started Aug 06 07:53:20 PM PDT 24
Finished Aug 06 07:54:19 PM PDT 24
Peak memory 241388 kb
Host smart-0ec026a9-8675-4563-a647-7ceeb98b3a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369030734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2369030734
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3550029988
Short name T869
Test name
Test status
Simulation time 114370350929 ps
CPU time 114.89 seconds
Started Aug 06 07:53:15 PM PDT 24
Finished Aug 06 07:55:10 PM PDT 24
Peak memory 249652 kb
Host smart-9e8973e2-5115-446f-8aa8-37f95f6d11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550029988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3550029988
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.853112594
Short name T241
Test name
Test status
Simulation time 91430642873 ps
CPU time 200.96 seconds
Started Aug 06 07:53:16 PM PDT 24
Finished Aug 06 07:56:37 PM PDT 24
Peak memory 254760 kb
Host smart-6c92e9ff-9882-48dc-8a95-e2a0d6299f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853112594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.853112594
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.653854423
Short name T951
Test name
Test status
Simulation time 364144819 ps
CPU time 7.67 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:53:21 PM PDT 24
Peak memory 241148 kb
Host smart-6ad4afa1-abb8-4024-9875-e9860ef12a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653854423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.653854423
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.541793363
Short name T572
Test name
Test status
Simulation time 2557985650 ps
CPU time 7.15 seconds
Started Aug 06 07:53:14 PM PDT 24
Finished Aug 06 07:53:21 PM PDT 24
Peak memory 225004 kb
Host smart-c402484e-e734-452d-a98f-112e16b9b8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541793363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.541793363
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1902900421
Short name T84
Test name
Test status
Simulation time 9376441321 ps
CPU time 21.06 seconds
Started Aug 06 07:53:11 PM PDT 24
Finished Aug 06 07:53:32 PM PDT 24
Peak memory 232112 kb
Host smart-c1163305-2c2a-497c-bee4-d7b60dba5081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902900421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1902900421
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3975110278
Short name T14
Test name
Test status
Simulation time 7629577545 ps
CPU time 61.1 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 251036 kb
Host smart-89c86f57-7976-436c-9277-9ab87b5d03e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975110278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3975110278
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1206541307
Short name T183
Test name
Test status
Simulation time 3266627743 ps
CPU time 13.02 seconds
Started Aug 06 07:53:28 PM PDT 24
Finished Aug 06 07:53:41 PM PDT 24
Peak memory 234276 kb
Host smart-f69be092-f33f-4aff-a5f7-11b12252048d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206541307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1206541307
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2698814932
Short name T417
Test name
Test status
Simulation time 17040277528 ps
CPU time 5.36 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:53:18 PM PDT 24
Peak memory 233172 kb
Host smart-ce1febbf-f9b4-416e-86c5-dae054f5e068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698814932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2698814932
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1383288234
Short name T36
Test name
Test status
Simulation time 1820767109 ps
CPU time 7.1 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:53:20 PM PDT 24
Peak memory 220636 kb
Host smart-9e537034-6905-41c2-b198-768eae75cab7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1383288234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1383288234
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3286013629
Short name T884
Test name
Test status
Simulation time 196486406754 ps
CPU time 412.25 seconds
Started Aug 06 07:53:11 PM PDT 24
Finished Aug 06 08:00:04 PM PDT 24
Peak memory 255548 kb
Host smart-56219eb4-e81f-49e9-b90e-0b9ecf83dc58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286013629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3286013629
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3156428277
Short name T597
Test name
Test status
Simulation time 4223190635 ps
CPU time 22.91 seconds
Started Aug 06 07:53:12 PM PDT 24
Finished Aug 06 07:53:35 PM PDT 24
Peak memory 216656 kb
Host smart-9de9e264-f8f7-4c76-b4f4-025890c00cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156428277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3156428277
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2487533528
Short name T768
Test name
Test status
Simulation time 8204363907 ps
CPU time 15.34 seconds
Started Aug 06 07:53:20 PM PDT 24
Finished Aug 06 07:53:36 PM PDT 24
Peak memory 216708 kb
Host smart-3368de72-781e-4a1a-b460-a3b9078ac4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487533528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2487533528
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3544860672
Short name T670
Test name
Test status
Simulation time 46247062 ps
CPU time 1.45 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:53:14 PM PDT 24
Peak memory 216660 kb
Host smart-0bb06d10-8c02-4634-a115-2f1896d967ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544860672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3544860672
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3315485377
Short name T317
Test name
Test status
Simulation time 20395931 ps
CPU time 0.82 seconds
Started Aug 06 07:53:12 PM PDT 24
Finished Aug 06 07:53:13 PM PDT 24
Peak memory 206388 kb
Host smart-f1f7178b-f297-475a-b37a-5c999687750f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315485377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3315485377
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2695506561
Short name T215
Test name
Test status
Simulation time 43529468506 ps
CPU time 23.34 seconds
Started Aug 06 07:53:22 PM PDT 24
Finished Aug 06 07:53:45 PM PDT 24
Peak memory 236608 kb
Host smart-65cae613-07a8-43ff-8638-65ceb97fbda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695506561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2695506561
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2442292366
Short name T769
Test name
Test status
Simulation time 46399671 ps
CPU time 0.72 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:53:14 PM PDT 24
Peak memory 205320 kb
Host smart-4b038f58-1275-4379-899c-71d8555cf4f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442292366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2442292366
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2685891446
Short name T175
Test name
Test status
Simulation time 2548916166 ps
CPU time 7.83 seconds
Started Aug 06 07:53:14 PM PDT 24
Finished Aug 06 07:53:22 PM PDT 24
Peak memory 233144 kb
Host smart-a76472ff-d81b-4da9-88ac-255362fd7589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685891446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2685891446
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1030525755
Short name T991
Test name
Test status
Simulation time 21551942 ps
CPU time 0.73 seconds
Started Aug 06 07:53:11 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 207004 kb
Host smart-c9749d2f-4f6d-4e74-82e8-ab479babc0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030525755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1030525755
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3172487972
Short name T220
Test name
Test status
Simulation time 11125515028 ps
CPU time 64.21 seconds
Started Aug 06 07:53:14 PM PDT 24
Finished Aug 06 07:54:19 PM PDT 24
Peak memory 257628 kb
Host smart-8ef43a38-82cb-495c-9034-b1767612c0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172487972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3172487972
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3531979269
Short name T820
Test name
Test status
Simulation time 10732084109 ps
CPU time 56.37 seconds
Started Aug 06 07:53:24 PM PDT 24
Finished Aug 06 07:54:20 PM PDT 24
Peak memory 249636 kb
Host smart-f8247e1f-bfab-4661-8ebe-5cb880a61f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531979269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3531979269
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1194610068
Short name T1001
Test name
Test status
Simulation time 263540225 ps
CPU time 3.55 seconds
Started Aug 06 07:53:14 PM PDT 24
Finished Aug 06 07:53:18 PM PDT 24
Peak memory 233156 kb
Host smart-c158ddd2-c1fb-4dce-9add-7253cc782105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194610068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1194610068
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1728244829
Short name T725
Test name
Test status
Simulation time 251242511665 ps
CPU time 418.51 seconds
Started Aug 06 07:53:14 PM PDT 24
Finished Aug 06 08:00:12 PM PDT 24
Peak memory 257704 kb
Host smart-a1c21470-d8ef-4c21-9f5c-beb6e45d6204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728244829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1728244829
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.171270206
Short name T969
Test name
Test status
Simulation time 827102127 ps
CPU time 6.7 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:53:20 PM PDT 24
Peak memory 230840 kb
Host smart-ef6fb525-e001-4ac4-aca7-dc7fc0b1610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171270206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.171270206
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1445075784
Short name T862
Test name
Test status
Simulation time 24884045326 ps
CPU time 64.76 seconds
Started Aug 06 07:53:16 PM PDT 24
Finished Aug 06 07:54:21 PM PDT 24
Peak memory 233196 kb
Host smart-3d8aee35-22b9-4d66-8340-ba0cb82a0ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445075784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1445075784
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3784534874
Short name T192
Test name
Test status
Simulation time 5012707122 ps
CPU time 7.8 seconds
Started Aug 06 07:53:17 PM PDT 24
Finished Aug 06 07:53:25 PM PDT 24
Peak memory 224908 kb
Host smart-b016d4a8-6d9e-42cc-a13f-d9bf2494c69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784534874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3784534874
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3039911262
Short name T428
Test name
Test status
Simulation time 7531296274 ps
CPU time 21.62 seconds
Started Aug 06 07:53:22 PM PDT 24
Finished Aug 06 07:53:44 PM PDT 24
Peak memory 224800 kb
Host smart-fa363973-0f8f-4e44-92cf-24164c954a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039911262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3039911262
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2994313598
Short name T843
Test name
Test status
Simulation time 3157003699 ps
CPU time 5.93 seconds
Started Aug 06 07:53:14 PM PDT 24
Finished Aug 06 07:53:20 PM PDT 24
Peak memory 223532 kb
Host smart-739f9b16-edfa-4bc3-85a9-c5b7e8997451
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2994313598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2994313598
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.338823351
Short name T26
Test name
Test status
Simulation time 369415203 ps
CPU time 3.99 seconds
Started Aug 06 07:53:12 PM PDT 24
Finished Aug 06 07:53:16 PM PDT 24
Peak memory 216620 kb
Host smart-212663ed-2c48-42cc-ac6a-c18fb9e85728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338823351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.338823351
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.184554221
Short name T780
Test name
Test status
Simulation time 225703917 ps
CPU time 3.16 seconds
Started Aug 06 07:53:13 PM PDT 24
Finished Aug 06 07:53:17 PM PDT 24
Peak memory 217032 kb
Host smart-d82bb409-c442-4323-8ba0-470fff8fafc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184554221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.184554221
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1482643314
Short name T949
Test name
Test status
Simulation time 518588882 ps
CPU time 2.67 seconds
Started Aug 06 07:53:15 PM PDT 24
Finished Aug 06 07:53:18 PM PDT 24
Peak memory 216724 kb
Host smart-091698d7-30b2-442a-8aad-36acb338f003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482643314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1482643314
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.481287696
Short name T498
Test name
Test status
Simulation time 146277180 ps
CPU time 0.79 seconds
Started Aug 06 07:53:12 PM PDT 24
Finished Aug 06 07:53:13 PM PDT 24
Peak memory 206976 kb
Host smart-e1176369-8e43-43b4-9780-0fe5b000638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481287696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.481287696
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.996096667
Short name T994
Test name
Test status
Simulation time 424162184 ps
CPU time 0.97 seconds
Started Aug 06 07:53:17 PM PDT 24
Finished Aug 06 07:53:18 PM PDT 24
Peak memory 207264 kb
Host smart-d23d870e-76b3-4de5-8ca5-f6af4df678ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996096667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.996096667
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1662070141
Short name T625
Test name
Test status
Simulation time 343710643 ps
CPU time 6.02 seconds
Started Aug 06 07:53:12 PM PDT 24
Finished Aug 06 07:53:18 PM PDT 24
Peak memory 233116 kb
Host smart-f38efac9-4ddc-4daa-9992-beccd62cbe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662070141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1662070141
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3116547710
Short name T599
Test name
Test status
Simulation time 21507158 ps
CPU time 0.78 seconds
Started Aug 06 07:53:30 PM PDT 24
Finished Aug 06 07:53:31 PM PDT 24
Peak memory 205804 kb
Host smart-ca2e738a-5149-45fa-92b4-42818fb294be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116547710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3116547710
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1758876256
Short name T249
Test name
Test status
Simulation time 1367332419 ps
CPU time 5.12 seconds
Started Aug 06 07:53:27 PM PDT 24
Finished Aug 06 07:53:32 PM PDT 24
Peak memory 233092 kb
Host smart-067df883-e84e-4f5e-8de2-c5eddd110203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758876256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1758876256
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2284281675
Short name T548
Test name
Test status
Simulation time 31076446 ps
CPU time 0.75 seconds
Started Aug 06 07:53:14 PM PDT 24
Finished Aug 06 07:53:15 PM PDT 24
Peak memory 206888 kb
Host smart-6fbfa218-678c-411d-bd38-90a4003f5dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284281675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2284281675
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.422649273
Short name T531
Test name
Test status
Simulation time 2214735673 ps
CPU time 13.14 seconds
Started Aug 06 07:53:35 PM PDT 24
Finished Aug 06 07:53:48 PM PDT 24
Peak memory 238700 kb
Host smart-16b13235-656e-48a5-a506-3665bf921f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422649273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.422649273
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.741991484
Short name T229
Test name
Test status
Simulation time 1648822511 ps
CPU time 43.12 seconds
Started Aug 06 07:53:33 PM PDT 24
Finished Aug 06 07:54:16 PM PDT 24
Peak memory 249616 kb
Host smart-caa149ac-08ab-47da-bf53-f2faaadf4e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741991484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.741991484
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.984717337
Short name T462
Test name
Test status
Simulation time 39711290 ps
CPU time 2.72 seconds
Started Aug 06 07:53:34 PM PDT 24
Finished Aug 06 07:53:37 PM PDT 24
Peak memory 233120 kb
Host smart-a6f01016-30d1-4c14-b787-affbf30aff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984717337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.984717337
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3119095922
Short name T159
Test name
Test status
Simulation time 3263247878 ps
CPU time 45.7 seconds
Started Aug 06 07:53:29 PM PDT 24
Finished Aug 06 07:54:15 PM PDT 24
Peak memory 239080 kb
Host smart-53fc2bdb-7abc-42f9-a1c3-2a45a4c3ea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119095922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3119095922
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1753629680
Short name T188
Test name
Test status
Simulation time 555443787 ps
CPU time 7.01 seconds
Started Aug 06 07:53:39 PM PDT 24
Finished Aug 06 07:53:46 PM PDT 24
Peak memory 233140 kb
Host smart-8eae15c8-f22c-45b6-8055-ddb18fd96d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753629680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1753629680
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2354651986
Short name T487
Test name
Test status
Simulation time 114514848 ps
CPU time 3.44 seconds
Started Aug 06 07:53:31 PM PDT 24
Finished Aug 06 07:53:35 PM PDT 24
Peak memory 233136 kb
Host smart-5e1ab440-8427-4e41-8ce5-a3cf40e5fd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354651986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2354651986
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1267276610
Short name T164
Test name
Test status
Simulation time 825208773 ps
CPU time 6.89 seconds
Started Aug 06 07:53:24 PM PDT 24
Finished Aug 06 07:53:31 PM PDT 24
Peak memory 233048 kb
Host smart-221eadfe-b09a-4f12-87bc-0d2d4f4c1c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267276610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1267276610
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2238899239
Short name T747
Test name
Test status
Simulation time 5000504422 ps
CPU time 5.3 seconds
Started Aug 06 07:53:28 PM PDT 24
Finished Aug 06 07:53:34 PM PDT 24
Peak memory 233180 kb
Host smart-a67ec954-cc7e-4ca8-8499-bf1cc16e506c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238899239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2238899239
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4293590066
Short name T792
Test name
Test status
Simulation time 2314449472 ps
CPU time 6.65 seconds
Started Aug 06 07:53:28 PM PDT 24
Finished Aug 06 07:53:35 PM PDT 24
Peak memory 219196 kb
Host smart-6322abea-99fc-4a66-b3e4-1c7ae002d601
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4293590066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4293590066
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3264630930
Short name T181
Test name
Test status
Simulation time 5172354620 ps
CPU time 107.82 seconds
Started Aug 06 07:53:31 PM PDT 24
Finished Aug 06 07:55:19 PM PDT 24
Peak memory 257216 kb
Host smart-ba8d25f3-3cf3-4d5f-a68c-229060ac1e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264630930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3264630930
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1474239711
Short name T465
Test name
Test status
Simulation time 3035601952 ps
CPU time 20.3 seconds
Started Aug 06 07:53:24 PM PDT 24
Finished Aug 06 07:53:44 PM PDT 24
Peak memory 216708 kb
Host smart-c655d469-2d14-43a5-a077-ac67d28adbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474239711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1474239711
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.96965598
Short name T551
Test name
Test status
Simulation time 1221268513 ps
CPU time 8.22 seconds
Started Aug 06 07:53:28 PM PDT 24
Finished Aug 06 07:53:36 PM PDT 24
Peak memory 216660 kb
Host smart-02cc1a8d-d2b0-40ba-8e9b-0bd1fdf88f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96965598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.96965598
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1348545940
Short name T335
Test name
Test status
Simulation time 83798080 ps
CPU time 1.35 seconds
Started Aug 06 07:53:26 PM PDT 24
Finished Aug 06 07:53:28 PM PDT 24
Peak memory 216616 kb
Host smart-72a798ef-731c-493d-9d7a-c086d2048d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348545940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1348545940
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1621616478
Short name T421
Test name
Test status
Simulation time 393322690 ps
CPU time 0.78 seconds
Started Aug 06 07:53:23 PM PDT 24
Finished Aug 06 07:53:24 PM PDT 24
Peak memory 206564 kb
Host smart-ebf41297-2018-4d6b-8701-74b2b5d56f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621616478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1621616478
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4164553068
Short name T723
Test name
Test status
Simulation time 4562510459 ps
CPU time 11.78 seconds
Started Aug 06 07:53:25 PM PDT 24
Finished Aug 06 07:53:37 PM PDT 24
Peak memory 241312 kb
Host smart-44274d56-315a-468e-b9fd-6b646f29c71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164553068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4164553068
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1135196062
Short name T924
Test name
Test status
Simulation time 42265490 ps
CPU time 0.73 seconds
Started Aug 06 07:53:28 PM PDT 24
Finished Aug 06 07:53:28 PM PDT 24
Peak memory 205864 kb
Host smart-05ec4f1f-0e45-4fdd-a163-0ee745336789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135196062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1135196062
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3065522305
Short name T998
Test name
Test status
Simulation time 649139380 ps
CPU time 3.7 seconds
Started Aug 06 07:53:30 PM PDT 24
Finished Aug 06 07:53:34 PM PDT 24
Peak memory 224872 kb
Host smart-8f9410ae-23e8-4c15-868c-f13879e48e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065522305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3065522305
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3470059915
Short name T736
Test name
Test status
Simulation time 29040671 ps
CPU time 0.76 seconds
Started Aug 06 07:53:28 PM PDT 24
Finished Aug 06 07:53:29 PM PDT 24
Peak memory 206032 kb
Host smart-db6653ba-a9db-4760-a3c8-c4a4dea880dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470059915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3470059915
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2661915401
Short name T641
Test name
Test status
Simulation time 61793197305 ps
CPU time 139.43 seconds
Started Aug 06 07:53:29 PM PDT 24
Finished Aug 06 07:55:49 PM PDT 24
Peak memory 257812 kb
Host smart-5c4adf50-2517-45d6-bc80-eb33052bb073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661915401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2661915401
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2897029958
Short name T976
Test name
Test status
Simulation time 7570024665 ps
CPU time 118.71 seconds
Started Aug 06 07:53:35 PM PDT 24
Finished Aug 06 07:55:34 PM PDT 24
Peak memory 263344 kb
Host smart-ce9ef40d-ff29-4568-bae6-f6ce609a5101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897029958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2897029958
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2319700952
Short name T176
Test name
Test status
Simulation time 65775711913 ps
CPU time 174.98 seconds
Started Aug 06 07:53:31 PM PDT 24
Finished Aug 06 07:56:26 PM PDT 24
Peak memory 255840 kb
Host smart-a71120bd-c55b-4c8d-abae-dc4bae2a8a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319700952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2319700952
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1274584890
Short name T297
Test name
Test status
Simulation time 105479347 ps
CPU time 4.6 seconds
Started Aug 06 07:53:30 PM PDT 24
Finished Aug 06 07:53:35 PM PDT 24
Peak memory 224920 kb
Host smart-f83f5fe2-fc2e-4dda-b718-2b53d4e8f744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274584890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1274584890
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2214372503
Short name T983
Test name
Test status
Simulation time 13268261752 ps
CPU time 95.52 seconds
Started Aug 06 07:53:33 PM PDT 24
Finished Aug 06 07:55:08 PM PDT 24
Peak memory 241392 kb
Host smart-622a1942-7c81-451b-a4da-751011d2e027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214372503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2214372503
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2350357782
Short name T742
Test name
Test status
Simulation time 122586792 ps
CPU time 3.29 seconds
Started Aug 06 07:53:31 PM PDT 24
Finished Aug 06 07:53:35 PM PDT 24
Peak memory 224924 kb
Host smart-2fbcb7c3-f1e3-4a39-a5ac-a7563d58256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350357782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2350357782
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4283428898
Short name T182
Test name
Test status
Simulation time 90337746872 ps
CPU time 65.47 seconds
Started Aug 06 07:53:29 PM PDT 24
Finished Aug 06 07:54:35 PM PDT 24
Peak memory 241128 kb
Host smart-fd138a30-bdb0-40cc-b91f-c2db8938a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283428898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4283428898
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3859483318
Short name T257
Test name
Test status
Simulation time 397708673 ps
CPU time 6.63 seconds
Started Aug 06 07:53:32 PM PDT 24
Finished Aug 06 07:53:38 PM PDT 24
Peak memory 233120 kb
Host smart-f0758c58-76c4-4cee-b57a-671fb796d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859483318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3859483318
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3951261346
Short name T627
Test name
Test status
Simulation time 498390265 ps
CPU time 3.48 seconds
Started Aug 06 07:53:30 PM PDT 24
Finished Aug 06 07:53:34 PM PDT 24
Peak memory 233124 kb
Host smart-3f24367f-c568-4af2-994d-32cc07863803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951261346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3951261346
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1901686214
Short name T697
Test name
Test status
Simulation time 241773501 ps
CPU time 5.37 seconds
Started Aug 06 07:53:33 PM PDT 24
Finished Aug 06 07:53:39 PM PDT 24
Peak memory 223624 kb
Host smart-aabcac7b-c240-4ece-9357-8292b88ea3af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1901686214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1901686214
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3414167982
Short name T29
Test name
Test status
Simulation time 36225076043 ps
CPU time 357.75 seconds
Started Aug 06 07:53:25 PM PDT 24
Finished Aug 06 07:59:22 PM PDT 24
Peak memory 268296 kb
Host smart-c3f04ebd-b103-4b5a-8e58-9826787a3af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414167982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3414167982
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1580298531
Short name T896
Test name
Test status
Simulation time 5021120824 ps
CPU time 31.58 seconds
Started Aug 06 07:53:29 PM PDT 24
Finished Aug 06 07:54:00 PM PDT 24
Peak memory 216736 kb
Host smart-79dc39c8-f566-4a67-8417-b5c9bdbb4487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580298531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1580298531
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1262883667
Short name T927
Test name
Test status
Simulation time 4709715986 ps
CPU time 13.57 seconds
Started Aug 06 07:53:26 PM PDT 24
Finished Aug 06 07:53:40 PM PDT 24
Peak memory 216688 kb
Host smart-7166b54c-5f0c-4cd3-8d5b-f86d026774bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262883667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1262883667
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.916398795
Short name T429
Test name
Test status
Simulation time 277486321 ps
CPU time 3.51 seconds
Started Aug 06 07:53:32 PM PDT 24
Finished Aug 06 07:53:36 PM PDT 24
Peak memory 216676 kb
Host smart-0f698d74-6ce7-4eb8-bbe3-b49cf293630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916398795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.916398795
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2636148802
Short name T611
Test name
Test status
Simulation time 33822082 ps
CPU time 0.84 seconds
Started Aug 06 07:53:26 PM PDT 24
Finished Aug 06 07:53:27 PM PDT 24
Peak memory 206392 kb
Host smart-a50955ea-46dc-4392-8c80-e8373b5cd186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636148802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2636148802
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2343286093
Short name T213
Test name
Test status
Simulation time 492822533 ps
CPU time 6.04 seconds
Started Aug 06 07:53:25 PM PDT 24
Finished Aug 06 07:53:32 PM PDT 24
Peak memory 224896 kb
Host smart-7183aa91-fa44-4e29-92af-01fa1fc31f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343286093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2343286093
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1728349864
Short name T63
Test name
Test status
Simulation time 47355075 ps
CPU time 0.76 seconds
Started Aug 06 07:53:29 PM PDT 24
Finished Aug 06 07:53:30 PM PDT 24
Peak memory 205340 kb
Host smart-e6ef95ad-7411-4308-9b8e-f7b443240676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728349864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1728349864
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3732873900
Short name T322
Test name
Test status
Simulation time 471285105 ps
CPU time 5.93 seconds
Started Aug 06 07:53:28 PM PDT 24
Finished Aug 06 07:53:34 PM PDT 24
Peak memory 233156 kb
Host smart-44e857fa-ea2a-4bc2-8ef2-e47bc797aadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732873900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3732873900
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2066241194
Short name T987
Test name
Test status
Simulation time 48244080 ps
CPU time 0.73 seconds
Started Aug 06 07:53:25 PM PDT 24
Finished Aug 06 07:53:26 PM PDT 24
Peak memory 207256 kb
Host smart-03b16bc0-f114-40a9-99f8-612bb71a8028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066241194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2066241194
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.597825909
Short name T872
Test name
Test status
Simulation time 3169193644 ps
CPU time 59.31 seconds
Started Aug 06 07:53:27 PM PDT 24
Finished Aug 06 07:54:26 PM PDT 24
Peak memory 257356 kb
Host smart-1debfde5-3708-4452-a65a-c3641cfe61c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597825909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.597825909
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.814156221
Short name T947
Test name
Test status
Simulation time 3416623384 ps
CPU time 51.18 seconds
Started Aug 06 07:53:38 PM PDT 24
Finished Aug 06 07:54:29 PM PDT 24
Peak memory 241248 kb
Host smart-7a657c2d-bcc0-42da-ae49-fd9704682cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814156221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.814156221
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2488536358
Short name T51
Test name
Test status
Simulation time 9871334492 ps
CPU time 56.4 seconds
Started Aug 06 07:53:34 PM PDT 24
Finished Aug 06 07:54:30 PM PDT 24
Peak memory 255348 kb
Host smart-89593193-b3e5-4630-8cbd-718c41e605be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488536358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2488536358
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1122892245
Short name T435
Test name
Test status
Simulation time 114976448 ps
CPU time 2.95 seconds
Started Aug 06 07:53:32 PM PDT 24
Finished Aug 06 07:53:35 PM PDT 24
Peak memory 224860 kb
Host smart-5632460e-ff6a-43ea-b2ff-959769e65f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122892245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1122892245
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3165716007
Short name T814
Test name
Test status
Simulation time 657410174 ps
CPU time 5.91 seconds
Started Aug 06 07:53:29 PM PDT 24
Finished Aug 06 07:53:35 PM PDT 24
Peak memory 224896 kb
Host smart-5c5c6d9a-b0fc-4475-94b8-f0bd063e8c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165716007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3165716007
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1828345937
Short name T267
Test name
Test status
Simulation time 191505235 ps
CPU time 4.76 seconds
Started Aug 06 07:53:34 PM PDT 24
Finished Aug 06 07:53:38 PM PDT 24
Peak memory 233132 kb
Host smart-7ebc1321-467c-4989-86ca-25185a11049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828345937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1828345937
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.327244506
Short name T654
Test name
Test status
Simulation time 138213575 ps
CPU time 3.4 seconds
Started Aug 06 07:53:33 PM PDT 24
Finished Aug 06 07:53:37 PM PDT 24
Peak memory 233132 kb
Host smart-dcd5224f-31ca-4dac-8977-2b477ea28502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327244506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.327244506
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1816570725
Short name T434
Test name
Test status
Simulation time 12240715613 ps
CPU time 8.08 seconds
Started Aug 06 07:53:27 PM PDT 24
Finished Aug 06 07:53:35 PM PDT 24
Peak memory 225004 kb
Host smart-cbe3123f-fbb0-4aba-b174-97c53cc0cf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816570725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1816570725
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3073523049
Short name T981
Test name
Test status
Simulation time 299136687 ps
CPU time 3.94 seconds
Started Aug 06 07:53:34 PM PDT 24
Finished Aug 06 07:53:38 PM PDT 24
Peak memory 223536 kb
Host smart-5dfbae38-c352-49fc-a049-3ac04fa7afd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3073523049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3073523049
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3353757582
Short name T19
Test name
Test status
Simulation time 32598654764 ps
CPU time 173.24 seconds
Started Aug 06 07:53:33 PM PDT 24
Finished Aug 06 07:56:26 PM PDT 24
Peak memory 251488 kb
Host smart-5f867ea4-7608-44d7-a6c5-3b9f22448d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353757582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3353757582
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2554294570
Short name T594
Test name
Test status
Simulation time 3844643641 ps
CPU time 28.65 seconds
Started Aug 06 07:53:35 PM PDT 24
Finished Aug 06 07:54:04 PM PDT 24
Peak memory 220564 kb
Host smart-5c7db559-1633-4b93-ac34-7f3ff13ebfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554294570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2554294570
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2926676146
Short name T337
Test name
Test status
Simulation time 1571447866 ps
CPU time 3.67 seconds
Started Aug 06 07:53:27 PM PDT 24
Finished Aug 06 07:53:31 PM PDT 24
Peak memory 216624 kb
Host smart-5c98f87d-a48b-46e6-aa6b-e8917b062ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926676146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2926676146
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3274833411
Short name T381
Test name
Test status
Simulation time 17538094 ps
CPU time 0.87 seconds
Started Aug 06 07:53:31 PM PDT 24
Finished Aug 06 07:53:33 PM PDT 24
Peak memory 207404 kb
Host smart-8afe74fd-940b-454e-96ea-9a9f913878b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274833411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3274833411
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3599048543
Short name T852
Test name
Test status
Simulation time 57176821 ps
CPU time 0.75 seconds
Started Aug 06 07:53:27 PM PDT 24
Finished Aug 06 07:53:28 PM PDT 24
Peak memory 206368 kb
Host smart-d1d24995-90e9-4d8e-b032-ba61d30707f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599048543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3599048543
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1769933345
Short name T804
Test name
Test status
Simulation time 533960547 ps
CPU time 3.53 seconds
Started Aug 06 07:53:37 PM PDT 24
Finished Aug 06 07:53:40 PM PDT 24
Peak memory 224924 kb
Host smart-b168c31b-71ce-4bea-9f8f-c58951b86cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769933345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1769933345
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.496662907
Short name T773
Test name
Test status
Simulation time 15501241 ps
CPU time 0.69 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:46 PM PDT 24
Peak memory 205860 kb
Host smart-66583a03-6f9b-457b-bf41-eaf730a6501b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496662907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.496662907
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.980729639
Short name T253
Test name
Test status
Simulation time 161758733 ps
CPU time 3.12 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:49 PM PDT 24
Peak memory 225092 kb
Host smart-f0179e2e-6031-403c-a33a-398df045d8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980729639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.980729639
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2742416116
Short name T476
Test name
Test status
Simulation time 14986176 ps
CPU time 0.76 seconds
Started Aug 06 07:53:32 PM PDT 24
Finished Aug 06 07:53:33 PM PDT 24
Peak memory 205912 kb
Host smart-b85a5139-a522-4dd3-b991-64041c3fd986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742416116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2742416116
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.354756079
Short name T228
Test name
Test status
Simulation time 524973645 ps
CPU time 10.41 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:55 PM PDT 24
Peak memory 241332 kb
Host smart-d10ee408-398b-4cb5-8138-9636d708c01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354756079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.354756079
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2264263166
Short name T303
Test name
Test status
Simulation time 131570743605 ps
CPU time 315.73 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 07:59:03 PM PDT 24
Peak memory 264720 kb
Host smart-8b96e46d-50f6-4b2d-811a-69299fb215f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264263166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2264263166
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2194714592
Short name T315
Test name
Test status
Simulation time 19502653330 ps
CPU time 109.33 seconds
Started Aug 06 07:53:42 PM PDT 24
Finished Aug 06 07:55:31 PM PDT 24
Peak memory 249572 kb
Host smart-cd82e94f-eb22-4522-9ee0-4e17c0d7730f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194714592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2194714592
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4247634884
Short name T707
Test name
Test status
Simulation time 625506291 ps
CPU time 9.15 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:53:59 PM PDT 24
Peak memory 234012 kb
Host smart-93e5ff39-2296-4898-9c00-3483d4d14be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247634884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4247634884
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2810220011
Short name T740
Test name
Test status
Simulation time 4802058088 ps
CPU time 46.65 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:37 PM PDT 24
Peak memory 249784 kb
Host smart-e5ecbc1d-29c5-46e9-ac44-b62a817952f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810220011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2810220011
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.774012390
Short name T737
Test name
Test status
Simulation time 9679212753 ps
CPU time 22.25 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 224992 kb
Host smart-ae6227f2-4890-450d-a968-a474131e8fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774012390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.774012390
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.450026614
Short name T619
Test name
Test status
Simulation time 5716777084 ps
CPU time 60.16 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:54:44 PM PDT 24
Peak memory 235032 kb
Host smart-c2a05da6-4ff6-4ee2-8044-9f8403e2f6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450026614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.450026614
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.929175482
Short name T274
Test name
Test status
Simulation time 383191758 ps
CPU time 5.39 seconds
Started Aug 06 07:53:33 PM PDT 24
Finished Aug 06 07:53:38 PM PDT 24
Peak memory 224820 kb
Host smart-2b5dbbf8-5728-469e-ad54-1b9dc73377af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929175482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.929175482
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.669046104
Short name T756
Test name
Test status
Simulation time 73534277 ps
CPU time 2.08 seconds
Started Aug 06 07:53:34 PM PDT 24
Finished Aug 06 07:53:37 PM PDT 24
Peak memory 223912 kb
Host smart-65b4b64a-6e5e-461a-b4c7-686c84e47d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669046104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.669046104
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.900552343
Short name T637
Test name
Test status
Simulation time 916476387 ps
CPU time 5.43 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:50 PM PDT 24
Peak memory 220460 kb
Host smart-af1b3ea4-84af-49b2-8b22-8db0dc9af7d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=900552343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.900552343
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1663409221
Short name T18
Test name
Test status
Simulation time 24211364821 ps
CPU time 217.45 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 07:57:25 PM PDT 24
Peak memory 249688 kb
Host smart-c439d30e-b049-41e8-bbd9-5fc95b5d7e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663409221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1663409221
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1185674881
Short name T302
Test name
Test status
Simulation time 1677460453 ps
CPU time 28.43 seconds
Started Aug 06 07:53:34 PM PDT 24
Finished Aug 06 07:54:03 PM PDT 24
Peak memory 216668 kb
Host smart-27d82b73-504d-43dc-b203-4ca4413ddb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185674881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1185674881
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.156356026
Short name T463
Test name
Test status
Simulation time 2485523110 ps
CPU time 2.65 seconds
Started Aug 06 07:53:36 PM PDT 24
Finished Aug 06 07:53:38 PM PDT 24
Peak memory 216688 kb
Host smart-914d7dde-b23c-414e-82f2-bd83875cd8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156356026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.156356026
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1393124635
Short name T316
Test name
Test status
Simulation time 53674565 ps
CPU time 1 seconds
Started Aug 06 07:53:33 PM PDT 24
Finished Aug 06 07:53:35 PM PDT 24
Peak memory 207568 kb
Host smart-61ba6ae9-0529-40f0-882c-23135c0ad8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393124635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1393124635
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2712481639
Short name T24
Test name
Test status
Simulation time 157709757 ps
CPU time 0.83 seconds
Started Aug 06 07:53:28 PM PDT 24
Finished Aug 06 07:53:29 PM PDT 24
Peak memory 207432 kb
Host smart-0b165ce8-d1ff-41ba-9f16-735e7737b5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712481639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2712481639
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1156816638
Short name T12
Test name
Test status
Simulation time 2499814259 ps
CPU time 9.4 seconds
Started Aug 06 07:53:42 PM PDT 24
Finished Aug 06 07:53:51 PM PDT 24
Peak memory 218648 kb
Host smart-c5e27887-2035-4a83-9564-141ff6037566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156816638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1156816638
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2736766802
Short name T883
Test name
Test status
Simulation time 17815891 ps
CPU time 0.7 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:45 PM PDT 24
Peak memory 205236 kb
Host smart-cc54b45a-99d4-4ed1-8f8c-8f6d16906be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736766802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2736766802
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3337623833
Short name T726
Test name
Test status
Simulation time 135847001 ps
CPU time 3.33 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:48 PM PDT 24
Peak memory 233156 kb
Host smart-aad85e55-101e-4a11-b5d5-56be3f184dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337623833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3337623833
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4244365006
Short name T743
Test name
Test status
Simulation time 65100137 ps
CPU time 0.79 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:46 PM PDT 24
Peak memory 207040 kb
Host smart-0d0ed1e5-8290-42d0-b5f1-7a28e4e3be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244365006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4244365006
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.479156527
Short name T331
Test name
Test status
Simulation time 15576903055 ps
CPU time 64.81 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:55 PM PDT 24
Peak memory 249632 kb
Host smart-e1fc693d-a4af-41a3-be73-400f3d880607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479156527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.479156527
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1502637712
Short name T362
Test name
Test status
Simulation time 145468465455 ps
CPU time 49.67 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:40 PM PDT 24
Peak memory 237924 kb
Host smart-2efdd44a-d422-4965-b104-3cbf627b3ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502637712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1502637712
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.983791444
Short name T217
Test name
Test status
Simulation time 21615207676 ps
CPU time 170.31 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:56:35 PM PDT 24
Peak memory 235636 kb
Host smart-ba47ca34-29dc-49be-8435-458dc94f5b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983791444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.983791444
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3249294973
Short name T911
Test name
Test status
Simulation time 3081822437 ps
CPU time 44.5 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:54:33 PM PDT 24
Peak memory 233148 kb
Host smart-67e8912e-34d0-419b-819b-3abe45377dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249294973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3249294973
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1593934544
Short name T564
Test name
Test status
Simulation time 4274522550 ps
CPU time 9.08 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:53 PM PDT 24
Peak memory 224892 kb
Host smart-09d6d834-d7c3-4a96-bd15-6fa272402052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593934544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1593934544
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.856018777
Short name T876
Test name
Test status
Simulation time 5188406896 ps
CPU time 43.86 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:35 PM PDT 24
Peak memory 233244 kb
Host smart-31cf6120-dbe6-490a-81fb-ee941c743d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856018777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.856018777
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3152944859
Short name T775
Test name
Test status
Simulation time 779706658 ps
CPU time 3.61 seconds
Started Aug 06 07:53:41 PM PDT 24
Finished Aug 06 07:53:45 PM PDT 24
Peak memory 233128 kb
Host smart-dab970da-4403-485a-bc09-b95bc1bcf439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152944859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3152944859
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1502642059
Short name T678
Test name
Test status
Simulation time 7658099757 ps
CPU time 6.69 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 07:53:54 PM PDT 24
Peak memory 224924 kb
Host smart-dc806564-ab5f-4b62-97b9-3dc9f313865c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502642059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1502642059
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1653454424
Short name T392
Test name
Test status
Simulation time 221055187 ps
CPU time 4.27 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:53:55 PM PDT 24
Peak memory 223248 kb
Host smart-78345aa8-b21b-4641-9f42-3372987de23d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1653454424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1653454424
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1628785942
Short name T130
Test name
Test status
Simulation time 114285876656 ps
CPU time 338.74 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:59:23 PM PDT 24
Peak memory 273408 kb
Host smart-ac67da3c-c6a1-43d5-a090-4d45c805e8ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628785942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1628785942
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2944196927
Short name T445
Test name
Test status
Simulation time 4152309979 ps
CPU time 18.76 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:09 PM PDT 24
Peak memory 220784 kb
Host smart-ee77aaef-3b8d-4a84-8dd8-0f8834893e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944196927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2944196927
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.167933952
Short name T419
Test name
Test status
Simulation time 1720673925 ps
CPU time 2.23 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:47 PM PDT 24
Peak memory 216648 kb
Host smart-28b2b9ff-3ad6-4904-acb2-3a48446b5829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167933952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.167933952
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.126499843
Short name T967
Test name
Test status
Simulation time 215027256 ps
CPU time 1.22 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:46 PM PDT 24
Peak memory 216724 kb
Host smart-0714e037-c23c-4ea9-8f52-d8c4ee72faab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126499843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.126499843
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3401334808
Short name T505
Test name
Test status
Simulation time 103716040 ps
CPU time 0.84 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:45 PM PDT 24
Peak memory 206324 kb
Host smart-bc7f3889-f164-457f-bb82-465f50b5218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401334808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3401334808
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3505912736
Short name T197
Test name
Test status
Simulation time 6842300019 ps
CPU time 9.67 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:54 PM PDT 24
Peak memory 233212 kb
Host smart-60e16b5e-bf5b-4030-bd65-23792e087fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505912736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3505912736
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2393373423
Short name T778
Test name
Test status
Simulation time 47284635 ps
CPU time 0.71 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:45 PM PDT 24
Peak memory 205824 kb
Host smart-d4dcc4b4-9302-479a-ba25-7def13f625a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393373423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2393373423
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.982268519
Short name T271
Test name
Test status
Simulation time 956656651 ps
CPU time 11.35 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:56 PM PDT 24
Peak memory 233192 kb
Host smart-583746c6-2b99-411d-a0ce-9dcf11ef8f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982268519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.982268519
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.925432210
Short name T877
Test name
Test status
Simulation time 60877444 ps
CPU time 0.87 seconds
Started Aug 06 07:53:46 PM PDT 24
Finished Aug 06 07:53:47 PM PDT 24
Peak memory 207064 kb
Host smart-a6f3c0bd-04a1-4037-a190-4bb59434fc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925432210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.925432210
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2085799941
Short name T44
Test name
Test status
Simulation time 246383742363 ps
CPU time 234.9 seconds
Started Aug 06 07:53:43 PM PDT 24
Finished Aug 06 07:57:38 PM PDT 24
Peak memory 251648 kb
Host smart-6aa1b4cd-7a4c-470d-97d6-9bdc9c2c5c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085799941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2085799941
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1019182463
Short name T555
Test name
Test status
Simulation time 4890876701 ps
CPU time 26.36 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:16 PM PDT 24
Peak memory 256228 kb
Host smart-2c4d64c0-99db-46f6-beee-328d6f554d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019182463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1019182463
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2677069829
Short name T60
Test name
Test status
Simulation time 1012318785 ps
CPU time 14.16 seconds
Started Aug 06 07:53:39 PM PDT 24
Finished Aug 06 07:53:53 PM PDT 24
Peak memory 241364 kb
Host smart-87ce2a5a-5df5-4cfc-83ae-b6a61e7941ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677069829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2677069829
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.437945629
Short name T543
Test name
Test status
Simulation time 6878683210 ps
CPU time 25.67 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:54:13 PM PDT 24
Peak memory 251968 kb
Host smart-91cd5b4d-6905-4b1e-8153-d486a451ea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437945629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.437945629
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3600350629
Short name T219
Test name
Test status
Simulation time 294187622 ps
CPU time 4.63 seconds
Started Aug 06 07:53:43 PM PDT 24
Finished Aug 06 07:53:48 PM PDT 24
Peak memory 224900 kb
Host smart-6f712570-943f-47d6-9d8b-b04a79a49c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600350629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3600350629
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.659839017
Short name T833
Test name
Test status
Simulation time 36952306 ps
CPU time 2.68 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 07:53:50 PM PDT 24
Peak memory 233140 kb
Host smart-5af0def9-398d-4df7-a806-e8d4f41dc2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659839017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.659839017
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3417590088
Short name T1004
Test name
Test status
Simulation time 1144586799 ps
CPU time 8.45 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 07:53:56 PM PDT 24
Peak memory 233076 kb
Host smart-8524f9c8-965b-440e-986d-0c706e02561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417590088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3417590088
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2255589590
Short name T425
Test name
Test status
Simulation time 28115051927 ps
CPU time 22.31 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:13 PM PDT 24
Peak memory 233216 kb
Host smart-20f3bbd6-0655-47c1-8380-e3d25f0c054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255589590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2255589590
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2216496284
Short name T423
Test name
Test status
Simulation time 3122444793 ps
CPU time 11.54 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:56 PM PDT 24
Peak memory 223068 kb
Host smart-82ab44c9-1c98-43c8-a94b-2e67203e0b35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2216496284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2216496284
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.124180207
Short name T631
Test name
Test status
Simulation time 3592697821 ps
CPU time 20.58 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:11 PM PDT 24
Peak memory 216724 kb
Host smart-8da2d4b4-b2a3-4aab-b067-1f6b1b9f304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124180207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.124180207
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1794072518
Short name T841
Test name
Test status
Simulation time 15536158165 ps
CPU time 10.56 seconds
Started Aug 06 07:53:46 PM PDT 24
Finished Aug 06 07:53:57 PM PDT 24
Peak memory 216672 kb
Host smart-51e560af-c8d8-42b5-80cd-dac4f9c2b18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794072518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1794072518
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2947056495
Short name T496
Test name
Test status
Simulation time 189383834 ps
CPU time 1.49 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:46 PM PDT 24
Peak memory 216692 kb
Host smart-b2acf2d1-9b69-4ba4-87f3-7cf26da8dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947056495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2947056495
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.627052269
Short name T406
Test name
Test status
Simulation time 108974968 ps
CPU time 0.83 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 07:53:48 PM PDT 24
Peak memory 206376 kb
Host smart-27d6b3d0-f027-400f-97d7-bab7f0ee5781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627052269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.627052269
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1547426548
Short name T455
Test name
Test status
Simulation time 28809490177 ps
CPU time 7.33 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:52 PM PDT 24
Peak memory 233200 kb
Host smart-246d27a1-8c41-4cd7-87c9-278ae425954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547426548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1547426548
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.128248881
Short name T490
Test name
Test status
Simulation time 72886263 ps
CPU time 0.71 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:45 PM PDT 24
Peak memory 205788 kb
Host smart-f992dee0-ed4a-40f0-9aba-c40f99622160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128248881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.128248881
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1790627474
Short name T491
Test name
Test status
Simulation time 814044041 ps
CPU time 3.75 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:51 PM PDT 24
Peak memory 224972 kb
Host smart-a614a081-f443-48ed-acbf-b2d76837c4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790627474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1790627474
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1344905023
Short name T373
Test name
Test status
Simulation time 40348479 ps
CPU time 0.75 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:46 PM PDT 24
Peak memory 206996 kb
Host smart-98b42c8e-96f9-4ea0-8280-73069c8e1cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344905023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1344905023
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2863863670
Short name T575
Test name
Test status
Simulation time 35308496214 ps
CPU time 83.75 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:55:09 PM PDT 24
Peak memory 255596 kb
Host smart-69876c7a-b237-4f75-828f-50612937ce4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863863670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2863863670
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3654194196
Short name T309
Test name
Test status
Simulation time 13282256620 ps
CPU time 48.69 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:39 PM PDT 24
Peak memory 257828 kb
Host smart-bffa47fe-073e-4049-8f3e-884d048750f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654194196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3654194196
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.970778403
Short name T691
Test name
Test status
Simulation time 1934146360 ps
CPU time 39.8 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:54:28 PM PDT 24
Peak memory 251168 kb
Host smart-4aa41b4e-3bb1-4583-b58a-13d674ba37b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970778403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.970778403
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.338846091
Short name T293
Test name
Test status
Simulation time 3374119134 ps
CPU time 48.51 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:54:32 PM PDT 24
Peak memory 249560 kb
Host smart-475de55b-8068-4057-9322-45fa54bccdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338846091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.338846091
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1025156029
Short name T741
Test name
Test status
Simulation time 30032292022 ps
CPU time 46.25 seconds
Started Aug 06 07:53:46 PM PDT 24
Finished Aug 06 07:54:32 PM PDT 24
Peak memory 249524 kb
Host smart-c2a83a26-67cb-44b9-af5a-828f63f17193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025156029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1025156029
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1937065651
Short name T621
Test name
Test status
Simulation time 375624877 ps
CPU time 6.92 seconds
Started Aug 06 07:53:49 PM PDT 24
Finished Aug 06 07:53:56 PM PDT 24
Peak memory 233160 kb
Host smart-7a74f21c-215f-4b2c-aa6c-0e4adcf00edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937065651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1937065651
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3320770696
Short name T880
Test name
Test status
Simulation time 4413156652 ps
CPU time 51.27 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 07:54:39 PM PDT 24
Peak memory 233180 kb
Host smart-acd3c9f9-44ae-4276-8c0e-dec27772afc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320770696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3320770696
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4180826805
Short name T464
Test name
Test status
Simulation time 4249304961 ps
CPU time 9.76 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:55 PM PDT 24
Peak memory 233108 kb
Host smart-31320cac-d37d-4e72-bc89-139869c096b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180826805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4180826805
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.346680434
Short name T721
Test name
Test status
Simulation time 3656296197 ps
CPU time 7.4 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:56 PM PDT 24
Peak memory 233024 kb
Host smart-ac47d18b-8f4a-4538-b329-551dda0aea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346680434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.346680434
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1168478421
Short name T514
Test name
Test status
Simulation time 59372522 ps
CPU time 3.03 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:51 PM PDT 24
Peak memory 219288 kb
Host smart-92715cd0-fbaf-4190-b1ac-9e1d457fa265
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1168478421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1168478421
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3069551610
Short name T222
Test name
Test status
Simulation time 52051854736 ps
CPU time 159.23 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:56:24 PM PDT 24
Peak memory 257868 kb
Host smart-2ab3629d-9542-4880-bcc1-7832d91f249e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069551610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3069551610
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3919740236
Short name T301
Test name
Test status
Simulation time 12795142006 ps
CPU time 19.36 seconds
Started Aug 06 07:53:47 PM PDT 24
Finished Aug 06 07:54:07 PM PDT 24
Peak memory 216788 kb
Host smart-1a3dfba9-5b22-48d2-b8a8-673946e7051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919740236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3919740236
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2682216566
Short name T964
Test name
Test status
Simulation time 4417021580 ps
CPU time 6.29 seconds
Started Aug 06 07:53:54 PM PDT 24
Finished Aug 06 07:54:01 PM PDT 24
Peak memory 216696 kb
Host smart-8d57ffcf-999d-4524-9bce-abd1eadf84bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682216566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2682216566
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1735796347
Short name T4
Test name
Test status
Simulation time 65681066 ps
CPU time 2.18 seconds
Started Aug 06 07:53:49 PM PDT 24
Finished Aug 06 07:53:51 PM PDT 24
Peak memory 216632 kb
Host smart-a528884b-2224-4439-9eb3-9d4da7f643d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735796347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1735796347
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2957361533
Short name T922
Test name
Test status
Simulation time 84958953 ps
CPU time 1.02 seconds
Started Aug 06 07:53:49 PM PDT 24
Finished Aug 06 07:53:50 PM PDT 24
Peak memory 207444 kb
Host smart-602b9ea9-3eac-4cda-84e0-3f92b24f737d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957361533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2957361533
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1688708463
Short name T439
Test name
Test status
Simulation time 324569193 ps
CPU time 3 seconds
Started Aug 06 07:53:44 PM PDT 24
Finished Aug 06 07:53:47 PM PDT 24
Peak memory 241316 kb
Host smart-8741f07f-decc-4bd6-bc80-f5491b79c08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688708463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1688708463
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3374303023
Short name T558
Test name
Test status
Simulation time 19809607 ps
CPU time 0.73 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:49 PM PDT 24
Peak memory 205780 kb
Host smart-4bc80a47-3f64-4edf-9fa5-efab8a2db737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374303023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3374303023
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.585386013
Short name T685
Test name
Test status
Simulation time 1712114559 ps
CPU time 4.71 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:53 PM PDT 24
Peak memory 233152 kb
Host smart-c6fe6995-5562-4077-bd55-216e5362418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585386013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.585386013
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2756651432
Short name T329
Test name
Test status
Simulation time 46046898 ps
CPU time 0.81 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:53:51 PM PDT 24
Peak memory 205936 kb
Host smart-a9f6e9d1-2747-4003-abe7-afaf75cc4f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756651432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2756651432
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1799859665
Short name T290
Test name
Test status
Simulation time 5224155002 ps
CPU time 102.08 seconds
Started Aug 06 07:53:46 PM PDT 24
Finished Aug 06 07:55:28 PM PDT 24
Peak memory 267600 kb
Host smart-4e2bec6f-8c95-4bda-ae86-a9670adbf32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799859665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1799859665
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3804979597
Short name T574
Test name
Test status
Simulation time 12982575574 ps
CPU time 61.42 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:54:52 PM PDT 24
Peak memory 249720 kb
Host smart-818f240e-9206-45f8-b269-82aa9971bef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804979597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3804979597
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.995478661
Short name T576
Test name
Test status
Simulation time 356474728 ps
CPU time 9.94 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:58 PM PDT 24
Peak memory 233088 kb
Host smart-68412d36-5fc0-4901-84a8-324a93950dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995478661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.995478661
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.4035837470
Short name T827
Test name
Test status
Simulation time 11501895217 ps
CPU time 110.48 seconds
Started Aug 06 07:53:49 PM PDT 24
Finished Aug 06 07:55:39 PM PDT 24
Peak memory 249612 kb
Host smart-664d6e08-1087-40d6-ae68-b2678d792591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035837470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.4035837470
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1239143129
Short name T582
Test name
Test status
Simulation time 214223923 ps
CPU time 5.54 seconds
Started Aug 06 07:53:49 PM PDT 24
Finished Aug 06 07:53:54 PM PDT 24
Peak memory 233176 kb
Host smart-1839284b-8db1-4f2e-a52d-9e96273eb505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239143129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1239143129
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1886313543
Short name T158
Test name
Test status
Simulation time 21949274089 ps
CPU time 23.2 seconds
Started Aug 06 07:53:43 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 225052 kb
Host smart-8008edb6-42ee-40ce-8fb6-33dd5c9455e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886313543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1886313543
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4057365137
Short name T501
Test name
Test status
Simulation time 593119862 ps
CPU time 4.15 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:49 PM PDT 24
Peak memory 224868 kb
Host smart-79eff641-36d4-4434-9769-1520de4ed43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057365137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4057365137
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.670839451
Short name T642
Test name
Test status
Simulation time 554168806 ps
CPU time 6.05 seconds
Started Aug 06 07:53:51 PM PDT 24
Finished Aug 06 07:53:57 PM PDT 24
Peak memory 239544 kb
Host smart-ee62630a-b18f-4445-b4e5-f7c21b1ca6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670839451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.670839451
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2894428212
Short name T446
Test name
Test status
Simulation time 81240868 ps
CPU time 3.55 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:53:54 PM PDT 24
Peak memory 220484 kb
Host smart-75067812-5868-47f5-bd26-26ca85ac22ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2894428212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2894428212
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3515306787
Short name T1000
Test name
Test status
Simulation time 160174454187 ps
CPU time 652.35 seconds
Started Aug 06 07:53:52 PM PDT 24
Finished Aug 06 08:04:45 PM PDT 24
Peak memory 265416 kb
Host smart-5bf1c942-6128-48d5-8a01-933daf8b272d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515306787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3515306787
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2903296257
Short name T1
Test name
Test status
Simulation time 6743781090 ps
CPU time 9.78 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:53:59 PM PDT 24
Peak memory 220264 kb
Host smart-92fa7c68-2aba-4a0d-9d95-c5ef366722ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903296257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2903296257
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1799049380
Short name T615
Test name
Test status
Simulation time 4550675907 ps
CPU time 3.76 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:52 PM PDT 24
Peak memory 216636 kb
Host smart-a0ac5351-d320-4968-8e5e-e314911a9892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799049380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1799049380
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3750905810
Short name T676
Test name
Test status
Simulation time 45780152 ps
CPU time 1.32 seconds
Started Aug 06 07:53:49 PM PDT 24
Finished Aug 06 07:53:51 PM PDT 24
Peak memory 208436 kb
Host smart-e23dc020-ed69-48c0-9d1e-d42105eaf3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750905810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3750905810
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.401014163
Short name T404
Test name
Test status
Simulation time 43205267 ps
CPU time 0.82 seconds
Started Aug 06 07:53:45 PM PDT 24
Finished Aug 06 07:53:46 PM PDT 24
Peak memory 206360 kb
Host smart-72d663d0-f8f8-407b-84ad-4d19cebb8187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401014163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.401014163
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3843647926
Short name T714
Test name
Test status
Simulation time 48429769772 ps
CPU time 34.41 seconds
Started Aug 06 07:53:46 PM PDT 24
Finished Aug 06 07:54:20 PM PDT 24
Peak memory 251672 kb
Host smart-29038e60-28c7-4082-b283-710dab32fd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843647926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3843647926
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.550538011
Short name T821
Test name
Test status
Simulation time 11735256 ps
CPU time 0.72 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:52:06 PM PDT 24
Peak memory 205820 kb
Host smart-3bc857b5-0604-4bba-9f05-e12318ae6c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550538011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.550538011
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1068751960
Short name T660
Test name
Test status
Simulation time 375017189 ps
CPU time 4.27 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:03 PM PDT 24
Peak memory 224852 kb
Host smart-05462a34-3e61-4132-a9d4-a2bbf4028694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068751960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1068751960
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3492635384
Short name T350
Test name
Test status
Simulation time 64066990 ps
CPU time 0.81 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:52:03 PM PDT 24
Peak memory 206948 kb
Host smart-a1adf4f8-2b01-46e0-8692-ae1478eee637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492635384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3492635384
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3740673001
Short name T275
Test name
Test status
Simulation time 45877183551 ps
CPU time 299.35 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:56:57 PM PDT 24
Peak memory 254888 kb
Host smart-68128603-ad72-4c3d-b884-d9e71b2d5511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740673001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3740673001
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3203171542
Short name T610
Test name
Test status
Simulation time 2124230781 ps
CPU time 36.78 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 241336 kb
Host smart-13d594f6-2986-42f3-849f-7ef17b007dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203171542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3203171542
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4096700373
Short name T50
Test name
Test status
Simulation time 8073155755 ps
CPU time 108.56 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:53:54 PM PDT 24
Peak memory 251116 kb
Host smart-1b304b25-11a7-42f2-b24b-072c7d055ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096700373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.4096700373
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4185609676
Short name T638
Test name
Test status
Simulation time 14056817 ps
CPU time 0.73 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:51:59 PM PDT 24
Peak memory 216120 kb
Host smart-a7e05e97-feea-4a1c-b79b-5b6bd2fb651a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185609676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4185609676
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.138299752
Short name T788
Test name
Test status
Simulation time 30123996 ps
CPU time 2.25 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:52:00 PM PDT 24
Peak memory 224552 kb
Host smart-b1e73753-1d66-4617-af25-3b1d5c877175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138299752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.138299752
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.692886775
Short name T834
Test name
Test status
Simulation time 11433750215 ps
CPU time 20.91 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:52:18 PM PDT 24
Peak memory 239056 kb
Host smart-932895b4-baf3-4ae8-82c4-fb6fe0e597e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692886775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.692886775
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2604524666
Short name T966
Test name
Test status
Simulation time 381530387 ps
CPU time 5.43 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:05 PM PDT 24
Peak memory 233368 kb
Host smart-328fc497-7250-4542-bdee-c10741700da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604524666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2604524666
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.591266929
Short name T545
Test name
Test status
Simulation time 5373534870 ps
CPU time 7.64 seconds
Started Aug 06 07:52:07 PM PDT 24
Finished Aug 06 07:52:15 PM PDT 24
Peak memory 241044 kb
Host smart-d2808595-0fdc-4232-a724-2246c1cd8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591266929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.591266929
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.232176757
Short name T632
Test name
Test status
Simulation time 141724723 ps
CPU time 4.34 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:04 PM PDT 24
Peak memory 223224 kb
Host smart-ef681089-8521-4e1b-bc60-27ea3fa3d121
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=232176757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.232176757
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.929195848
Short name T72
Test name
Test status
Simulation time 38742682 ps
CPU time 0.98 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:52:06 PM PDT 24
Peak memory 235800 kb
Host smart-27d79f12-bd7d-440d-a42d-b259f39b9a50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929195848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.929195848
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2062797659
Short name T313
Test name
Test status
Simulation time 15780885467 ps
CPU time 20.45 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:20 PM PDT 24
Peak memory 216908 kb
Host smart-86ffa0b0-a3be-4329-926e-f96ca758ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062797659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2062797659
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.127048875
Short name T342
Test name
Test status
Simulation time 1483451932 ps
CPU time 3.6 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:04 PM PDT 24
Peak memory 216852 kb
Host smart-c30f5d6c-0010-4dc9-81dc-594463ac18ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127048875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.127048875
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1592296589
Short name T390
Test name
Test status
Simulation time 70265921 ps
CPU time 0.84 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:00 PM PDT 24
Peak memory 207640 kb
Host smart-76d302b8-7e19-4e7a-ad85-7399ed6a848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592296589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1592296589
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3424611342
Short name T396
Test name
Test status
Simulation time 57401733 ps
CPU time 0.73 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:00 PM PDT 24
Peak memory 206572 kb
Host smart-91b30110-c8b5-44e5-a3a6-d9d42ff86f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424611342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3424611342
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1108252980
Short name T483
Test name
Test status
Simulation time 32283443214 ps
CPU time 21.78 seconds
Started Aug 06 07:52:08 PM PDT 24
Finished Aug 06 07:52:29 PM PDT 24
Peak memory 233152 kb
Host smart-9e608d1b-cb61-4be4-b786-7b3191d3a788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108252980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1108252980
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2101341902
Short name T662
Test name
Test status
Simulation time 40559209 ps
CPU time 0.75 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:02 PM PDT 24
Peak memory 205844 kb
Host smart-4cda7318-189a-4e79-ad09-0a72fc6cde41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101341902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2101341902
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1698192026
Short name T784
Test name
Test status
Simulation time 33019897 ps
CPU time 2.53 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:05 PM PDT 24
Peak memory 224908 kb
Host smart-79122109-5c0d-4b8d-aff9-15c572d3a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698192026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1698192026
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2150035531
Short name T904
Test name
Test status
Simulation time 35414522 ps
CPU time 0.81 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:53:51 PM PDT 24
Peak memory 206992 kb
Host smart-9963e697-ebc8-4c4f-a21b-e39550948c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150035531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2150035531
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.4015780786
Short name T221
Test name
Test status
Simulation time 9984372530 ps
CPU time 47.86 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:50 PM PDT 24
Peak memory 256032 kb
Host smart-5bb6d976-bc63-44a5-ac7e-479e63dc85bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015780786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4015780786
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1847817159
Short name T710
Test name
Test status
Simulation time 3664652020 ps
CPU time 19.98 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:27 PM PDT 24
Peak memory 224928 kb
Host smart-0600cd3e-ae01-4cd8-9ab3-f0aea5c30bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847817159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1847817159
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2537952622
Short name T292
Test name
Test status
Simulation time 29484958962 ps
CPU time 28.53 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:34 PM PDT 24
Peak memory 250336 kb
Host smart-78e5ad4c-4a00-4756-8ece-dfe64d445f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537952622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2537952622
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1364097513
Short name T240
Test name
Test status
Simulation time 54365358644 ps
CPU time 140.26 seconds
Started Aug 06 07:53:57 PM PDT 24
Finished Aug 06 07:56:18 PM PDT 24
Peak memory 256600 kb
Host smart-e31f27ed-f852-43b0-8d97-c12f7071bb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364097513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1364097513
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1946228297
Short name T992
Test name
Test status
Simulation time 289699852 ps
CPU time 4.75 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:53 PM PDT 24
Peak memory 224900 kb
Host smart-4985f9fe-40d1-4f3e-afa1-37b9fe930295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946228297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1946228297
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1466209440
Short name T454
Test name
Test status
Simulation time 9100378263 ps
CPU time 25.58 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 233248 kb
Host smart-9aa9ed45-79d7-4397-bf2b-b76774de6e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466209440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1466209440
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2401725128
Short name T695
Test name
Test status
Simulation time 3060479395 ps
CPU time 5.26 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:54 PM PDT 24
Peak memory 224968 kb
Host smart-ee7c1ac8-1771-40ab-a502-d8671d948fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401725128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2401725128
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2570834798
Short name T391
Test name
Test status
Simulation time 44480856 ps
CPU time 2.77 seconds
Started Aug 06 07:53:50 PM PDT 24
Finished Aug 06 07:53:53 PM PDT 24
Peak memory 233088 kb
Host smart-64f66f24-f914-4a2b-ad76-a50e32526f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570834798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2570834798
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1960070796
Short name T923
Test name
Test status
Simulation time 5804048611 ps
CPU time 17.65 seconds
Started Aug 06 07:54:00 PM PDT 24
Finished Aug 06 07:54:18 PM PDT 24
Peak memory 219476 kb
Host smart-99130d39-0e18-408b-9961-3f27f725acb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1960070796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1960070796
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2858960335
Short name T52
Test name
Test status
Simulation time 118500250265 ps
CPU time 604.75 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 08:04:07 PM PDT 24
Peak memory 273372 kb
Host smart-84181400-0a7c-4e2a-9c6f-af492bdfaa40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858960335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2858960335
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1640493747
Short name T306
Test name
Test status
Simulation time 2209915296 ps
CPU time 11.49 seconds
Started Aug 06 07:53:54 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 216728 kb
Host smart-a0a96c2a-64cd-4271-92b1-1fc2d4baea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640493747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1640493747
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1053865352
Short name T376
Test name
Test status
Simulation time 18822122870 ps
CPU time 9.6 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:58 PM PDT 24
Peak memory 216748 kb
Host smart-c234e252-e44d-4896-95bb-6a6cd389e6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053865352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1053865352
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.597335441
Short name T961
Test name
Test status
Simulation time 14280120 ps
CPU time 0.78 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:49 PM PDT 24
Peak memory 206300 kb
Host smart-51f90c05-0093-446e-92de-50ba70a60148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597335441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.597335441
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.567091600
Short name T616
Test name
Test status
Simulation time 54659996 ps
CPU time 0.85 seconds
Started Aug 06 07:53:48 PM PDT 24
Finished Aug 06 07:53:49 PM PDT 24
Peak memory 206348 kb
Host smart-aacc2d23-265e-47e3-a6e8-89104d270e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567091600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.567091600
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3903187452
Short name T119
Test name
Test status
Simulation time 5251336565 ps
CPU time 8.49 seconds
Started Aug 06 07:54:01 PM PDT 24
Finished Aug 06 07:54:09 PM PDT 24
Peak memory 233156 kb
Host smart-afb0bfe0-1f41-4ddd-9db3-6df8ab128044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903187452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3903187452
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.748789159
Short name T67
Test name
Test status
Simulation time 22749194 ps
CPU time 0.72 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:03 PM PDT 24
Peak memory 205848 kb
Host smart-e332f50a-eca5-45a9-a6eb-cd027c0b22d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748789159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.748789159
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3681902797
Short name T410
Test name
Test status
Simulation time 490261777 ps
CPU time 3.67 seconds
Started Aug 06 07:54:00 PM PDT 24
Finished Aug 06 07:54:04 PM PDT 24
Peak memory 233020 kb
Host smart-354944e4-612d-4e50-bf3a-f2a2a57502a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681902797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3681902797
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2501235913
Short name T635
Test name
Test status
Simulation time 21353419 ps
CPU time 0.85 seconds
Started Aug 06 07:54:01 PM PDT 24
Finished Aug 06 07:54:02 PM PDT 24
Peak memory 206980 kb
Host smart-5c4f1873-dbea-4784-9b23-b70c2614c572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501235913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2501235913
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2622717554
Short name T614
Test name
Test status
Simulation time 33421071862 ps
CPU time 238.24 seconds
Started Aug 06 07:54:03 PM PDT 24
Finished Aug 06 07:58:02 PM PDT 24
Peak memory 248612 kb
Host smart-fadd0d6b-8be9-4689-9f58-f2edc449ad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622717554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2622717554
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.752066744
Short name T798
Test name
Test status
Simulation time 10691725161 ps
CPU time 64 seconds
Started Aug 06 07:54:01 PM PDT 24
Finished Aug 06 07:55:05 PM PDT 24
Peak memory 250584 kb
Host smart-658df152-b669-4083-8aad-56ff8aab6292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752066744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.752066744
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1953537400
Short name T712
Test name
Test status
Simulation time 33712504918 ps
CPU time 304.03 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:59:08 PM PDT 24
Peak memory 249612 kb
Host smart-a5ab3256-2679-4f1c-8e98-e27f409e9bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953537400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1953537400
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4035618448
Short name T139
Test name
Test status
Simulation time 8311184113 ps
CPU time 57.36 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:59 PM PDT 24
Peak memory 253832 kb
Host smart-4ed36dc2-f934-446e-b349-50637f62ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035618448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4035618448
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3377619047
Short name T432
Test name
Test status
Simulation time 58107760 ps
CPU time 0.8 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:03 PM PDT 24
Peak memory 216132 kb
Host smart-dbd7889e-23dd-494b-919b-3e2c8d9e6249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377619047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3377619047
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2437193260
Short name T952
Test name
Test status
Simulation time 348053524 ps
CPU time 6.63 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 233160 kb
Host smart-64a3f922-c9ac-4c3f-bce3-629ff2ac610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437193260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2437193260
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.161999418
Short name T251
Test name
Test status
Simulation time 9158131494 ps
CPU time 85.31 seconds
Started Aug 06 07:53:59 PM PDT 24
Finished Aug 06 07:55:25 PM PDT 24
Peak memory 241064 kb
Host smart-16da68f6-d4fa-411b-98e1-52e4b3aab551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161999418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.161999418
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3573021128
Short name T687
Test name
Test status
Simulation time 2914280648 ps
CPU time 9.81 seconds
Started Aug 06 07:54:00 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 233132 kb
Host smart-66b73d43-8558-4f47-8505-1bab36e0d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573021128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3573021128
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3546075314
Short name T630
Test name
Test status
Simulation time 56304325 ps
CPU time 2.05 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 223424 kb
Host smart-1def526e-e393-4ac2-a682-b1877bfa64c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546075314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3546075314
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1193807228
Short name T415
Test name
Test status
Simulation time 386394959 ps
CPU time 3.54 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 223160 kb
Host smart-6fa078d4-0084-45ad-9221-9defe72d21b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1193807228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1193807228
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2826891809
Short name T283
Test name
Test status
Simulation time 5735962526 ps
CPU time 158.41 seconds
Started Aug 06 07:54:01 PM PDT 24
Finished Aug 06 07:56:40 PM PDT 24
Peak memory 271200 kb
Host smart-334f4ef8-1c01-4a89-b7ee-0ea1003f8cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826891809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2826891809
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3681207227
Short name T450
Test name
Test status
Simulation time 4052959933 ps
CPU time 23.29 seconds
Started Aug 06 07:54:03 PM PDT 24
Finished Aug 06 07:54:27 PM PDT 24
Peak memory 220720 kb
Host smart-3e653511-8567-4e07-a743-5a9ed74f0b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681207227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3681207227
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.487554596
Short name T379
Test name
Test status
Simulation time 3077948902 ps
CPU time 6.74 seconds
Started Aug 06 07:54:01 PM PDT 24
Finished Aug 06 07:54:08 PM PDT 24
Peak memory 216744 kb
Host smart-596bd5fb-c31b-466c-a46c-83785e7ff91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487554596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.487554596
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2161322627
Short name T333
Test name
Test status
Simulation time 13466776 ps
CPU time 0.7 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:54:05 PM PDT 24
Peak memory 206008 kb
Host smart-6d9539b4-af82-435d-a4e0-224bf5dfd982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161322627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2161322627
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3644587582
Short name T748
Test name
Test status
Simulation time 86380620 ps
CPU time 0.79 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 206420 kb
Host smart-16556655-8590-4fb1-9366-3ed60ce17a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644587582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3644587582
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4170590233
Short name T957
Test name
Test status
Simulation time 18681442296 ps
CPU time 22.45 seconds
Started Aug 06 07:54:00 PM PDT 24
Finished Aug 06 07:54:23 PM PDT 24
Peak memory 225048 kb
Host smart-9559c1c1-0446-4d75-b316-f8940c3e977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170590233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4170590233
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2431317700
Short name T577
Test name
Test status
Simulation time 14296348 ps
CPU time 0.74 seconds
Started Aug 06 07:54:03 PM PDT 24
Finished Aug 06 07:54:04 PM PDT 24
Peak memory 205316 kb
Host smart-aef79f94-6baf-4662-a97c-88b5faf4e966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431317700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2431317700
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1658936538
Short name T179
Test name
Test status
Simulation time 2082965823 ps
CPU time 6.91 seconds
Started Aug 06 07:54:06 PM PDT 24
Finished Aug 06 07:54:13 PM PDT 24
Peak memory 233092 kb
Host smart-9ae92b47-5007-4b6a-9649-096221cfbcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658936538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1658936538
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2092634824
Short name T345
Test name
Test status
Simulation time 25087801 ps
CPU time 0.78 seconds
Started Aug 06 07:54:03 PM PDT 24
Finished Aug 06 07:54:04 PM PDT 24
Peak memory 207020 kb
Host smart-d879083e-2515-41ec-90b8-25409f771636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092634824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2092634824
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1847169067
Short name T808
Test name
Test status
Simulation time 7631187222 ps
CPU time 52.36 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:57 PM PDT 24
Peak memory 224976 kb
Host smart-c33ce6ba-7e0d-454f-9d54-68ca64769244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847169067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1847169067
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2656066737
Short name T766
Test name
Test status
Simulation time 7034779270 ps
CPU time 98.41 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:55:46 PM PDT 24
Peak memory 274156 kb
Host smart-a1e0f4c3-5c68-417a-9178-153baa93a84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656066737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2656066737
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3015666814
Short name T855
Test name
Test status
Simulation time 21047307800 ps
CPU time 212.67 seconds
Started Aug 06 07:53:59 PM PDT 24
Finished Aug 06 07:57:32 PM PDT 24
Peak memory 250536 kb
Host smart-e2a6d53a-c2fc-498f-9a75-66fae55361e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015666814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3015666814
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1141182311
Short name T346
Test name
Test status
Simulation time 44199850 ps
CPU time 3.09 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:05 PM PDT 24
Peak memory 233136 kb
Host smart-18f5b5a1-01ad-4cf6-92de-87b855d52c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141182311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1141182311
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3317420622
Short name T803
Test name
Test status
Simulation time 3415020652 ps
CPU time 16.04 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:18 PM PDT 24
Peak memory 239248 kb
Host smart-208b3464-164d-4ee6-bb5c-5f69b041a58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317420622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3317420622
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.72107391
Short name T528
Test name
Test status
Simulation time 2667153314 ps
CPU time 8.78 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:11 PM PDT 24
Peak memory 233172 kb
Host smart-9dea7c72-45a5-4458-b158-150e62a0692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72107391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.72107391
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3943692825
Short name T357
Test name
Test status
Simulation time 4564743318 ps
CPU time 52.55 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:59 PM PDT 24
Peak memory 233160 kb
Host smart-8871ded2-9b67-4b16-abb5-7eaf37614836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943692825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3943692825
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1402231100
Short name T270
Test name
Test status
Simulation time 340683609 ps
CPU time 3.12 seconds
Started Aug 06 07:54:06 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 224908 kb
Host smart-e22e5d54-c2aa-4918-8ab7-ff65206c76d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402231100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1402231100
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1321750487
Short name T692
Test name
Test status
Simulation time 343733364 ps
CPU time 2.33 seconds
Started Aug 06 07:54:03 PM PDT 24
Finished Aug 06 07:54:05 PM PDT 24
Peak memory 223460 kb
Host smart-a7437219-87e1-4070-abde-c7ad4435d8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321750487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1321750487
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.477354719
Short name T38
Test name
Test status
Simulation time 4046692327 ps
CPU time 9.97 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:12 PM PDT 24
Peak memory 220712 kb
Host smart-50df6ed3-1b48-489c-86af-427d187ef8c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=477354719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.477354719
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1719739477
Short name T154
Test name
Test status
Simulation time 11904329127 ps
CPU time 129.31 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:56:11 PM PDT 24
Peak memory 254128 kb
Host smart-a9027988-2828-43a2-bca8-5eaa40ed29cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719739477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1719739477
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1339139105
Short name T996
Test name
Test status
Simulation time 5112795585 ps
CPU time 17.76 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:24 PM PDT 24
Peak memory 218008 kb
Host smart-7a0bc1bb-a8e0-44d6-910e-959f2e7c3a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339139105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1339139105
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.630992892
Short name T771
Test name
Test status
Simulation time 6412651507 ps
CPU time 5.41 seconds
Started Aug 06 07:54:03 PM PDT 24
Finished Aug 06 07:54:09 PM PDT 24
Peak memory 216672 kb
Host smart-355490b8-cb1d-440a-aad8-fb3e20746776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630992892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.630992892
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3493591198
Short name T649
Test name
Test status
Simulation time 65616711 ps
CPU time 1.62 seconds
Started Aug 06 07:54:01 PM PDT 24
Finished Aug 06 07:54:03 PM PDT 24
Peak memory 216536 kb
Host smart-a065d080-8d8a-42a5-b3e0-399ea6b87246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493591198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3493591198
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1262053225
Short name T906
Test name
Test status
Simulation time 170000902 ps
CPU time 0.96 seconds
Started Aug 06 07:54:01 PM PDT 24
Finished Aug 06 07:54:02 PM PDT 24
Peak memory 206388 kb
Host smart-26b6c43f-41c6-4825-97a6-7b730a9fb0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262053225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1262053225
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2397055370
Short name T819
Test name
Test status
Simulation time 1995536622 ps
CPU time 7.43 seconds
Started Aug 06 07:54:06 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 233140 kb
Host smart-bfe451e7-ec5c-431c-8f5e-88f83209c819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397055370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2397055370
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.645855761
Short name T782
Test name
Test status
Simulation time 82487755 ps
CPU time 0.7 seconds
Started Aug 06 07:54:09 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 205256 kb
Host smart-e78f4c8d-3689-4c28-acf2-0e0124a5a5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645855761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.645855761
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1890780125
Short name T544
Test name
Test status
Simulation time 581274769 ps
CPU time 3.62 seconds
Started Aug 06 07:54:06 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 233096 kb
Host smart-2493480a-12f2-4f73-ac17-c1a7c8e3b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890780125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1890780125
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3917044559
Short name T606
Test name
Test status
Simulation time 73738020 ps
CPU time 0.79 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 206832 kb
Host smart-632976be-aa62-41d2-a795-654a2550abcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917044559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3917044559
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2943304812
Short name T720
Test name
Test status
Simulation time 14502620974 ps
CPU time 80.31 seconds
Started Aug 06 07:54:08 PM PDT 24
Finished Aug 06 07:55:28 PM PDT 24
Peak memory 256864 kb
Host smart-fb2cd69e-f168-4baf-a745-a1b604e4ceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943304812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2943304812
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.179339330
Short name T890
Test name
Test status
Simulation time 81182424683 ps
CPU time 221.84 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:57:49 PM PDT 24
Peak memory 249660 kb
Host smart-bbc63466-4ff2-4406-a4a2-ffaefc5cc07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179339330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.179339330
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2784910452
Short name T284
Test name
Test status
Simulation time 44159217389 ps
CPU time 464.12 seconds
Started Aug 06 07:54:10 PM PDT 24
Finished Aug 06 08:01:54 PM PDT 24
Peak memory 265540 kb
Host smart-de779d21-17c5-44ab-8658-766f90564f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784910452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2784910452
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3378100508
Short name T547
Test name
Test status
Simulation time 188891928 ps
CPU time 4.07 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:09 PM PDT 24
Peak memory 233324 kb
Host smart-7be0ce02-f426-4c97-9564-925cc3434ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378100508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3378100508
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1790755827
Short name T938
Test name
Test status
Simulation time 1809754915 ps
CPU time 26.49 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:31 PM PDT 24
Peak memory 249456 kb
Host smart-05eac0a1-d364-44d0-a0ea-efaab8b09ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790755827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1790755827
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1371533379
Short name T234
Test name
Test status
Simulation time 1650187513 ps
CPU time 16.02 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:54:20 PM PDT 24
Peak memory 224904 kb
Host smart-76337200-fb12-4ace-b8cf-ae80c13cc9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371533379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1371533379
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1811070701
Short name T750
Test name
Test status
Simulation time 400074475 ps
CPU time 3.57 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:08 PM PDT 24
Peak memory 224804 kb
Host smart-c932c3bd-6365-4636-8b64-6f294a07b13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811070701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1811070701
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2889328668
Short name T262
Test name
Test status
Simulation time 357530294 ps
CPU time 2.49 seconds
Started Aug 06 07:54:01 PM PDT 24
Finished Aug 06 07:54:04 PM PDT 24
Peak memory 225028 kb
Host smart-2b6ed062-b295-4f07-ad27-6d616d64e291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889328668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2889328668
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.891299839
Short name T227
Test name
Test status
Simulation time 521420751 ps
CPU time 4.91 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:07 PM PDT 24
Peak memory 232964 kb
Host smart-d234c08c-544a-4d90-b4ed-7dcf3f3730a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891299839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.891299839
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.612781177
Short name T554
Test name
Test status
Simulation time 1112251200 ps
CPU time 12.29 seconds
Started Aug 06 07:54:08 PM PDT 24
Finished Aug 06 07:54:20 PM PDT 24
Peak memory 219192 kb
Host smart-6633bb6e-d635-4e78-a25c-b022adf463fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=612781177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.612781177
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.380573206
Short name T287
Test name
Test status
Simulation time 282430186058 ps
CPU time 373.81 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 08:00:16 PM PDT 24
Peak memory 265352 kb
Host smart-a55f43b5-4c6c-4b86-aacf-8d2be0eda451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380573206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.380573206
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3856259276
Short name T593
Test name
Test status
Simulation time 6424278867 ps
CPU time 14.58 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:54:19 PM PDT 24
Peak memory 216796 kb
Host smart-cf7fb095-48a3-4bf1-a61a-0e0024da990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856259276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3856259276
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3282213010
Short name T609
Test name
Test status
Simulation time 1228881204 ps
CPU time 6.88 seconds
Started Aug 06 07:54:10 PM PDT 24
Finished Aug 06 07:54:17 PM PDT 24
Peak memory 216628 kb
Host smart-40da5990-b0f8-472c-ba74-f90b53eb10f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282213010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3282213010
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.508671663
Short name T850
Test name
Test status
Simulation time 64086833 ps
CPU time 1.53 seconds
Started Aug 06 07:54:03 PM PDT 24
Finished Aug 06 07:54:04 PM PDT 24
Peak memory 216692 kb
Host smart-737777ec-76a1-4e21-b25b-5043da034866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508671663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.508671663
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2314082993
Short name T901
Test name
Test status
Simulation time 51891127 ps
CPU time 0.72 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:08 PM PDT 24
Peak memory 206304 kb
Host smart-fb9b1978-85a6-4bc4-9fe2-1f760264fc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314082993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2314082993
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.518523556
Short name T809
Test name
Test status
Simulation time 560568087 ps
CPU time 4.65 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:07 PM PDT 24
Peak memory 224864 kb
Host smart-abb3b12c-4ace-44aa-aebd-6c1457b35a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518523556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.518523556
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.695388667
Short name T661
Test name
Test status
Simulation time 13377534 ps
CPU time 0.72 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 205236 kb
Host smart-c73c890c-7f9c-4d5f-a408-5d6b6332c218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695388667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.695388667
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2679093634
Short name T481
Test name
Test status
Simulation time 386997101 ps
CPU time 2.92 seconds
Started Aug 06 07:54:02 PM PDT 24
Finished Aug 06 07:54:05 PM PDT 24
Peak memory 224860 kb
Host smart-c16ce623-e8d2-4391-9c96-84e206e1e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679093634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2679093634
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2823240448
Short name T663
Test name
Test status
Simulation time 35011136 ps
CPU time 0.73 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 205932 kb
Host smart-0bb0898b-c501-42df-9ae9-47217f4e60ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823240448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2823240448
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.620638462
Short name T939
Test name
Test status
Simulation time 1278738816 ps
CPU time 9.93 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:15 PM PDT 24
Peak memory 241344 kb
Host smart-812e8ef1-c09a-4fa0-a541-b2ef4b3dc5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620638462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.620638462
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.983137655
Short name T672
Test name
Test status
Simulation time 4494613818 ps
CPU time 35.56 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:41 PM PDT 24
Peak memory 225028 kb
Host smart-e25454c6-740d-473b-aa84-bd204c88d5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983137655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.983137655
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3422066875
Short name T116
Test name
Test status
Simulation time 14919455658 ps
CPU time 108.15 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:55:55 PM PDT 24
Peak memory 249656 kb
Host smart-d030474b-1624-4d35-b7d3-db6417023897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422066875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3422066875
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2464964045
Short name T910
Test name
Test status
Simulation time 10997440932 ps
CPU time 9.25 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 225020 kb
Host smart-f2e859d3-478a-489f-9f54-18cc42186bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464964045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2464964045
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3967428005
Short name T823
Test name
Test status
Simulation time 53908485984 ps
CPU time 92.6 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 07:55:38 PM PDT 24
Peak memory 251224 kb
Host smart-c057e9a9-eaef-40bb-a503-9a6994a193cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967428005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3967428005
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.496469247
Short name T272
Test name
Test status
Simulation time 405740440 ps
CPU time 5.98 seconds
Started Aug 06 07:54:06 PM PDT 24
Finished Aug 06 07:54:12 PM PDT 24
Peak memory 224960 kb
Host smart-d080c348-01bb-44fe-a3c6-21da8db4519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496469247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.496469247
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1658229312
Short name T842
Test name
Test status
Simulation time 147941491237 ps
CPU time 85.96 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:55:30 PM PDT 24
Peak memory 233220 kb
Host smart-e5ea8674-724a-47e9-a693-cea68a0b1a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658229312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1658229312
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1332370109
Short name T565
Test name
Test status
Simulation time 434052258 ps
CPU time 2.41 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:54:07 PM PDT 24
Peak memory 224920 kb
Host smart-f416b401-b26f-4af7-9374-fb3fa8f3dbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332370109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1332370109
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3000915105
Short name T394
Test name
Test status
Simulation time 604895974 ps
CPU time 5.63 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:54:09 PM PDT 24
Peak memory 224872 kb
Host smart-903988db-177a-44aa-bbbf-e0f25b32fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000915105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3000915105
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3354128824
Short name T377
Test name
Test status
Simulation time 6734429976 ps
CPU time 17.44 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:25 PM PDT 24
Peak memory 222720 kb
Host smart-bbc463dd-b4a1-40ab-8d81-8c54ce8d05ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3354128824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3354128824
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1283394982
Short name T127
Test name
Test status
Simulation time 382547965537 ps
CPU time 688.35 seconds
Started Aug 06 07:54:05 PM PDT 24
Finished Aug 06 08:05:33 PM PDT 24
Peak memory 283768 kb
Host smart-4ef8f935-7a4d-429e-ae0b-e1a23e2a4102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283394982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1283394982
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4153082278
Short name T122
Test name
Test status
Simulation time 3312302422 ps
CPU time 16.46 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:24 PM PDT 24
Peak memory 219172 kb
Host smart-c55a47f9-6f85-4ed9-bfbc-982118192b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153082278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4153082278
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1877602940
Short name T509
Test name
Test status
Simulation time 32106899628 ps
CPU time 5.37 seconds
Started Aug 06 07:54:06 PM PDT 24
Finished Aug 06 07:54:12 PM PDT 24
Peak memory 216772 kb
Host smart-3efb918d-57d2-4696-8315-e8c749e0b4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877602940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1877602940
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3500826472
Short name T478
Test name
Test status
Simulation time 277803045 ps
CPU time 1.41 seconds
Started Aug 06 07:54:09 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 216584 kb
Host smart-934f3bdd-8ad7-450b-981a-7b2830001ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500826472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3500826472
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2517572170
Short name T806
Test name
Test status
Simulation time 46774838 ps
CPU time 0.83 seconds
Started Aug 06 07:54:10 PM PDT 24
Finished Aug 06 07:54:11 PM PDT 24
Peak memory 206296 kb
Host smart-b2bb7118-9fdd-4c1b-9805-2bf470a694a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517572170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2517572170
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1742404738
Short name T875
Test name
Test status
Simulation time 382105749 ps
CPU time 3.1 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 224904 kb
Host smart-8abffb7d-d2cb-48bc-be56-437edae45412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742404738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1742404738
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.672834217
Short name T963
Test name
Test status
Simulation time 77005595 ps
CPU time 0.72 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 205232 kb
Host smart-d5903459-654e-48c7-974b-173c87ef0793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672834217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.672834217
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2118723310
Short name T941
Test name
Test status
Simulation time 5716607399 ps
CPU time 23.74 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:31 PM PDT 24
Peak memory 233132 kb
Host smart-08e59c5b-853c-4638-bc23-48e9571dc588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118723310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2118723310
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2097650660
Short name T683
Test name
Test status
Simulation time 60688182 ps
CPU time 0.76 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:08 PM PDT 24
Peak memory 205964 kb
Host smart-8745cd42-288c-4888-b0c1-8d77e109e190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097650660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2097650660
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3597240449
Short name T570
Test name
Test status
Simulation time 4618143074 ps
CPU time 20.32 seconds
Started Aug 06 07:54:03 PM PDT 24
Finished Aug 06 07:54:23 PM PDT 24
Peak memory 224940 kb
Host smart-e2d1b4ac-3846-4e70-9436-e36a95af8979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597240449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3597240449
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2536261759
Short name T995
Test name
Test status
Simulation time 17766485297 ps
CPU time 175.57 seconds
Started Aug 06 07:54:13 PM PDT 24
Finished Aug 06 07:57:08 PM PDT 24
Peak memory 249616 kb
Host smart-09c35072-1be7-45dd-b7af-495c88318942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536261759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2536261759
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4148764363
Short name T277
Test name
Test status
Simulation time 15438353703 ps
CPU time 106.53 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:56:00 PM PDT 24
Peak memory 272520 kb
Host smart-220944f0-113c-46e0-a975-03776589ad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148764363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4148764363
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4088187834
Short name T296
Test name
Test status
Simulation time 685878181 ps
CPU time 6.56 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 224892 kb
Host smart-600f1a59-050b-49d6-af1e-407ff37cb6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088187834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4088187834
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1362840488
Short name T926
Test name
Test status
Simulation time 4507826921 ps
CPU time 56.62 seconds
Started Aug 06 07:54:08 PM PDT 24
Finished Aug 06 07:55:05 PM PDT 24
Peak memory 249480 kb
Host smart-f804f7c0-4571-4f31-bb2a-f21e6177a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362840488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1362840488
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.381813300
Short name T184
Test name
Test status
Simulation time 408222486 ps
CPU time 7.16 seconds
Started Aug 06 07:54:09 PM PDT 24
Finished Aug 06 07:54:16 PM PDT 24
Peak memory 233152 kb
Host smart-8aaae410-3a32-4a4e-8352-47a7de4a14fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381813300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.381813300
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1867313142
Short name T673
Test name
Test status
Simulation time 46092582533 ps
CPU time 61.7 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:55:09 PM PDT 24
Peak memory 250728 kb
Host smart-8c3ca3e0-4891-478b-9ec1-d1c9c6db7a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867313142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1867313142
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3274529155
Short name T549
Test name
Test status
Simulation time 2039330284 ps
CPU time 5.63 seconds
Started Aug 06 07:54:08 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 238468 kb
Host smart-a9fe3022-1bab-42fc-8deb-f82c5ebbf46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274529155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3274529155
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2141751970
Short name T522
Test name
Test status
Simulation time 9455549174 ps
CPU time 7.93 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:15 PM PDT 24
Peak memory 233216 kb
Host smart-b9633404-a84b-4ce6-94df-acd92306d667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141751970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2141751970
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4067258396
Short name T566
Test name
Test status
Simulation time 371790778 ps
CPU time 7.01 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 223636 kb
Host smart-262ac672-cc5d-4d91-a3ad-1a58d41bd24c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4067258396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4067258396
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1457437191
Short name T458
Test name
Test status
Simulation time 90326482 ps
CPU time 0.96 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:54:17 PM PDT 24
Peak memory 207896 kb
Host smart-19eccf70-a3c5-428a-a8e9-4780aca90d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457437191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1457437191
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4240398337
Short name T612
Test name
Test status
Simulation time 9984888068 ps
CPU time 13.74 seconds
Started Aug 06 07:54:04 PM PDT 24
Finished Aug 06 07:54:18 PM PDT 24
Peak memory 216684 kb
Host smart-533158ee-f612-4ebe-800f-b80d28e06ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240398337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4240398337
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1820616241
Short name T456
Test name
Test status
Simulation time 5232709412 ps
CPU time 8.3 seconds
Started Aug 06 07:54:06 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 216712 kb
Host smart-674223f7-0709-4b79-9690-022be8628509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820616241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1820616241
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2934182744
Short name T815
Test name
Test status
Simulation time 30004063 ps
CPU time 1.02 seconds
Started Aug 06 07:54:09 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 207944 kb
Host smart-e655808b-a6e6-4e1b-98df-a3e23701a49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934182744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2934182744
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1744716730
Short name T858
Test name
Test status
Simulation time 183260903 ps
CPU time 0.86 seconds
Started Aug 06 07:54:07 PM PDT 24
Finished Aug 06 07:54:08 PM PDT 24
Peak memory 206828 kb
Host smart-a12e2e7a-1005-48f5-8317-a4f170bfa0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744716730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1744716730
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2586860638
Short name T671
Test name
Test status
Simulation time 14026655797 ps
CPU time 23.51 seconds
Started Aug 06 07:54:08 PM PDT 24
Finished Aug 06 07:54:32 PM PDT 24
Peak memory 233248 kb
Host smart-4781f1cf-d715-4039-916f-03fb1305f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586860638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2586860638
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1112363556
Short name T643
Test name
Test status
Simulation time 13736819 ps
CPU time 0.73 seconds
Started Aug 06 07:54:13 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 205856 kb
Host smart-932ec55c-2821-4b20-98b2-a7fbd4f6c8fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112363556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1112363556
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2869341954
Short name T160
Test name
Test status
Simulation time 458283287 ps
CPU time 3.55 seconds
Started Aug 06 07:54:15 PM PDT 24
Finished Aug 06 07:54:18 PM PDT 24
Peak memory 233056 kb
Host smart-83c867e7-72b4-48c5-af2a-0bfce45cffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869341954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2869341954
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3010809518
Short name T142
Test name
Test status
Simulation time 68407957 ps
CPU time 0.82 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:18 PM PDT 24
Peak memory 207024 kb
Host smart-a844a241-cb82-471f-b8cd-667c9e0548a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010809518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3010809518
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3093010284
Short name T177
Test name
Test status
Simulation time 68185192150 ps
CPU time 132.86 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:56:27 PM PDT 24
Peak memory 253004 kb
Host smart-3756ca5a-bddc-4cc7-9ec6-ec983ded66f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093010284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3093010284
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2092064535
Short name T536
Test name
Test status
Simulation time 5106328402 ps
CPU time 55.6 seconds
Started Aug 06 07:54:13 PM PDT 24
Finished Aug 06 07:55:09 PM PDT 24
Peak memory 249712 kb
Host smart-b346b01e-d3b6-4b7f-b0bc-aa004b40399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092064535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2092064535
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.955061394
Short name T620
Test name
Test status
Simulation time 3083259248 ps
CPU time 12.54 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:27 PM PDT 24
Peak memory 218196 kb
Host smart-b7c69ac6-37cf-49f0-9a7b-ab015225a5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955061394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.955061394
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3172684694
Short name T902
Test name
Test status
Simulation time 3915873293 ps
CPU time 10.9 seconds
Started Aug 06 07:54:12 PM PDT 24
Finished Aug 06 07:54:23 PM PDT 24
Peak memory 249480 kb
Host smart-2dd5bc45-0423-4965-bc4a-d93e0305cf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172684694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3172684694
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3456976064
Short name T144
Test name
Test status
Simulation time 1715303987 ps
CPU time 31.7 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:46 PM PDT 24
Peak memory 250380 kb
Host smart-dcffd728-bece-49c3-a271-13d351331d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456976064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3456976064
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.204529599
Short name T214
Test name
Test status
Simulation time 896836202 ps
CPU time 9.07 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:27 PM PDT 24
Peak memory 233000 kb
Host smart-687dd321-ed63-4a92-b297-32c2ec6344c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204529599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.204529599
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.792223342
Short name T847
Test name
Test status
Simulation time 10938659883 ps
CPU time 102.47 seconds
Started Aug 06 07:54:11 PM PDT 24
Finished Aug 06 07:55:54 PM PDT 24
Peak memory 233160 kb
Host smart-338cf273-df20-40b5-a4b7-ad6c5b619569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792223342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.792223342
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2931600735
Short name T168
Test name
Test status
Simulation time 31466776202 ps
CPU time 21.69 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:36 PM PDT 24
Peak memory 233104 kb
Host smart-fe433d68-63bb-41bf-a1dd-4587928d5a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931600735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2931600735
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.474530554
Short name T472
Test name
Test status
Simulation time 1706115852 ps
CPU time 4.08 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:18 PM PDT 24
Peak memory 224816 kb
Host smart-7cddbb3c-13b8-4dc0-a10e-261c83dc0a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474530554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.474530554
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1561927050
Short name T457
Test name
Test status
Simulation time 867099995 ps
CPU time 8.63 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:23 PM PDT 24
Peak memory 223024 kb
Host smart-0952eee0-c283-4dfa-bc7c-b951f1f48fe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1561927050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1561927050
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4169996772
Short name T148
Test name
Test status
Simulation time 47192137039 ps
CPU time 121.4 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:56:16 PM PDT 24
Peak memory 241480 kb
Host smart-24656e12-48f4-4dd1-bb8a-7918610ecd46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169996772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4169996772
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1389080486
Short name T948
Test name
Test status
Simulation time 2210941847 ps
CPU time 8.67 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:26 PM PDT 24
Peak memory 216692 kb
Host smart-b09a6517-3256-4b0b-b811-878a3088fcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389080486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1389080486
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2199366236
Short name T762
Test name
Test status
Simulation time 5029411322 ps
CPU time 9.61 seconds
Started Aug 06 07:54:15 PM PDT 24
Finished Aug 06 07:54:25 PM PDT 24
Peak memory 216696 kb
Host smart-52556297-ecd5-452c-bf7f-8c0fe51197ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199366236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2199366236
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.747169915
Short name T899
Test name
Test status
Simulation time 33627130 ps
CPU time 1.36 seconds
Started Aug 06 07:54:15 PM PDT 24
Finished Aug 06 07:54:16 PM PDT 24
Peak memory 216660 kb
Host smart-795ad4ce-302a-44ba-95c5-fdcd236276a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747169915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.747169915
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4003101977
Short name T891
Test name
Test status
Simulation time 55082881 ps
CPU time 0.82 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:15 PM PDT 24
Peak memory 206396 kb
Host smart-3044260b-a884-40a8-a3f5-1d81b6588127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003101977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4003101977
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3329168123
Short name T588
Test name
Test status
Simulation time 18190974754 ps
CPU time 14.38 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:32 PM PDT 24
Peak memory 224828 kb
Host smart-5a875f61-bd08-46ea-8c53-1beee21d9444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329168123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3329168123
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2375647651
Short name T353
Test name
Test status
Simulation time 20504987 ps
CPU time 0.74 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:15 PM PDT 24
Peak memory 205212 kb
Host smart-5761caff-8610-4503-ad98-33d6be011125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375647651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2375647651
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2544143578
Short name T746
Test name
Test status
Simulation time 152988278 ps
CPU time 2.32 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:16 PM PDT 24
Peak memory 233148 kb
Host smart-71d32e93-00af-4071-857c-ec7a33f56098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544143578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2544143578
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.567499388
Short name T886
Test name
Test status
Simulation time 26639874 ps
CPU time 0.76 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:54:17 PM PDT 24
Peak memory 205956 kb
Host smart-10f92b0c-0700-44a2-81c6-7c78064f1495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567499388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.567499388
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3892364002
Short name T382
Test name
Test status
Simulation time 30747656312 ps
CPU time 19.28 seconds
Started Aug 06 07:54:22 PM PDT 24
Finished Aug 06 07:54:42 PM PDT 24
Peak memory 237068 kb
Host smart-1316326f-eeec-4e57-abe6-ccae8069eea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892364002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3892364002
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1495205185
Short name T681
Test name
Test status
Simulation time 2057403414 ps
CPU time 26.85 seconds
Started Aug 06 07:54:13 PM PDT 24
Finished Aug 06 07:54:40 PM PDT 24
Peak memory 240672 kb
Host smart-6049ffa4-0335-4aef-befe-0bb20307a4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495205185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1495205185
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1764689753
Short name T787
Test name
Test status
Simulation time 26351421785 ps
CPU time 46.25 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:55:04 PM PDT 24
Peak memory 249936 kb
Host smart-692b76a6-a1fd-46fd-b9fb-3a573bcfa192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764689753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1764689753
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1626177950
Short name T473
Test name
Test status
Simulation time 1576567816 ps
CPU time 5.79 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:23 PM PDT 24
Peak memory 237756 kb
Host smart-74b5e9aa-c169-4c56-9241-6a18628989fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626177950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1626177950
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2422604387
Short name T624
Test name
Test status
Simulation time 68003406406 ps
CPU time 130.68 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:56:27 PM PDT 24
Peak memory 249168 kb
Host smart-73150797-bdf0-457f-8a52-c98087f5701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422604387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2422604387
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1729338719
Short name T451
Test name
Test status
Simulation time 995316588 ps
CPU time 4.09 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:21 PM PDT 24
Peak memory 224944 kb
Host smart-7b32f980-1f3c-4c9c-a2d3-a4f2fa5ca6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729338719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1729338719
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.923492932
Short name T269
Test name
Test status
Simulation time 28496962603 ps
CPU time 140.13 seconds
Started Aug 06 07:54:26 PM PDT 24
Finished Aug 06 07:56:46 PM PDT 24
Peak memory 238116 kb
Host smart-45457b24-08f4-419e-8659-c5bb9508feb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923492932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.923492932
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1786090142
Short name T416
Test name
Test status
Simulation time 1934582630 ps
CPU time 4.13 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:54:20 PM PDT 24
Peak memory 224948 kb
Host smart-d16ee351-b8c4-40a8-b140-949f7a8f95a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786090142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1786090142
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2911878508
Short name T418
Test name
Test status
Simulation time 1204738432 ps
CPU time 6.62 seconds
Started Aug 06 07:54:12 PM PDT 24
Finished Aug 06 07:54:19 PM PDT 24
Peak memory 224932 kb
Host smart-6bcf6727-9245-485b-a920-0c5116a200e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911878508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2911878508
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1859737843
Short name T959
Test name
Test status
Simulation time 3448884771 ps
CPU time 8.7 seconds
Started Aug 06 07:54:21 PM PDT 24
Finished Aug 06 07:54:30 PM PDT 24
Peak memory 222660 kb
Host smart-f60e7cd2-3136-4c54-8c19-2199240b31fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1859737843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1859737843
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2428759623
Short name T129
Test name
Test status
Simulation time 21898068275 ps
CPU time 153.37 seconds
Started Aug 06 07:54:12 PM PDT 24
Finished Aug 06 07:56:46 PM PDT 24
Peak memory 257780 kb
Host smart-058c2138-1837-4ebb-ac72-8fffc7f49b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428759623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2428759623
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1945799744
Short name T859
Test name
Test status
Simulation time 1755954992 ps
CPU time 7.86 seconds
Started Aug 06 07:54:25 PM PDT 24
Finished Aug 06 07:54:33 PM PDT 24
Peak memory 219188 kb
Host smart-47f9918d-ff19-4d87-8df9-830033f2da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945799744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1945799744
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2568677264
Short name T437
Test name
Test status
Simulation time 766982019 ps
CPU time 2.01 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:54:26 PM PDT 24
Peak memory 208260 kb
Host smart-43a30425-dd83-40e7-845e-f1976d38b80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568677264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2568677264
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2846765759
Short name T646
Test name
Test status
Simulation time 160331200 ps
CPU time 1.43 seconds
Started Aug 06 07:54:14 PM PDT 24
Finished Aug 06 07:54:16 PM PDT 24
Peak memory 216632 kb
Host smart-be2738e6-b2ee-4637-aec2-70a30d8908e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846765759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2846765759
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.908277859
Short name T422
Test name
Test status
Simulation time 36219739 ps
CPU time 0.82 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:18 PM PDT 24
Peak memory 206268 kb
Host smart-0a5841fd-aef3-40d2-aeee-0327c3097801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908277859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.908277859
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.539809983
Short name T932
Test name
Test status
Simulation time 52475697 ps
CPU time 2.44 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:54:19 PM PDT 24
Peak memory 224936 kb
Host smart-7c7ec55c-e617-447f-a0ba-0120e5bd3b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539809983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.539809983
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.679404876
Short name T66
Test name
Test status
Simulation time 13387555 ps
CPU time 0.7 seconds
Started Aug 06 07:54:21 PM PDT 24
Finished Aug 06 07:54:21 PM PDT 24
Peak memory 206144 kb
Host smart-df7e5d6d-d610-4f64-bcfe-51b56338a55f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679404876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.679404876
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.756691936
Short name T724
Test name
Test status
Simulation time 1069230294 ps
CPU time 11.9 seconds
Started Aug 06 07:54:25 PM PDT 24
Finished Aug 06 07:54:37 PM PDT 24
Peak memory 233112 kb
Host smart-800c4b0d-8773-4828-9313-08aa0deb303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756691936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.756691936
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2171765679
Short name T861
Test name
Test status
Simulation time 30831874 ps
CPU time 0.8 seconds
Started Aug 06 07:54:13 PM PDT 24
Finished Aug 06 07:54:13 PM PDT 24
Peak memory 207308 kb
Host smart-37da43c2-f557-47f5-a984-5539e8256b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171765679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2171765679
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.226620806
Short name T187
Test name
Test status
Simulation time 19272416349 ps
CPU time 131.91 seconds
Started Aug 06 07:54:25 PM PDT 24
Finished Aug 06 07:56:37 PM PDT 24
Peak memory 249560 kb
Host smart-e7ae8c26-679e-443d-a08d-a0d9c3f970af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226620806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.226620806
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3797608530
Short name T745
Test name
Test status
Simulation time 26177447213 ps
CPU time 282.26 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:58:59 PM PDT 24
Peak memory 264668 kb
Host smart-f5da9e49-2cb0-4cf9-8176-bc50bf26a917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797608530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3797608530
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.830666045
Short name T986
Test name
Test status
Simulation time 121380683123 ps
CPU time 570.03 seconds
Started Aug 06 07:54:27 PM PDT 24
Finished Aug 06 08:03:57 PM PDT 24
Peak memory 254700 kb
Host smart-4ce4a49e-6986-4142-829a-b95e536a6bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830666045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.830666045
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3679516103
Short name T299
Test name
Test status
Simulation time 853121922 ps
CPU time 13.71 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:31 PM PDT 24
Peak memory 224948 kb
Host smart-f72c794c-29b6-4a13-8a33-ae1f9ec772da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679516103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3679516103
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2494737165
Short name T57
Test name
Test status
Simulation time 41443796059 ps
CPU time 141.09 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:56:44 PM PDT 24
Peak memory 249192 kb
Host smart-834b33be-c855-48ff-9fc1-fa4e47965ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494737165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2494737165
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1028331204
Short name T207
Test name
Test status
Simulation time 5573369433 ps
CPU time 14.83 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:32 PM PDT 24
Peak memory 233196 kb
Host smart-20f9830e-c783-4433-bc35-cd0a61ed3c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028331204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1028331204
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1673224310
Short name T893
Test name
Test status
Simulation time 8771771620 ps
CPU time 18.79 seconds
Started Aug 06 07:54:25 PM PDT 24
Finished Aug 06 07:54:44 PM PDT 24
Peak memory 250316 kb
Host smart-55096a9a-54fd-474a-9292-ffded608c9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673224310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1673224310
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3012896891
Short name T529
Test name
Test status
Simulation time 29695266 ps
CPU time 2.12 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:54:19 PM PDT 24
Peak memory 224884 kb
Host smart-2a4a9a14-1aa3-4b00-b00d-9e0cb779e5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012896891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3012896891
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2758753238
Short name T85
Test name
Test status
Simulation time 1356590196 ps
CPU time 5.54 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:54:22 PM PDT 24
Peak memory 224560 kb
Host smart-fc341cee-9cbe-44ff-886f-583084672875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758753238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2758753238
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2916678024
Short name T561
Test name
Test status
Simulation time 2105750660 ps
CPU time 7.63 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:25 PM PDT 24
Peak memory 219280 kb
Host smart-33530f57-a20e-4dc7-9268-72980e5bf9b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2916678024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2916678024
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1030162574
Short name T538
Test name
Test status
Simulation time 5430072981 ps
CPU time 14.91 seconds
Started Aug 06 07:54:17 PM PDT 24
Finished Aug 06 07:54:32 PM PDT 24
Peak memory 216748 kb
Host smart-87733ace-1c00-45ba-b690-e6f899ce4ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030162574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1030162574
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1242316903
Short name T513
Test name
Test status
Simulation time 5049750934 ps
CPU time 7.49 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:54:24 PM PDT 24
Peak memory 216816 kb
Host smart-b9a2b614-6fc4-4e92-bf0c-84a9697be577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242316903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1242316903
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3305149218
Short name T332
Test name
Test status
Simulation time 91508347 ps
CPU time 0.68 seconds
Started Aug 06 07:54:13 PM PDT 24
Finished Aug 06 07:54:14 PM PDT 24
Peak memory 206040 kb
Host smart-add56f1c-3bb7-453a-98e2-8f7905efbcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305149218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3305149218
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3522955590
Short name T895
Test name
Test status
Simulation time 48500843 ps
CPU time 0.86 seconds
Started Aug 06 07:54:25 PM PDT 24
Finished Aug 06 07:54:26 PM PDT 24
Peak memory 206400 kb
Host smart-0b842135-cbb5-4963-8fb8-cd09ed93a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522955590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3522955590
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.705950282
Short name T971
Test name
Test status
Simulation time 673776197 ps
CPU time 3.55 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:54:26 PM PDT 24
Peak memory 224608 kb
Host smart-6f8079ff-5521-492c-a34b-8d11e9b3f24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705950282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.705950282
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3065397806
Short name T519
Test name
Test status
Simulation time 14360975 ps
CPU time 0.71 seconds
Started Aug 06 07:54:24 PM PDT 24
Finished Aug 06 07:54:25 PM PDT 24
Peak memory 205836 kb
Host smart-6610ab99-0827-4bf6-bb88-e0521d63ecc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065397806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3065397806
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3424138779
Short name T873
Test name
Test status
Simulation time 846581147 ps
CPU time 4.07 seconds
Started Aug 06 07:54:25 PM PDT 24
Finished Aug 06 07:54:29 PM PDT 24
Peak memory 224936 kb
Host smart-34f6821a-8d33-4f48-8400-0c3c57910d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424138779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3424138779
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.758352826
Short name T326
Test name
Test status
Simulation time 16509549 ps
CPU time 0.8 seconds
Started Aug 06 07:54:24 PM PDT 24
Finished Aug 06 07:54:25 PM PDT 24
Peak memory 207048 kb
Host smart-43966df7-451b-4822-9d17-0481e0b6a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758352826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.758352826
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.474181379
Short name T977
Test name
Test status
Simulation time 54393382961 ps
CPU time 127.65 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:56:31 PM PDT 24
Peak memory 249176 kb
Host smart-e8f25646-4ae0-436b-8011-026e5048f54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474181379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.474181379
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3343201328
Short name T785
Test name
Test status
Simulation time 9297091942 ps
CPU time 72.56 seconds
Started Aug 06 07:54:22 PM PDT 24
Finished Aug 06 07:55:35 PM PDT 24
Peak memory 250676 kb
Host smart-aee4766d-11d1-4ac8-ba04-44a2d3ed6334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343201328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3343201328
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1491965614
Short name T708
Test name
Test status
Simulation time 7976150114 ps
CPU time 62.42 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:55:26 PM PDT 24
Peak memory 251276 kb
Host smart-0f42be9a-b154-42f3-8915-e52578f5f447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491965614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1491965614
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.756813017
Short name T295
Test name
Test status
Simulation time 14738447955 ps
CPU time 47.25 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:55:10 PM PDT 24
Peak memory 250224 kb
Host smart-c6017b76-7840-4014-948e-0ffcadd20492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756813017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.756813017
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3431090814
Short name T208
Test name
Test status
Simulation time 27692014021 ps
CPU time 151.73 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:56:55 PM PDT 24
Peak memory 255180 kb
Host smart-84758ffb-b9f0-487c-9a9f-c42c90fb07a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431090814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3431090814
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2273077043
Short name T218
Test name
Test status
Simulation time 595958511 ps
CPU time 5.19 seconds
Started Aug 06 07:54:27 PM PDT 24
Finished Aug 06 07:54:32 PM PDT 24
Peak memory 224876 kb
Host smart-280494aa-5974-4dc3-92ed-23bfdac33c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273077043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2273077043
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.19442938
Short name T255
Test name
Test status
Simulation time 14601865785 ps
CPU time 86.04 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:55:50 PM PDT 24
Peak memory 233220 kb
Host smart-7b9af3ce-2c0f-4b6b-82e5-8419e264780a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19442938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.19442938
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3756233778
Short name T860
Test name
Test status
Simulation time 496844522 ps
CPU time 4.53 seconds
Started Aug 06 07:54:21 PM PDT 24
Finished Aug 06 07:54:25 PM PDT 24
Peak memory 239300 kb
Host smart-89da6e33-03e5-40c1-b3ec-551ab8ae6e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756233778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3756233778
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.969928601
Short name T162
Test name
Test status
Simulation time 1027205856 ps
CPU time 3.74 seconds
Started Aug 06 07:54:22 PM PDT 24
Finished Aug 06 07:54:25 PM PDT 24
Peak memory 233084 kb
Host smart-9fdd3b6a-2b33-4714-8815-dcae610c24e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969928601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.969928601
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3248816982
Short name T915
Test name
Test status
Simulation time 747707863 ps
CPU time 4.81 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:54:28 PM PDT 24
Peak memory 220912 kb
Host smart-0e29cdc2-fda2-4d0f-ba51-4f61b1453744
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3248816982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3248816982
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1393330865
Short name T149
Test name
Test status
Simulation time 1608792674 ps
CPU time 42.15 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:55:05 PM PDT 24
Peak memory 249748 kb
Host smart-35c99ef3-631d-4e69-bb96-73028d18b455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393330865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1393330865
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3845625421
Short name T25
Test name
Test status
Simulation time 7330417510 ps
CPU time 29.78 seconds
Started Aug 06 07:54:23 PM PDT 24
Finished Aug 06 07:54:53 PM PDT 24
Peak memory 216404 kb
Host smart-fb434a90-82df-445f-9154-1628bb6f0a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845625421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3845625421
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3235437306
Short name T482
Test name
Test status
Simulation time 647549961 ps
CPU time 5.73 seconds
Started Aug 06 07:54:27 PM PDT 24
Finished Aug 06 07:54:33 PM PDT 24
Peak memory 216616 kb
Host smart-d0bcd1e0-fde3-45e3-9466-164a80dd6c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235437306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3235437306
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.222919565
Short name T412
Test name
Test status
Simulation time 234717011 ps
CPU time 1.64 seconds
Started Aug 06 07:54:24 PM PDT 24
Finished Aug 06 07:54:26 PM PDT 24
Peak memory 216716 kb
Host smart-c1c41b76-3809-4f79-8152-dc4b00ae4c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222919565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.222919565
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1013050093
Short name T811
Test name
Test status
Simulation time 11113694 ps
CPU time 0.67 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:54:17 PM PDT 24
Peak memory 206028 kb
Host smart-ac9aac50-3cfb-46eb-b5e3-c88f410effdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013050093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1013050093
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.731295209
Short name T744
Test name
Test status
Simulation time 165800029 ps
CPU time 3.86 seconds
Started Aug 06 07:54:16 PM PDT 24
Finished Aug 06 07:54:19 PM PDT 24
Peak memory 232976 kb
Host smart-c9516204-15a8-4e83-9324-ef68caa7aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731295209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.731295209
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1148696520
Short name T735
Test name
Test status
Simulation time 33881607 ps
CPU time 0.71 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:51:57 PM PDT 24
Peak memory 205820 kb
Host smart-64c4a662-cfa6-46d1-bbaa-d1c6e18db65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148696520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
148696520
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2975009100
Short name T608
Test name
Test status
Simulation time 1880510160 ps
CPU time 6.19 seconds
Started Aug 06 07:52:10 PM PDT 24
Finished Aug 06 07:52:17 PM PDT 24
Peak memory 224892 kb
Host smart-ac72e896-e892-451c-bfd3-845d73c3c2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975009100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2975009100
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1904448918
Short name T58
Test name
Test status
Simulation time 21388950 ps
CPU time 0.79 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:17 PM PDT 24
Peak memory 207004 kb
Host smart-dee7ca52-ed21-423d-8931-dfecd9e24343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904448918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1904448918
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1799192121
Short name T580
Test name
Test status
Simulation time 28983642515 ps
CPU time 120.48 seconds
Started Aug 06 07:51:56 PM PDT 24
Finished Aug 06 07:53:56 PM PDT 24
Peak memory 253720 kb
Host smart-aadaa221-5a3b-410a-8e6e-c48d7800c6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799192121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1799192121
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2277076892
Short name T395
Test name
Test status
Simulation time 54655572808 ps
CPU time 140.67 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:54:18 PM PDT 24
Peak memory 250556 kb
Host smart-02bf7b01-722d-4889-b36a-e8866e224052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277076892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2277076892
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.522738645
Short name T349
Test name
Test status
Simulation time 27207903733 ps
CPU time 22.46 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:52:24 PM PDT 24
Peak memory 235300 kb
Host smart-8634a590-d76b-4b0b-8306-7b559d04e239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522738645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.522738645
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1538626854
Short name T82
Test name
Test status
Simulation time 14072456755 ps
CPU time 72.49 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:53:10 PM PDT 24
Peak memory 249592 kb
Host smart-17267e36-04b8-49cf-8d0a-0069dc289653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538626854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1538626854
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2609404027
Short name T252
Test name
Test status
Simulation time 217053452 ps
CPU time 3.14 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:52:09 PM PDT 24
Peak memory 224876 kb
Host smart-624f9b50-e1f2-4ed0-b44c-6e824c85a4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609404027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2609404027
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2558280718
Short name T504
Test name
Test status
Simulation time 2580702236 ps
CPU time 22.83 seconds
Started Aug 06 07:52:09 PM PDT 24
Finished Aug 06 07:52:32 PM PDT 24
Peak memory 240616 kb
Host smart-e6ee6f05-900f-4f27-9005-e9f7e98321cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558280718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2558280718
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.195102657
Short name T733
Test name
Test status
Simulation time 106104151 ps
CPU time 2.34 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 224856 kb
Host smart-d59856c4-0d17-4877-837c-ad91c5ef0017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195102657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
195102657
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.790696973
Short name T887
Test name
Test status
Simulation time 1508284531 ps
CPU time 4.67 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:52:10 PM PDT 24
Peak memory 233136 kb
Host smart-5225789b-9671-4903-a3dc-db94024f161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790696973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.790696973
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.84928127
Short name T356
Test name
Test status
Simulation time 493325140 ps
CPU time 3.32 seconds
Started Aug 06 07:51:56 PM PDT 24
Finished Aug 06 07:52:00 PM PDT 24
Peak memory 219296 kb
Host smart-cfac66b2-0cf4-4c8e-b1cb-b777e4022307
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=84928127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct
.84928127
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1183897073
Short name T150
Test name
Test status
Simulation time 3762443194 ps
CPU time 53.43 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:52:50 PM PDT 24
Peak memory 249620 kb
Host smart-6974b62a-6fa1-4944-9115-0f2570250a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183897073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1183897073
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2378548842
Short name T655
Test name
Test status
Simulation time 198833853 ps
CPU time 3.86 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:52:01 PM PDT 24
Peak memory 216716 kb
Host smart-9ae20cb6-21f6-4a96-954e-d19c4cfb9857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378548842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2378548842
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.903594335
Short name T790
Test name
Test status
Simulation time 1638717320 ps
CPU time 8.7 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:52:15 PM PDT 24
Peak memory 216648 kb
Host smart-0a41c598-df19-40b6-92e5-2647c75be21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903594335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.903594335
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1658417095
Short name T312
Test name
Test status
Simulation time 125380898 ps
CPU time 1.15 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 208316 kb
Host smart-45c10098-7c04-4d5b-8868-3f64fa0fa3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658417095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1658417095
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1637587509
Short name T502
Test name
Test status
Simulation time 20070616 ps
CPU time 0.86 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:52:07 PM PDT 24
Peak memory 206340 kb
Host smart-3a429e41-6983-470c-b01f-a079a14c3c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637587509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1637587509
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3030216120
Short name T273
Test name
Test status
Simulation time 608657215 ps
CPU time 2.93 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:03 PM PDT 24
Peak memory 233084 kb
Host smart-bf802743-60dc-487e-90dd-636abba4a672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030216120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3030216120
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.434718642
Short name T868
Test name
Test status
Simulation time 13218441 ps
CPU time 0.7 seconds
Started Aug 06 07:52:07 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 206140 kb
Host smart-e1902c01-3278-4820-8e30-25da81681889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434718642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.434718642
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.231926807
Short name T727
Test name
Test status
Simulation time 565308501 ps
CPU time 2.57 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:19 PM PDT 24
Peak memory 233028 kb
Host smart-4bc31621-0237-47dc-abd4-aeb6c897bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231926807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.231926807
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1934611445
Short name T560
Test name
Test status
Simulation time 27752540 ps
CPU time 0.76 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:51:58 PM PDT 24
Peak memory 206980 kb
Host smart-592196b4-a57a-4aee-9a65-34c1fc105bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934611445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1934611445
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1735232023
Short name T339
Test name
Test status
Simulation time 3361460198 ps
CPU time 10.97 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:52:09 PM PDT 24
Peak memory 235508 kb
Host smart-0b119251-052f-47f3-a698-3146de9ceaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735232023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1735232023
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2869091226
Short name T985
Test name
Test status
Simulation time 41341886600 ps
CPU time 128.47 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:54:10 PM PDT 24
Peak memory 238396 kb
Host smart-202759d7-4c0a-4445-bc50-22a3feb84be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869091226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2869091226
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.271266976
Short name T506
Test name
Test status
Simulation time 16380073802 ps
CPU time 34.96 seconds
Started Aug 06 07:52:14 PM PDT 24
Finished Aug 06 07:52:49 PM PDT 24
Peak memory 217912 kb
Host smart-a3464458-b6aa-4754-a419-20e2baa49a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271266976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
271266976
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2056724033
Short name T822
Test name
Test status
Simulation time 364149527 ps
CPU time 8.51 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 233356 kb
Host smart-1e0b7f0a-6741-4c0b-a94f-8e0536a69d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056724033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2056724033
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3433347780
Short name T848
Test name
Test status
Simulation time 35179102940 ps
CPU time 46.67 seconds
Started Aug 06 07:51:56 PM PDT 24
Finished Aug 06 07:52:43 PM PDT 24
Peak memory 239260 kb
Host smart-207a5a9e-d023-46b4-beff-b77ba17f36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433347780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3433347780
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3756943813
Short name T225
Test name
Test status
Simulation time 1277194792 ps
CPU time 7.73 seconds
Started Aug 06 07:52:01 PM PDT 24
Finished Aug 06 07:52:09 PM PDT 24
Peak memory 233096 kb
Host smart-cafe074b-d964-46d2-9865-0bf31d0e6c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756943813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3756943813
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1081934526
Short name T898
Test name
Test status
Simulation time 1422455214 ps
CPU time 3.63 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:04 PM PDT 24
Peak memory 224828 kb
Host smart-42476bf2-ba64-4c19-8437-fc16da1b61e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081934526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1081934526
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.364373727
Short name T690
Test name
Test status
Simulation time 185824251 ps
CPU time 4.24 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:05 PM PDT 24
Peak memory 224808 kb
Host smart-aaaf6850-cede-40b1-840d-90ea65414196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364373727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
364373727
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1209871151
Short name T568
Test name
Test status
Simulation time 12661600463 ps
CPU time 35.89 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:52:35 PM PDT 24
Peak memory 233420 kb
Host smart-da1870af-4fb1-496a-bbef-c5b338886dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209871151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1209871151
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2911463031
Short name T37
Test name
Test status
Simulation time 1552806900 ps
CPU time 6.45 seconds
Started Aug 06 07:52:14 PM PDT 24
Finished Aug 06 07:52:21 PM PDT 24
Peak memory 220516 kb
Host smart-c6353fab-d575-42e1-9e6f-69e055f1434b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2911463031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2911463031
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2547553375
Short name T20
Test name
Test status
Simulation time 12329027922 ps
CPU time 55.82 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:52:53 PM PDT 24
Peak memory 253484 kb
Host smart-a07eac79-a3b5-4806-8d66-f874bb98d8f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547553375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2547553375
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3496210225
Short name T448
Test name
Test status
Simulation time 41620959 ps
CPU time 0.73 seconds
Started Aug 06 07:52:01 PM PDT 24
Finished Aug 06 07:52:02 PM PDT 24
Peak memory 206040 kb
Host smart-e94666d8-894f-49ef-aae3-e99102204f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496210225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3496210225
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3503123988
Short name T813
Test name
Test status
Simulation time 232207175 ps
CPU time 2.25 seconds
Started Aug 06 07:51:55 PM PDT 24
Finished Aug 06 07:51:58 PM PDT 24
Peak memory 215780 kb
Host smart-dda2a9e2-b943-483d-b006-7086fd0fb594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503123988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3503123988
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.696850249
Short name T492
Test name
Test status
Simulation time 720771759 ps
CPU time 2.12 seconds
Started Aug 06 07:51:55 PM PDT 24
Finished Aug 06 07:51:58 PM PDT 24
Peak memory 215740 kb
Host smart-e96185e8-e98d-4f61-85c8-8ef44b534ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696850249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.696850249
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.112854253
Short name T330
Test name
Test status
Simulation time 105381288 ps
CPU time 0.82 seconds
Started Aug 06 07:52:01 PM PDT 24
Finished Aug 06 07:52:02 PM PDT 24
Peak memory 206308 kb
Host smart-a67c50cd-7a47-458f-8408-305b831363f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112854253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.112854253
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1785768221
Short name T666
Test name
Test status
Simulation time 179042038 ps
CPU time 4.27 seconds
Started Aug 06 07:52:12 PM PDT 24
Finished Aug 06 07:52:16 PM PDT 24
Peak memory 224836 kb
Host smart-23f95738-421a-4d34-a5a4-274f589ab6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785768221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1785768221
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1492328698
Short name T389
Test name
Test status
Simulation time 39494516 ps
CPU time 0.82 seconds
Started Aug 06 07:51:55 PM PDT 24
Finished Aug 06 07:51:56 PM PDT 24
Peak memory 205252 kb
Host smart-41afb8ba-47fe-4c8b-8214-a792088c70f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492328698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
492328698
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2456685333
Short name T387
Test name
Test status
Simulation time 461294343 ps
CPU time 2.6 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:19 PM PDT 24
Peak memory 224768 kb
Host smart-284c9079-39f3-42ac-ad1c-633adeb44dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456685333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2456685333
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2294619705
Short name T475
Test name
Test status
Simulation time 45111928 ps
CPU time 0.75 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:17 PM PDT 24
Peak memory 205992 kb
Host smart-dbcb3772-fe79-44b4-a30f-a079c3968832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294619705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2294619705
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3815831305
Short name T3
Test name
Test status
Simulation time 736583058 ps
CPU time 16.1 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:52:22 PM PDT 24
Peak memory 238652 kb
Host smart-e77d942c-26ac-4ac9-b986-6a12ece5f8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815831305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3815831305
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.532965296
Short name T239
Test name
Test status
Simulation time 79735049286 ps
CPU time 176.58 seconds
Started Aug 06 07:51:57 PM PDT 24
Finished Aug 06 07:54:53 PM PDT 24
Peak memory 249664 kb
Host smart-c65dfbe8-a4da-4ea6-9530-fdcdc9f663f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532965296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.532965296
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.66821198
Short name T427
Test name
Test status
Simulation time 14576879996 ps
CPU time 121.41 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:53:52 PM PDT 24
Peak memory 249600 kb
Host smart-2f01b941-46c6-45b6-af18-7d390c531a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66821198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.66821198
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1844760948
Short name T34
Test name
Test status
Simulation time 414019389 ps
CPU time 10.09 seconds
Started Aug 06 07:51:53 PM PDT 24
Finished Aug 06 07:52:04 PM PDT 24
Peak memory 240416 kb
Host smart-be5fb36d-d9eb-42fe-a422-6853e8824fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844760948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1844760948
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2381902331
Short name T929
Test name
Test status
Simulation time 6222583249 ps
CPU time 11.85 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:28 PM PDT 24
Peak memory 224892 kb
Host smart-5fcd319f-51af-40c2-be0e-f8513ef74d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381902331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2381902331
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.579027970
Short name T488
Test name
Test status
Simulation time 27623988810 ps
CPU time 13.04 seconds
Started Aug 06 07:52:04 PM PDT 24
Finished Aug 06 07:52:17 PM PDT 24
Peak memory 233248 kb
Host smart-83af1ecc-2135-4b1a-9324-1b6fedbbd524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579027970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.579027970
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1797155935
Short name T232
Test name
Test status
Simulation time 3241702688 ps
CPU time 34.53 seconds
Started Aug 06 07:51:50 PM PDT 24
Finished Aug 06 07:52:25 PM PDT 24
Peak memory 235356 kb
Host smart-dd877e50-c41a-4448-bb31-693ee5854dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797155935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1797155935
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2220900689
Short name T965
Test name
Test status
Simulation time 175354781 ps
CPU time 2.15 seconds
Started Aug 06 07:52:22 PM PDT 24
Finished Aug 06 07:52:24 PM PDT 24
Peak memory 224068 kb
Host smart-09cf647b-215a-4918-a85f-c87d1eeed57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220900689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2220900689
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3997596647
Short name T954
Test name
Test status
Simulation time 190283545 ps
CPU time 2.61 seconds
Started Aug 06 07:52:08 PM PDT 24
Finished Aug 06 07:52:10 PM PDT 24
Peak memory 233124 kb
Host smart-e0f6aaa9-edca-4cf9-ab83-49ff462700e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997596647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3997596647
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.319398603
Short name T689
Test name
Test status
Simulation time 4792539205 ps
CPU time 15.32 seconds
Started Aug 06 07:51:55 PM PDT 24
Finished Aug 06 07:52:11 PM PDT 24
Peak memory 223640 kb
Host smart-17e50152-4d20-4caf-ac99-bf5c1aba1ff6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=319398603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.319398603
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3072406367
Short name T845
Test name
Test status
Simulation time 52856141390 ps
CPU time 23.73 seconds
Started Aug 06 07:52:00 PM PDT 24
Finished Aug 06 07:52:24 PM PDT 24
Peak memory 216716 kb
Host smart-3c81be7a-de5f-4363-8485-0df101f665ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072406367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3072406367
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2169913587
Short name T968
Test name
Test status
Simulation time 18578204279 ps
CPU time 8.26 seconds
Started Aug 06 07:51:58 PM PDT 24
Finished Aug 06 07:52:06 PM PDT 24
Peak memory 217900 kb
Host smart-dee1730d-e653-4ed1-8202-27af9329dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169913587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2169913587
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.938534575
Short name T973
Test name
Test status
Simulation time 77959443 ps
CPU time 1.69 seconds
Started Aug 06 07:52:06 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 216556 kb
Host smart-c51c57ae-2b49-4caf-9721-50f2d67f8ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938534575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.938534575
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3119371809
Short name T358
Test name
Test status
Simulation time 161272690 ps
CPU time 0.99 seconds
Started Aug 06 07:52:20 PM PDT 24
Finished Aug 06 07:52:21 PM PDT 24
Peak memory 207336 kb
Host smart-c3c8589b-a730-41cc-b0c3-f1fc278435d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119371809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3119371809
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2858289005
Short name T452
Test name
Test status
Simulation time 218751661 ps
CPU time 2.61 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 224916 kb
Host smart-6d31a002-c97a-4daf-8bb2-53c9d900fbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858289005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2858289005
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.730580982
Short name T801
Test name
Test status
Simulation time 31260175 ps
CPU time 0.72 seconds
Started Aug 06 07:52:11 PM PDT 24
Finished Aug 06 07:52:12 PM PDT 24
Peak memory 205320 kb
Host smart-11f2006f-a388-49ed-8a7b-bd2bcae84976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730580982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.730580982
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3982987803
Short name T715
Test name
Test status
Simulation time 1694168268 ps
CPU time 5.13 seconds
Started Aug 06 07:52:11 PM PDT 24
Finished Aug 06 07:52:16 PM PDT 24
Peak memory 224884 kb
Host smart-5239a6b0-969c-4847-85ff-16e865200a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982987803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3982987803
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2019850299
Short name T401
Test name
Test status
Simulation time 55703428 ps
CPU time 0.78 seconds
Started Aug 06 07:52:01 PM PDT 24
Finished Aug 06 07:52:02 PM PDT 24
Peak memory 206816 kb
Host smart-9e242409-1de9-48e0-bb69-bb482c15c40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019850299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2019850299
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4007481692
Short name T694
Test name
Test status
Simulation time 9711049637 ps
CPU time 74.36 seconds
Started Aug 06 07:51:59 PM PDT 24
Finished Aug 06 07:53:14 PM PDT 24
Peak memory 252172 kb
Host smart-eb8b0a31-06dd-4c5d-b592-2ec3a46bd016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007481692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4007481692
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.851986444
Short name T411
Test name
Test status
Simulation time 4339547191 ps
CPU time 84.08 seconds
Started Aug 06 07:52:12 PM PDT 24
Finished Aug 06 07:53:36 PM PDT 24
Peak memory 257840 kb
Host smart-8322d716-e85d-4c27-9041-5e53fd784291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851986444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.851986444
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.284674801
Short name T550
Test name
Test status
Simulation time 11140940553 ps
CPU time 69.46 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 233188 kb
Host smart-bf3233ed-6b85-4c03-8cde-af0c2f83792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284674801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
284674801
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2596445289
Short name T59
Test name
Test status
Simulation time 20693170046 ps
CPU time 189.73 seconds
Started Aug 06 07:52:24 PM PDT 24
Finished Aug 06 07:55:34 PM PDT 24
Peak memory 254168 kb
Host smart-c16fd26c-d980-4836-94c3-baffce74c685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596445289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2596445289
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4253578000
Short name T837
Test name
Test status
Simulation time 100142201 ps
CPU time 2.46 seconds
Started Aug 06 07:52:15 PM PDT 24
Finished Aug 06 07:52:18 PM PDT 24
Peak memory 233144 kb
Host smart-2b318710-09ad-416e-86c5-9ec14494c1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253578000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4253578000
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.247188318
Short name T1002
Test name
Test status
Simulation time 2422311098 ps
CPU time 16.21 seconds
Started Aug 06 07:52:14 PM PDT 24
Finished Aug 06 07:52:30 PM PDT 24
Peak memory 233248 kb
Host smart-4f39a4de-1161-4c4e-a083-4c2c8109797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247188318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.247188318
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1216411764
Short name T794
Test name
Test status
Simulation time 479053884 ps
CPU time 7.91 seconds
Started Aug 06 07:52:03 PM PDT 24
Finished Aug 06 07:52:11 PM PDT 24
Peak memory 257008 kb
Host smart-ee4c0a15-ce6e-4a9c-be0e-3ebeb8afefca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216411764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1216411764
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3199369295
Short name T978
Test name
Test status
Simulation time 527090774 ps
CPU time 4.47 seconds
Started Aug 06 07:52:20 PM PDT 24
Finished Aug 06 07:52:24 PM PDT 24
Peak memory 233172 kb
Host smart-215f1749-63be-4071-a245-26d1a8426419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199369295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3199369295
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1911343653
Short name T137
Test name
Test status
Simulation time 1290615417 ps
CPU time 5.06 seconds
Started Aug 06 07:52:12 PM PDT 24
Finished Aug 06 07:52:17 PM PDT 24
Peak memory 219804 kb
Host smart-a2e5eafb-3dd7-43fd-80e7-050a141c0eca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1911343653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1911343653
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2240161738
Short name T126
Test name
Test status
Simulation time 280370473872 ps
CPU time 748.12 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 08:04:34 PM PDT 24
Peak memory 306976 kb
Host smart-b8d9aaab-f53a-440e-b33e-4a794c83e45e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240161738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2240161738
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2256089817
Short name T854
Test name
Test status
Simulation time 1006997226 ps
CPU time 4.58 seconds
Started Aug 06 07:52:15 PM PDT 24
Finished Aug 06 07:52:20 PM PDT 24
Peak memory 216660 kb
Host smart-cfbc42d5-8bed-4fdd-82b6-fc8a9af72662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256089817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2256089817
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.514704680
Short name T511
Test name
Test status
Simulation time 67673315 ps
CPU time 0.9 seconds
Started Aug 06 07:52:12 PM PDT 24
Finished Aug 06 07:52:13 PM PDT 24
Peak memory 207800 kb
Host smart-e471506e-9f19-43bc-9081-0b2da7cfd1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514704680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.514704680
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2786031985
Short name T327
Test name
Test status
Simulation time 149591037 ps
CPU time 0.78 seconds
Started Aug 06 07:52:14 PM PDT 24
Finished Aug 06 07:52:15 PM PDT 24
Peak memory 206324 kb
Host smart-351f0ab9-d6d4-48b0-8070-2761290df692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786031985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2786031985
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4262866366
Short name T864
Test name
Test status
Simulation time 10262424808 ps
CPU time 19.06 seconds
Started Aug 06 07:52:14 PM PDT 24
Finished Aug 06 07:52:33 PM PDT 24
Peak memory 233148 kb
Host smart-1c145de7-a03d-4b14-85b5-364782ca2dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262866366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4262866366
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2004564442
Short name T500
Test name
Test status
Simulation time 44595395 ps
CPU time 0.7 seconds
Started Aug 06 07:52:03 PM PDT 24
Finished Aug 06 07:52:04 PM PDT 24
Peak memory 205808 kb
Host smart-861b04b8-f0f6-4857-875e-11ae1a405690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004564442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
004564442
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1880738535
Short name T752
Test name
Test status
Simulation time 134775579 ps
CPU time 2.27 seconds
Started Aug 06 07:52:05 PM PDT 24
Finished Aug 06 07:52:07 PM PDT 24
Peak memory 224372 kb
Host smart-1059812e-a7b4-4ee4-8103-b19d234a26ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880738535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1880738535
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2596707211
Short name T818
Test name
Test status
Simulation time 68508923 ps
CPU time 0.81 seconds
Started Aug 06 07:52:02 PM PDT 24
Finished Aug 06 07:52:03 PM PDT 24
Peak memory 207044 kb
Host smart-ac13a1a6-947c-4fc2-bf0c-2d6cf4fc37fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596707211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2596707211
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2158614689
Short name T420
Test name
Test status
Simulation time 6954769374 ps
CPU time 64.12 seconds
Started Aug 06 07:52:19 PM PDT 24
Finished Aug 06 07:53:23 PM PDT 24
Peak memory 252796 kb
Host smart-106d306d-3cf2-4962-a8cb-5c925a66b7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158614689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2158614689
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3062276959
Short name T55
Test name
Test status
Simulation time 17268542358 ps
CPU time 54.3 seconds
Started Aug 06 07:52:11 PM PDT 24
Finished Aug 06 07:53:06 PM PDT 24
Peak memory 257556 kb
Host smart-22e9b46d-5a3c-4e53-b834-34b6d7882cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062276959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3062276959
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3986807824
Short name T193
Test name
Test status
Simulation time 15996627335 ps
CPU time 93.25 seconds
Started Aug 06 07:52:10 PM PDT 24
Finished Aug 06 07:53:44 PM PDT 24
Peak memory 256464 kb
Host smart-750bc487-d03a-444f-96f5-637026fa30b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986807824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3986807824
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1105557701
Short name T680
Test name
Test status
Simulation time 735657358 ps
CPU time 7.34 seconds
Started Aug 06 07:52:11 PM PDT 24
Finished Aug 06 07:52:18 PM PDT 24
Peak memory 233064 kb
Host smart-5d9a50e8-c9eb-45fc-a318-1bd7d3120746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105557701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1105557701
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2736842348
Short name T276
Test name
Test status
Simulation time 186094366648 ps
CPU time 150.21 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:54:46 PM PDT 24
Peak memory 256436 kb
Host smart-70d04131-46a1-4ee9-aa25-00fc13b05997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736842348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2736842348
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2036216130
Short name T399
Test name
Test status
Simulation time 230044795 ps
CPU time 4.14 seconds
Started Aug 06 07:52:20 PM PDT 24
Finished Aug 06 07:52:25 PM PDT 24
Peak memory 233144 kb
Host smart-f01a8345-4367-491e-97af-ba8b862b4205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036216130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2036216130
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2223166136
Short name T590
Test name
Test status
Simulation time 10390843531 ps
CPU time 20.06 seconds
Started Aug 06 07:52:18 PM PDT 24
Finished Aug 06 07:52:38 PM PDT 24
Peak memory 225012 kb
Host smart-4c71fb38-ff6b-429d-897e-8ac4f77036a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223166136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2223166136
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3249146537
Short name T539
Test name
Test status
Simulation time 2113176781 ps
CPU time 7.25 seconds
Started Aug 06 07:52:16 PM PDT 24
Finished Aug 06 07:52:23 PM PDT 24
Peak memory 233068 kb
Host smart-ee92602e-2755-42e0-82ee-a6c5d456c315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249146537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3249146537
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1542603588
Short name T245
Test name
Test status
Simulation time 1272612000 ps
CPU time 2.85 seconds
Started Aug 06 07:52:23 PM PDT 24
Finished Aug 06 07:52:26 PM PDT 24
Peak memory 224856 kb
Host smart-9703821d-942d-4944-92a6-a4c921160124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542603588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1542603588
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2875032240
Short name T940
Test name
Test status
Simulation time 1377468450 ps
CPU time 4.64 seconds
Started Aug 06 07:52:09 PM PDT 24
Finished Aug 06 07:52:14 PM PDT 24
Peak memory 220380 kb
Host smart-91d5e37f-5292-4cab-b13f-a861c95e3c20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2875032240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2875032240
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.572226995
Short name T717
Test name
Test status
Simulation time 7040449726 ps
CPU time 24.79 seconds
Started Aug 06 07:52:07 PM PDT 24
Finished Aug 06 07:52:32 PM PDT 24
Peak memory 225000 kb
Host smart-35333623-6dc2-4ef9-840f-df23ee498fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572226995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.572226995
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2928744012
Short name T832
Test name
Test status
Simulation time 13082426 ps
CPU time 0.72 seconds
Started Aug 06 07:52:08 PM PDT 24
Finished Aug 06 07:52:09 PM PDT 24
Peak memory 206060 kb
Host smart-d621b3c1-41b7-403e-86f9-b806b82b3edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928744012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2928744012
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.553425250
Short name T447
Test name
Test status
Simulation time 7333748518 ps
CPU time 13.01 seconds
Started Aug 06 07:52:10 PM PDT 24
Finished Aug 06 07:52:23 PM PDT 24
Peak memory 216668 kb
Host smart-4cce46cc-3db3-4e64-a7ef-2d91f81e9470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553425250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.553425250
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1597414581
Short name T314
Test name
Test status
Simulation time 343736877 ps
CPU time 1.26 seconds
Started Aug 06 07:52:34 PM PDT 24
Finished Aug 06 07:52:35 PM PDT 24
Peak memory 207420 kb
Host smart-7ce72c11-4751-47fd-9eda-c7b355cce787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597414581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1597414581
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2092182724
Short name T397
Test name
Test status
Simulation time 23976872 ps
CPU time 0.79 seconds
Started Aug 06 07:52:07 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 206400 kb
Host smart-5d8bfc8d-ed60-460e-8154-c389e8a9fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092182724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2092182724
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1296145684
Short name T398
Test name
Test status
Simulation time 8698160056 ps
CPU time 12.08 seconds
Started Aug 06 07:52:15 PM PDT 24
Finished Aug 06 07:52:27 PM PDT 24
Peak memory 233232 kb
Host smart-8074e7d1-fb38-4caa-a9d6-735dd3cc496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296145684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1296145684
Directory /workspace/9.spi_device_upload/latest
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