Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3183692	1			T1	1		T2	713		T3	5355
all_values[1]	3183692	1			T1	1		T2	713		T3	5355
all_values[2]	3183692	1			T1	1		T2	713		T3	5355
all_values[3]	3183692	1			T1	1		T2	713		T3	5355
all_values[4]	3183692	1			T1	1		T2	713		T3	5355
all_values[5]	3183692	1			T1	1		T2	713		T3	5355
all_values[6]	3183692	1			T1	1		T2	713		T3	5355
all_values[7]	3183692	1			T1	1		T2	713		T3	5355

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25029956

1

T1

8

T2

5704

T3

42770

auto[1]

439580

1

T3

70

T12

120

T15

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25439253

1

T1

8

T2

5704

T3

42487

auto[1]

30283

1

T3

353

T11

630

T12

69

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3152677	1			T1	1		T2	713		T3	5218
all_values[0]	auto[0]	auto[1]	14259	1			T3	128		T11	290		T12	2
all_values[0]	auto[1]	auto[0]	16154	1			T3	7		T12	11		T15	1
all_values[0]	auto[1]	auto[1]	602	1			T3	2		T12	8		T15	1
all_values[1]	auto[0]	auto[0]	3074645	1			T1	1		T2	713		T3	5251
all_values[1]	auto[0]	auto[1]	9190	1			T3	93		T11	239		T12	5
all_values[1]	auto[1]	auto[0]	99110	1			T3	8		T12	9		T15	1
all_values[1]	auto[1]	auto[1]	747	1			T3	3		T12	6		T15	1
all_values[2]	auto[0]	auto[0]	3133725	1			T1	1		T2	713		T3	5260
all_values[2]	auto[0]	auto[1]	3472	1			T3	90		T11	101		T12	4
all_values[2]	auto[1]	auto[0]	46226	1			T3	3		T12	12		T16	8
all_values[2]	auto[1]	auto[1]	269	1			T3	2		T12	2		T15	1
all_values[3]	auto[0]	auto[0]	3156796	1			T1	1		T2	713		T3	5346
all_values[3]	auto[0]	auto[1]	182	1			T3	3		T12	4		T15	2
all_values[3]	auto[1]	auto[0]	26546	1			T3	3		T12	12		T15	3
all_values[3]	auto[1]	auto[1]	168	1			T3	3		T12	6		T15	4
all_values[4]	auto[0]	auto[0]	3159379	1			T1	1		T2	713		T3	5340
all_values[4]	auto[0]	auto[1]	172	1			T3	5		T12	3		T15	1
all_values[4]	auto[1]	auto[0]	23961	1			T3	7		T12	10		T15	2
all_values[4]	auto[1]	auto[1]	180	1			T3	3		T12	4		T15	1
all_values[5]	auto[0]	auto[0]	3078661	1			T1	1		T2	713		T3	5344
all_values[5]	auto[0]	auto[1]	155	1			T3	3		T12	6		T15	3
all_values[5]	auto[1]	auto[0]	104712	1			T3	7		T12	6		T15	5
all_values[5]	auto[1]	auto[1]	164	1			T3	1		T12	3		T15	1
all_values[6]	auto[0]	auto[0]	3111390	1			T1	1		T2	713		T3	5343
all_values[6]	auto[0]	auto[1]	186	1			T3	5		T12	4		T15	3
all_values[6]	auto[1]	auto[0]	71926	1			T3	1		T12	9		T15	4
all_values[6]	auto[1]	auto[1]	190	1			T3	6		T12	4		T15	2
all_values[7]	auto[0]	auto[0]	3134893	1			T1	1		T2	713		T3	5340
all_values[7]	auto[0]	auto[1]	174	1			T3	1		T12	2		T16	2
all_values[7]	auto[1]	auto[0]	48452	1			T3	9		T12	12		T15	8
all_values[7]	auto[1]	auto[1]	173	1			T3	5		T12	6		T15	1