Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33417	1			T2	107		T3	223		T6	66
auto[SpiFlashAddrCfg]	7807	1			T1	4		T2	36		T3	62
auto[SpiFlashAddr3b]	9170	1			T1	2		T2	59		T3	63
auto[SpiFlashAddr4b]	7888	1			T2	38		T3	53		T4	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33593

1

T1

6

T2

135

T3

216

auto[1]

24689

1

T2

105

T3

185

T6

117

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30725

1

T2

151

T3

280

T4

5

auto[1]

27557

1

T1

6

T2

89

T3

121

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38114	1			T2	113		T3	255		T6	100
values[1]	1066	1			T2	4		T3	3		T6	18
values[2]	1553	1			T2	3		T3	22		T6	6
values[3]	1507	1			T2	16		T3	1		T6	9
values[4]	1433	1			T2	5		T3	14		T6	18
values[5]	1500	1			T2	12		T3	12		T4	3
values[6]	1482	1			T2	11		T3	10		T6	4
values[7]	1460	1			T2	10		T3	10		T6	9
values[8]	10167	1			T1	6		T2	66		T3	74

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31441

1

T1

6

T3

401

T6

240

auto[1]

26841

1

T2

240

T4

11

T26

143

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54995

1

T1

6

T2

228

T3

379

write

3287

1

T2

12

T3

22

T6

15

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19627

1

T1

6

T2

117

T3

138

valids[0x1]

38655

1

T2

123

T3

263

T4

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1505	1			T2	10		T3	8		T6	12
internal_process_ops[0x5a]	1559	1			T2	13		T3	14		T6	5
internal_process_ops[0x05]	19520	1			T2	9		T3	133		T6	4
internal_process_ops[0x35]	1558	1			T2	12		T3	9		T6	13
internal_process_ops[0x15]	1596	1			T2	12		T3	5		T6	8
internal_process_ops[0x03]	1084	1			T2	4		T3	11		T4	3
internal_process_ops[0x0b]	1072	1			T2	1		T3	11		T4	3
internal_process_ops[0x3b]	1117	1			T2	3		T3	8		T4	1
internal_process_ops[0x6b]	1087	1			T1	4		T2	3		T3	7
internal_process_ops[0xbb]	1149	1			T2	4		T3	10		T6	11
internal_process_ops[0xeb]	1137	1			T1	2		T2	5		T3	13

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56709

1

T1

6

T2

232

T3

392

auto[1]

1573

1

T2

8

T3

9

T6

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55844

1

T1

6

T2

235

T3

390

auto[1]

2438

1

T2

5

T3

11

T6

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10327

1

T3

127

T6

46

T7

12

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6266

1

T3

92

T6

20

T8

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2114

1

T1

4

T3

26

T6

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1957

1

T3

34

T6

27

T8

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2665

1

T1

2

T3

27

T6

35

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2249

1

T3

32

T6

30

T8

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2168

1

T3

22

T6

23

T8

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1998

1

T3

19

T6

31

T8

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

100

1

T3

2

T11

2

T24

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

95

1

T3

2

T11

5

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T11

2

T39

3

T17

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

99

1

T11

4

T37

2

T16

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

168

1

T3

2

T6

3

T11

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T6

3

T11

3

T38

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

107

1

T6

2

T11

1

T24

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T6

1

T8

1

T11

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

117

1

T3

2

T11

7

T38

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

127

1

T11

1

T24

1

T31

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

70

1

T8

3

T11

2

T16

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

100

1

T3

2

T8

2

T11

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

122

1

T3

5

T24

4

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

102

1

T3

1

T11

5

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

87

1

T3

2

T6

1

T11

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

113

1

T3

4

T6

5

T8

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9845

1

T2

76

T26

39

T30

53

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6190

1

T2

29

T26

70

T30

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1486

1

T2

17

T4

3

T26

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1365

1

T2

15

T26

2

T30

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1764

1

T2

18

T4

4

T26

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1693

1

T2

37

T26

3

T30

24

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1501

1

T2

18

T4

4

T26

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1407

1

T2

18

T26

9

T30

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

118

1

T151

1

T153

1

T16

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

109

1

T2

1

T41

3

T153

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

75

1

T2

1

T26

1

T42

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T26

1

T30

2

T41

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T26

3

T42

2

T41

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

85

1

T2

3

T41

2

T151

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

139

1

T26

3

T42

3

T71

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

78

1

T2

1

T30

2

T41

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T2

1

T30

2

T41

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

92

1

T154

2

T72

1

T155

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

119

1

T2

1

T42

1

T41

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

86

1

T2

2

T42

1

T71

7

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

109

1

T2

1

T71

2

T151

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

84

1

T30

1

T41

2

T151

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

99

1

T16

1

T72

3

T155

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

98

1

T2

1

T42

4

T71

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4080	1			T3	54		T6	35		T8	23
auto[0]	values[0]	valids[0x1]	15519	1			T3	201		T6	65		T7	12
auto[0]	values[1]	valids[0x1]	575	1			T3	3		T6	18		T8	2
auto[0]	values[2]	valids[0x0]	589	1			T3	13		T6	1		T8	1
auto[0]	values[2]	valids[0x1]	324	1			T3	9		T6	5		T8	2
auto[0]	values[3]	valids[0x0]	583	1			T6	5		T8	5		T11	6
auto[0]	values[3]	valids[0x1]	327	1			T3	1		T6	4		T8	2
auto[0]	values[4]	valids[0x0]	554	1			T3	7		T6	10		T8	3
auto[0]	values[4]	valids[0x1]	304	1			T3	7		T6	8		T8	2
auto[0]	values[5]	valids[0x0]	553	1			T3	9		T6	11		T8	2
auto[0]	values[5]	valids[0x1]	326	1			T3	3		T6	5		T8	3
auto[0]	values[6]	valids[0x0]	622	1			T3	5		T6	3		T8	2
auto[0]	values[6]	valids[0x1]	305	1			T3	5		T6	1		T11	3
auto[0]	values[7]	valids[0x0]	539	1			T3	6		T6	4		T11	9
auto[0]	values[7]	valids[0x1]	339	1			T3	4		T6	5		T11	1
auto[0]	values[8]	valids[0x0]	3716	1			T1	6		T3	44		T6	35
auto[0]	values[8]	valids[0x1]	2186	1			T3	30		T6	25		T8	7
auto[1]	values[0]	valids[0x0]	3776	1			T2	44		T26	18		T30	34
auto[1]	values[0]	valids[0x1]	14739	1			T2	69		T26	99		T30	34
auto[1]	values[1]	valids[0x1]	491	1			T2	4		T26	2		T30	12
auto[1]	values[2]	valids[0x0]	375	1			T2	2		T26	1		T30	7
auto[1]	values[2]	valids[0x1]	265	1			T2	1		T26	2		T30	5
auto[1]	values[3]	valids[0x0]	334	1			T2	7		T42	1		T41	6
auto[1]	values[3]	valids[0x1]	263	1			T2	9		T26	1		T30	1
auto[1]	values[4]	valids[0x0]	342	1			T2	3		T26	1		T30	1
auto[1]	values[4]	valids[0x1]	233	1			T2	2		T30	4		T42	3
auto[1]	values[5]	valids[0x0]	377	1			T2	8		T4	3		T30	3
auto[1]	values[5]	valids[0x1]	244	1			T2	4		T30	2		T41	1
auto[1]	values[6]	valids[0x0]	348	1			T2	8		T30	4		T42	1
auto[1]	values[6]	valids[0x1]	207	1			T2	3		T30	1		T42	3
auto[1]	values[7]	valids[0x0]	357	1			T2	8		T26	1		T30	4
auto[1]	values[7]	valids[0x1]	225	1			T2	2		T30	1		T41	6
auto[1]	values[8]	valids[0x0]	2482	1			T2	37		T4	2		T26	8
auto[1]	values[8]	valids[0x1]	1783	1			T2	29		T4	6		T26	10