Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3395374

1

T1

225

T2

11448

T3

23981

auto[1]

27940

1

T2

341

T3

121

T6

183

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

865945

1

T1

225

T2

529

T3

82

auto[1]

2557369

1

T2

11260

T3

24020

T6

23776

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	580483	1			T1	128		T2	57		T3	314
auto[524288:1048575]	421275	1			T1	1		T2	585		T3	5006
auto[1048576:1572863]	411191	1			T2	9		T3	6255		T4	1164
auto[1572864:2097151]	458085	1			T1	19		T2	640		T3	3763
auto[2097152:2621439]	367618	1			T1	31		T2	2536		T3	3339
auto[2621440:3145727]	416091	1			T1	6		T2	3040		T3	4615
auto[3145728:3670015]	376596	1			T1	1		T2	4900		T3	770
auto[3670016:4194303]	391975	1			T1	39		T2	22		T3	40

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2593534

1

T1

25

T2

11786

T3

24102

auto[1]

829780

1

T1

200

T2

3

T4

2026

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2976713

1

T1

225

T2

10425

T3

18669

auto[1]

446601

1

T2

1364

T3

5433

T6

5311

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	181392	1			T1	128		T2	31		T3	14
auto[0]	auto[0]	auto[0:524287]	auto[1]	341642	1			T3	11		T6	133		T8	128
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	110584	1			T1	1		T2	49		T3	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	245256	1			T2	384		T3	2425		T6	3666
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	101535	1			T2	9		T3	6		T4	1164
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	265015	1			T3	4198		T6	2028		T7	226
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	133153	1			T1	19		T2	75		T3	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	275833	1			T2	466		T3	3234		T6	5706
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	70605	1			T1	31		T2	67		T3	12
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	237049	1			T2	2070		T3	3264		T6	2655
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	112341	1			T1	6		T2	64		T3	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	232731	1			T2	2153		T3	4605		T6	320
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	52868	1			T1	1		T2	74		T3	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	254036	1			T2	4826		T3	768		T6	515
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	90615	1			T1	39		T2	11		T3	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	249935	1			T3	7		T6	3403		T7	1980
auto[0]	auto[1]	auto[0:524287]	auto[0]	869	1			T2	22		T3	9		T8	14
auto[0]	auto[1]	auto[0:524287]	auto[1]	53213	1			T2	4		T3	258		T8	1219
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1180	1			T2	6		T3	1		T6	22
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	59851	1			T3	2577		T11	1205		T42	1831
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1894	1			T3	1		T6	11		T24	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	40499	1			T3	2050		T42	512		T71	131
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1401	1			T2	37		T3	4		T6	24
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	44937	1			T2	62		T3	512		T6	2556
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1469	1			T2	15		T3	1		T6	15
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	54889	1			T2	384		T6	2658		T8	1204
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	705	1			T2	39		T3	5		T8	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	66951	1			T2	591		T3	1		T8	3085
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	706	1			T6	2		T11	3		T30	64
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	65122	1			T11	2994		T30	261		T41	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	668	1			T2	9		T6	10		T11	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	46430	1			T26	1		T71	259		T16	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	482	1			T3	2		T6	8		T11	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2349	1			T3	9		T11	2		T71	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	350	1			T2	16		T6	4		T8	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2055	1			T2	130		T6	5		T8	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	278	1			T11	1		T31	5		T41	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1568	1			T11	2		T153	4		T17	22
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	419	1			T3	1		T6	3		T11	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1856	1			T3	3		T6	46		T11	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	448	1			T3	2		T6	3		T8	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2526	1			T3	60		T6	75		T8	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	382	1			T11	4		T30	2		T31	26
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2263	1			T11	2		T71	2		T153	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	384	1			T6	11		T11	4		T26	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2848	1			T11	1		T26	12		T30	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	486	1			T3	3		T6	5		T11	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3429	1			T3	27		T6	10		T11	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	116	1			T3	2		T8	7		T11	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	420	1			T3	9		T8	50		T11	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	80	1			T6	8		T71	1		T154	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1919	1			T71	1		T154	3		T155	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	89	1			T16	4		T17	1		T19	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	313	1			T16	2		T17	5		T19	7
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	93	1			T6	5		T42	1		T142	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	393	1			T42	10		T142	9		T143	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	105	1			T153	1		T193	3		T155	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	527	1			T153	4		T143	7		T201	33
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	97	1			T2	3		T3	1		T71	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	621	1			T2	190		T3	2		T71	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	90	1			T11	1		T41	1		T71	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	542	1			T71	1		T19	6		T142	16
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	61	1			T2	2		T154	1		T39	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	351	1			T154	2		T72	4		T19	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2129389	1			T1	25		T2	10279		T3	18562
auto[0]	auto[0]	auto[1]	825201	1			T1	200		T4	2026		T7	9071
auto[0]	auto[1]	auto[0]	436887	1			T2	1169		T3	5419		T6	5298
auto[0]	auto[1]	auto[1]	3897	1			T8	5		T135	1263		T219	159
auto[1]	auto[0]	auto[0]	21579	1			T2	144		T3	107		T6	163
auto[1]	auto[0]	auto[1]	544	1			T2	2		T6	7		T11	2
auto[1]	auto[1]	auto[0]	5679	1			T2	194		T3	14		T6	11
auto[1]	auto[1]	auto[1]	138	1			T2	1		T6	2		T8	2