Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3183692	1			T1	1		T2	713		T3	5355
all_pins[1]	3183692	1			T1	1		T2	713		T3	5355
all_pins[2]	3183692	1			T1	1		T2	713		T3	5355
all_pins[3]	3183692	1			T1	1		T2	713		T3	5355
all_pins[4]	3183692	1			T1	1		T2	713		T3	5355
all_pins[5]	3183692	1			T1	1		T2	713		T3	5355
all_pins[6]	3183692	1			T1	1		T2	713		T3	5355
all_pins[7]	3183692	1			T1	1		T2	713		T3	5355

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	25393800	1			T1	8		T2	5704		T3	42815
values[0x1]	75736	1			T3	25		T12	39		T15	12
transitions[0x0=>0x1]	72918	1			T3	20		T12	31		T15	11
transitions[0x1=>0x0]	72933	1			T3	20		T12	31		T15	11

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3183019	1			T1	1		T2	713		T3	5353
all_pins[0]	values[0x1]	673	1			T3	2		T12	8		T15	1
all_pins[0]	transitions[0x0=>0x1]	372	1			T3	1		T12	6		T15	1
all_pins[0]	transitions[0x1=>0x0]	524	1			T3	2		T12	4		T15	1
all_pins[1]	values[0x0]	3182867	1			T1	1		T2	713		T3	5352
all_pins[1]	values[0x1]	825	1			T3	3		T12	6		T15	1
all_pins[1]	transitions[0x0=>0x1]	696	1			T3	3		T12	6		T15	1
all_pins[1]	transitions[0x1=>0x0]	166	1			T3	2		T12	2		T15	1
all_pins[2]	values[0x0]	3183397	1			T1	1		T2	713		T3	5353
all_pins[2]	values[0x1]	295	1			T3	2		T12	2		T15	1
all_pins[2]	transitions[0x0=>0x1]	262	1			T3	2		T15	1		T16	2
all_pins[2]	transitions[0x1=>0x0]	135	1			T3	3		T12	4		T15	4
all_pins[3]	values[0x0]	3183524	1			T1	1		T2	713		T3	5352
all_pins[3]	values[0x1]	168	1			T3	3		T12	6		T15	4
all_pins[3]	transitions[0x0=>0x1]	136	1			T3	3		T12	5		T15	4
all_pins[3]	transitions[0x1=>0x0]	148	1			T3	3		T12	3		T15	1
all_pins[4]	values[0x0]	3183512	1			T1	1		T2	713		T3	5352
all_pins[4]	values[0x1]	180	1			T3	3		T12	4		T15	1
all_pins[4]	transitions[0x0=>0x1]	145	1			T3	3		T12	4		T16	1
all_pins[4]	transitions[0x1=>0x0]	3111	1			T3	1		T12	3		T16	3
all_pins[5]	values[0x0]	3180546	1			T1	1		T2	713		T3	5354
all_pins[5]	values[0x1]	3146	1			T3	1		T12	3		T15	1
all_pins[5]	transitions[0x0=>0x1]	944	1			T3	1		T12	3		T15	1
all_pins[5]	transitions[0x1=>0x0]	68074	1			T3	6		T12	4		T15	2
all_pins[6]	values[0x0]	3113416	1			T1	1		T2	713		T3	5349
all_pins[6]	values[0x1]	70276	1			T3	6		T12	4		T15	2
all_pins[6]	transitions[0x0=>0x1]	70236	1			T3	3		T12	3		T15	2
all_pins[6]	transitions[0x1=>0x0]	133	1			T3	2		T12	5		T15	1
all_pins[7]	values[0x0]	3183519	1			T1	1		T2	713		T3	5350
all_pins[7]	values[0x1]	173	1			T3	5		T12	6		T15	1
all_pins[7]	transitions[0x0=>0x1]	127	1			T3	4		T12	4		T15	1
all_pins[7]	transitions[0x1=>0x0]	642	1			T3	1		T12	6		T15	1