Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18205

1

T1

6

T3

216

T6

123

auto[1]

13236

1

T3

185

T6

117

T8

44

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3620	1			T3	20		T6	20		T8	20
values[1]	4175	1			T3	50		T6	60		T8	20
values[2]	2813	1			T6	20		T7	16		T11	93
values[3]	3703	1			T1	6		T3	31		T6	40
values[4]	4631	1			T3	98		T8	77		T11	62
values[5]	4095	1			T3	75		T6	60		T11	86
values[6]	4149	1			T3	67		T6	20		T8	28
values[7]	4255	1			T3	60		T6	20		T8	24

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3362	1			T3	30		T6	40		T11	42
values[1]	4140	1			T3	70		T6	20		T8	20
values[2]	4271	1			T3	40		T6	40		T8	28
values[3]	4201	1			T3	68		T6	40		T11	84
values[4]	4015	1			T6	40		T8	77		T11	87
values[5]	3851	1			T1	6		T3	173		T6	20
values[6]	3854	1			T6	20		T7	16		T8	44
values[7]	3747	1			T3	20		T6	20		T11	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	233	1			T6	11		T220	6		T178	13
auto[0]	values[0]	values[1]	248	1			T8	8		T31	8		T193	11
auto[0]	values[0]	values[2]	158	1			T9	8		T31	12		T221	4
auto[0]	values[0]	values[3]	272	1			T24	9		T48	6		T50	8
auto[0]	values[0]	values[4]	195	1			T11	16		T217	6		T189	12
auto[0]	values[0]	values[5]	170	1			T135	4		T16	11		T38	16
auto[0]	values[0]	values[6]	356	1			T142	9		T206	8		T202	9
auto[0]	values[0]	values[7]	267	1			T3	8		T17	16		T18	5
auto[0]	values[1]	values[0]	234	1			T39	13		T142	9		T195	13
auto[0]	values[1]	values[1]	247	1			T3	40		T18	15		T189	8
auto[0]	values[1]	values[2]	371	1			T6	8		T222	6		T178	16
auto[0]	values[1]	values[3]	377	1			T11	12		T223	43		T39	14
auto[0]	values[1]	values[4]	332	1			T6	13		T193	11		T119	22
auto[0]	values[1]	values[5]	184	1			T6	10		T11	8		T224	2
auto[0]	values[1]	values[6]	338	1			T8	14		T203	10		T69	20
auto[0]	values[1]	values[7]	287	1			T13	6		T24	23		T31	13
auto[0]	values[2]	values[0]	166	1			T142	11		T206	9		T225	12
auto[0]	values[2]	values[1]	186	1			T31	9		T226	7		T181	68
auto[0]	values[2]	values[2]	208	1			T6	10		T178	15		T187	57
auto[0]	values[2]	values[3]	332	1			T11	20		T38	13		T219	8
auto[0]	values[2]	values[4]	126	1			T175	12		T195	6		T197	9
auto[0]	values[2]	values[5]	193	1			T24	13		T18	9		T227	13
auto[0]	values[2]	values[6]	244	1			T7	16		T11	23		T24	11
auto[0]	values[2]	values[7]	156	1			T228	2		T199	12		T18	14
auto[0]	values[3]	values[0]	404	1			T17	10		T196	11		T185	11
auto[0]	values[3]	values[1]	295	1			T11	27		T31	12		T17	13
auto[0]	values[3]	values[2]	305	1			T99	10		T39	16		T18	11
auto[0]	values[3]	values[3]	308	1			T17	24		T197	57		T229	2
auto[0]	values[3]	values[4]	312	1			T6	10		T38	11		T185	7
auto[0]	values[3]	values[5]	311	1			T1	6		T3	11		T18	10
auto[0]	values[3]	values[6]	163	1			T11	16		T18	13		T19	16
auto[0]	values[3]	values[7]	214	1			T6	16		T150	2		T19	19
auto[0]	values[4]	values[0]	277	1			T3	25		T11	22		T31	9
auto[0]	values[4]	values[1]	445	1			T17	33		T18	106		T19	16
auto[0]	values[4]	values[2]	362	1			T3	9		T31	11		T39	6
auto[0]	values[4]	values[3]	291	1			T3	33		T11	11		T17	13
auto[0]	values[4]	values[4]	372	1			T8	68		T17	29		T177	10
auto[0]	values[4]	values[5]	344	1			T24	15		T39	13		T17	28
auto[0]	values[4]	values[6]	363	1			T24	14		T230	12		T231	13
auto[0]	values[4]	values[7]	204	1			T17	8		T142	9		T195	9
auto[0]	values[5]	values[0]	272	1			T6	12		T16	13		T39	12
auto[0]	values[5]	values[1]	412	1			T118	20		T39	13		T232	14
auto[0]	values[5]	values[2]	181	1			T11	8		T233	16		T38	14
auto[0]	values[5]	values[3]	389	1			T6	7		T24	27		T31	14
auto[0]	values[5]	values[4]	222	1			T11	10		T38	9		T187	14
auto[0]	values[5]	values[5]	345	1			T3	8		T11	14		T100	6
auto[0]	values[5]	values[6]	210	1			T6	9		T11	15		T178	16
auto[0]	values[5]	values[7]	261	1			T69	17		T234	5		T227	44
auto[0]	values[6]	values[0]	202	1			T189	29		T235	12		T202	17
auto[0]	values[6]	values[1]	371	1			T3	12		T6	7		T11	15
auto[0]	values[6]	values[2]	502	1			T8	23		T11	11		T213	10
auto[0]	values[6]	values[3]	174	1			T31	12		T18	13		T189	13
auto[0]	values[6]	values[4]	309	1			T11	17		T213	15		T189	11
auto[0]	values[6]	values[5]	185	1			T3	28		T187	10		T202	13
auto[0]	values[6]	values[6]	263	1			T36	4		T200	18		T18	11
auto[0]	values[6]	values[7]	384	1			T11	13		T16	7		T193	18
auto[0]	values[7]	values[0]	175	1			T236	20		T196	8		T69	16
auto[0]	values[7]	values[1]	329	1			T31	12		T38	8		T39	14
auto[0]	values[7]	values[2]	317	1			T3	16		T206	13		T187	30
auto[0]	values[7]	values[3]	344	1			T3	12		T6	10		T35	8
auto[0]	values[7]	values[4]	380	1			T11	13		T69	10		T176	40
auto[0]	values[7]	values[5]	548	1			T3	14		T24	24		T237	8
auto[0]	values[7]	values[6]	272	1			T8	12		T11	27		T24	15
auto[0]	values[7]	values[7]	308	1			T134	10		T238	14		T143	14
auto[1]	values[0]	values[0]	146	1			T6	9		T178	11		T142	6
auto[1]	values[0]	values[1]	331	1			T8	12		T31	12		T193	9
auto[1]	values[0]	values[2]	122	1			T31	8		T206	9		T196	13
auto[1]	values[0]	values[3]	170	1			T24	11		T16	9		T18	4
auto[1]	values[0]	values[4]	186	1			T11	7		T189	10		T239	10
auto[1]	values[0]	values[5]	160	1			T16	10		T38	5		T206	10
auto[1]	values[0]	values[6]	251	1			T142	68		T206	13		T202	11
auto[1]	values[0]	values[7]	355	1			T3	12		T17	8		T18	15
auto[1]	values[1]	values[0]	153	1			T39	7		T142	11		T195	7
auto[1]	values[1]	values[1]	175	1			T3	10		T18	5		T189	12
auto[1]	values[1]	values[2]	245	1			T6	12		T178	4		T206	7
auto[1]	values[1]	values[3]	176	1			T11	8		T39	6		T17	12
auto[1]	values[1]	values[4]	381	1			T6	7		T193	9		T119	9
auto[1]	values[1]	values[5]	140	1			T6	10		T11	12		T196	6
auto[1]	values[1]	values[6]	299	1			T8	6		T203	10		T69	22
auto[1]	values[1]	values[7]	236	1			T24	7		T31	7		T38	7
auto[1]	values[2]	values[0]	192	1			T142	19		T206	11		T225	12
auto[1]	values[2]	values[1]	96	1			T31	11		T226	13		T181	11
auto[1]	values[2]	values[2]	170	1			T6	10		T178	5		T187	10
auto[1]	values[2]	values[3]	131	1			T11	24		T38	9		T17	6
auto[1]	values[2]	values[4]	87	1			T240	2		T195	14		T197	11
auto[1]	values[2]	values[5]	132	1			T24	9		T18	11		T227	7
auto[1]	values[2]	values[6]	177	1			T11	26		T24	9		T241	6
auto[1]	values[2]	values[7]	217	1			T242	8		T18	69		T178	5
auto[1]	values[3]	values[0]	195	1			T17	10		T212	20		T196	9
auto[1]	values[3]	values[1]	159	1			T11	16		T31	8		T17	7
auto[1]	values[3]	values[2]	281	1			T39	10		T18	9		T19	16
auto[1]	values[3]	values[3]	167	1			T17	11		T197	8		T243	16
auto[1]	values[3]	values[4]	259	1			T6	10		T38	9		T185	13
auto[1]	values[3]	values[5]	96	1			T3	20		T18	10		T143	8
auto[1]	values[3]	values[6]	127	1			T11	8		T18	10		T19	7
auto[1]	values[3]	values[7]	107	1			T6	4		T19	10		T143	12
auto[1]	values[4]	values[0]	205	1			T3	5		T11	20		T31	11
auto[1]	values[4]	values[1]	288	1			T17	16		T18	11		T19	6
auto[1]	values[4]	values[2]	387	1			T3	11		T31	9		T39	14
auto[1]	values[4]	values[3]	273	1			T3	15		T11	9		T17	30
auto[1]	values[4]	values[4]	230	1			T8	9		T17	12		T178	11
auto[1]	values[4]	values[5]	202	1			T24	5		T39	15		T17	18
auto[1]	values[4]	values[6]	214	1			T24	26		T230	8		T231	59
auto[1]	values[4]	values[7]	174	1			T17	17		T142	11		T195	11
auto[1]	values[5]	values[0]	202	1			T6	8		T16	8		T39	8
auto[1]	values[5]	values[1]	160	1			T39	10		T213	8		T244	54
auto[1]	values[5]	values[2]	196	1			T11	12		T37	14		T38	6
auto[1]	values[5]	values[3]	242	1			T6	13		T24	5		T101	10
auto[1]	values[5]	values[4]	248	1			T11	10		T38	13		T187	6
auto[1]	values[5]	values[5]	385	1			T3	67		T11	9		T17	29
auto[1]	values[5]	values[6]	219	1			T6	11		T11	8		T178	11
auto[1]	values[5]	values[7]	151	1			T69	6		T245	16		T246	16
auto[1]	values[6]	values[0]	178	1			T189	5		T202	7		T247	10
auto[1]	values[6]	values[1]	127	1			T3	8		T6	13		T11	5
auto[1]	values[6]	values[2]	347	1			T8	5		T11	11		T213	17
auto[1]	values[6]	values[3]	191	1			T31	8		T18	9		T189	11
auto[1]	values[6]	values[4]	253	1			T11	7		T213	13		T189	10
auto[1]	values[6]	values[5]	260	1			T3	19		T187	10		T202	23
auto[1]	values[6]	values[6]	205	1			T18	17		T119	5		T206	12
auto[1]	values[6]	values[7]	198	1			T11	7		T16	13		T193	2
auto[1]	values[7]	values[0]	128	1			T196	15		T248	8		T69	9
auto[1]	values[7]	values[1]	271	1			T31	8		T38	13		T39	12
auto[1]	values[7]	values[2]	119	1			T3	4		T206	8		T187	7
auto[1]	values[7]	values[3]	364	1			T3	8		T6	10		T38	1
auto[1]	values[7]	values[4]	123	1			T11	7		T69	16		T176	3
auto[1]	values[7]	values[5]	196	1			T3	6		T24	5		T143	5
auto[1]	values[7]	values[6]	153	1			T8	12		T11	15		T24	5
auto[1]	values[7]	values[7]	228	1			T143	10		T69	7		T249	8