Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15740

1

T1

3

T3

172

T6

125

auto[1]

42542

1

T1

3

T2

240

T3

229

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1338	1			T2	10		T3	11		T4	3
auto[4:7]	22716	1			T2	34		T3	161		T6	17
auto[8:11]	1331	1			T2	3		T3	13		T4	3
auto[12:15]	354	1			T2	5		T3	4		T6	1
auto[16:19]	303	1			T3	2		T11	3		T24	3
auto[20:23]	1827	1			T2	12		T3	6		T6	9
auto[24:27]	312	1			T2	3		T3	3		T6	2
auto[28:31]	339	1			T2	3		T6	2		T11	1
auto[32:35]	342	1			T3	6		T6	2		T8	1
auto[36:39]	345	1			T2	3		T3	1		T6	3
auto[40:43]	348	1			T2	4		T3	1		T8	1
auto[44:47]	301	1			T3	9		T11	4		T35	2
auto[48:51]	308	1			T2	2		T3	2		T6	2
auto[52:55]	1804	1			T2	20		T3	10		T6	13
auto[56:59]	1386	1			T2	10		T3	9		T4	1
auto[60:63]	339	1			T3	2		T6	6		T11	3
auto[64:67]	319	1			T2	1		T3	2		T11	1
auto[68:71]	319	1			T2	9		T3	2		T6	2
auto[72:75]	298	1			T2	1		T3	1		T6	3
auto[76:79]	355	1			T2	2		T3	1		T6	4
auto[80:83]	269	1			T2	3		T6	2		T8	1
auto[84:87]	336	1			T3	3		T11	2		T24	3
auto[88:91]	1797	1			T2	13		T3	16		T6	5
auto[92:95]	349	1			T2	1		T6	2		T11	4
auto[96:99]	351	1			T2	2		T3	9		T6	1
auto[100:103]	295	1			T2	2		T8	2		T11	8
auto[104:107]	1293	1			T1	4		T2	3		T3	7
auto[108:111]	310	1			T2	2		T6	2		T8	1
auto[112:115]	318	1			T2	1		T3	1		T6	2
auto[116:119]	338	1			T2	4		T6	3		T8	1
auto[120:123]	326	1			T2	2		T6	4		T8	2
auto[124:127]	335	1			T2	1		T3	7		T8	6
auto[128:131]	322	1			T3	2		T6	4		T11	5
auto[132:135]	366	1			T3	1		T6	5		T8	1
auto[136:139]	311	1			T2	3		T3	4		T6	2
auto[140:143]	367	1			T3	1		T6	4		T24	2
auto[144:147]	364	1			T2	1		T3	4		T11	2
auto[148:151]	308	1			T2	4		T3	1		T6	1
auto[152:155]	311	1			T3	2		T8	2		T11	1
auto[156:159]	1779	1			T2	11		T3	18		T6	14
auto[160:163]	316	1			T2	4		T3	2		T6	1
auto[164:167]	319	1			T2	1		T3	3		T24	3
auto[168:171]	298	1			T3	1		T6	2		T8	2
auto[172:175]	330	1			T2	3		T3	3		T6	5
auto[176:179]	346	1			T6	1		T11	1		T24	1
auto[180:183]	1843	1			T2	2		T3	10		T6	3
auto[184:187]	1400	1			T2	5		T3	11		T6	12
auto[188:191]	314	1			T2	1		T11	6		T42	3
auto[192:195]	267	1			T3	3		T6	4		T11	2
auto[196:199]	330	1			T2	1		T3	4		T6	3
auto[200:203]	344	1			T2	7		T6	3		T8	1
auto[204:207]	300	1			T2	1		T3	1		T6	5
auto[208:211]	361	1			T2	2		T3	2		T6	2
auto[212:215]	342	1			T2	5		T6	4		T8	1
auto[216:219]	314	1			T2	1		T6	4		T11	1
auto[220:223]	307	1			T2	4		T3	4		T6	1
auto[224:227]	313	1			T2	3		T6	2		T8	2
auto[228:231]	302	1			T6	1		T11	4		T30	2
auto[232:235]	2865	1			T1	2		T2	14		T3	24
auto[236:239]	344	1			T2	3		T3	3		T6	1
auto[240:243]	354	1			T3	1		T11	4		T24	2
auto[244:247]	311	1			T2	1		T3	3		T6	1
auto[248:251]	324	1			T2	2		T6	6		T11	2
auto[252:255]	309	1			T2	5		T3	4		T6	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	462	1			T3	1		T6	9		T8	2
auto[0:3]	auto[1]	876	1			T2	10		T3	10		T4	3
auto[4:7]	auto[0]	5885	1			T3	42		T6	13		T7	4
auto[4:7]	auto[1]	16831	1			T2	34		T3	119		T6	4
auto[8:11]	auto[0]	500	1			T3	3		T6	8		T8	3
auto[8:11]	auto[1]	831	1			T2	3		T3	10		T4	3
auto[12:15]	auto[0]	75	1			T3	4		T11	4		T31	1
auto[12:15]	auto[1]	279	1			T2	5		T6	1		T8	2
auto[16:19]	auto[0]	61	1			T3	2		T11	1		T31	2
auto[16:19]	auto[1]	242	1			T11	2		T24	3		T26	3
auto[20:23]	auto[0]	453	1			T3	5		T6	5		T11	8
auto[20:23]	auto[1]	1374	1			T2	12		T3	1		T6	4
auto[24:27]	auto[0]	92	1			T3	1		T6	2		T24	1
auto[24:27]	auto[1]	220	1			T2	3		T3	2		T24	3
auto[28:31]	auto[0]	87	1			T11	1		T24	1		T31	3
auto[28:31]	auto[1]	252	1			T2	3		T6	2		T30	5
auto[32:35]	auto[0]	77	1			T3	5		T11	1		T17	2
auto[32:35]	auto[1]	265	1			T3	1		T6	2		T8	1
auto[36:39]	auto[0]	87	1			T6	3		T8	1		T11	1
auto[36:39]	auto[1]	258	1			T2	3		T3	1		T30	1
auto[40:43]	auto[0]	100	1			T3	1		T11	6		T24	1
auto[40:43]	auto[1]	248	1			T2	4		T8	1		T11	2
auto[44:47]	auto[0]	77	1			T11	2		T35	1		T18	2
auto[44:47]	auto[1]	224	1			T3	9		T11	2		T35	1
auto[48:51]	auto[0]	66	1			T3	2		T6	2		T8	1
auto[48:51]	auto[1]	242	1			T2	2		T11	1		T26	3
auto[52:55]	auto[0]	469	1			T3	2		T6	10		T7	2
auto[52:55]	auto[1]	1335	1			T2	20		T3	8		T6	3
auto[56:59]	auto[0]	474	1			T3	6		T6	3		T8	1
auto[56:59]	auto[1]	912	1			T2	10		T3	3		T4	1
auto[60:63]	auto[0]	101	1			T6	3		T11	2		T37	1
auto[60:63]	auto[1]	238	1			T3	2		T6	3		T11	1
auto[64:67]	auto[0]	92	1			T3	1		T39	1		T193	3
auto[64:67]	auto[1]	227	1			T2	1		T3	1		T11	1
auto[68:71]	auto[0]	81	1			T3	2		T6	1		T8	2
auto[68:71]	auto[1]	238	1			T2	9		T6	1		T8	1
auto[72:75]	auto[0]	56	1			T8	1		T11	2		T37	1
auto[72:75]	auto[1]	242	1			T2	1		T3	1		T6	3
auto[76:79]	auto[0]	81	1			T3	1		T6	2		T11	3
auto[76:79]	auto[1]	274	1			T2	2		T6	2		T11	1
auto[80:83]	auto[0]	69	1			T6	2		T24	1		T101	1
auto[80:83]	auto[1]	200	1			T2	3		T8	1		T11	2
auto[84:87]	auto[0]	103	1			T3	3		T11	1		T24	1
auto[84:87]	auto[1]	233	1			T11	1		T24	2		T26	1
auto[88:91]	auto[0]	487	1			T3	5		T7	2		T9	1
auto[88:91]	auto[1]	1310	1			T2	13		T3	11		T6	5
auto[92:95]	auto[0]	88	1			T11	3		T37	2		T31	2
auto[92:95]	auto[1]	261	1			T2	1		T6	2		T11	1
auto[96:99]	auto[0]	108	1			T3	7		T6	1		T11	4
auto[96:99]	auto[1]	243	1			T2	2		T3	2		T24	1
auto[100:103]	auto[0]	65	1			T8	2		T11	8		T16	1
auto[100:103]	auto[1]	230	1			T2	2		T30	1		T41	4
auto[104:107]	auto[0]	438	1			T1	2		T3	6		T6	4
auto[104:107]	auto[1]	855	1			T1	2		T2	3		T3	1
auto[108:111]	auto[0]	80	1			T6	1		T11	1		T31	1
auto[108:111]	auto[1]	230	1			T2	2		T6	1		T8	1
auto[112:115]	auto[0]	68	1			T17	1		T19	2		T250	1
auto[112:115]	auto[1]	250	1			T2	1		T3	1		T6	2
auto[116:119]	auto[0]	91	1			T6	1		T8	1		T11	4
auto[116:119]	auto[1]	247	1			T2	4		T6	2		T24	4
auto[120:123]	auto[0]	86	1			T8	1		T11	4		T118	1
auto[120:123]	auto[1]	240	1			T2	2		T6	4		T8	1
auto[124:127]	auto[0]	79	1			T3	7		T8	5		T11	5
auto[124:127]	auto[1]	256	1			T2	1		T8	1		T11	3
auto[128:131]	auto[0]	76	1			T3	2		T6	2		T11	2
auto[128:131]	auto[1]	246	1			T6	2		T11	3		T24	3
auto[132:135]	auto[0]	82	1			T3	1		T24	2		T31	1
auto[132:135]	auto[1]	284	1			T6	5		T8	1		T11	1
auto[136:139]	auto[0]	79	1			T3	3		T6	2		T8	2
auto[136:139]	auto[1]	232	1			T2	3		T3	1		T8	3
auto[140:143]	auto[0]	93	1			T3	1		T6	1		T24	1
auto[140:143]	auto[1]	274	1			T6	3		T24	1		T30	1
auto[144:147]	auto[0]	85	1			T3	2		T24	1		T31	2
auto[144:147]	auto[1]	279	1			T2	1		T3	2		T11	2
auto[148:151]	auto[0]	79	1			T3	1		T11	2		T24	1
auto[148:151]	auto[1]	229	1			T2	4		T6	1		T11	1
auto[152:155]	auto[0]	68	1			T3	1		T24	2		T38	1
auto[152:155]	auto[1]	243	1			T3	1		T8	2		T11	1
auto[156:159]	auto[0]	474	1			T3	7		T6	9		T8	1
auto[156:159]	auto[1]	1305	1			T2	11		T3	11		T6	5
auto[160:163]	auto[0]	66	1			T3	1		T11	3		T237	1
auto[160:163]	auto[1]	250	1			T2	4		T3	1		T6	1
auto[164:167]	auto[0]	76	1			T24	3		T31	1		T38	2
auto[164:167]	auto[1]	243	1			T2	1		T3	3		T26	1
auto[168:171]	auto[0]	76	1			T3	1		T6	1		T11	4
auto[168:171]	auto[1]	222	1			T6	1		T8	2		T24	1
auto[172:175]	auto[0]	72	1			T3	1		T6	4		T11	1
auto[172:175]	auto[1]	258	1			T2	3		T3	2		T6	1
auto[176:179]	auto[0]	78	1			T6	1		T31	1		T233	1
auto[176:179]	auto[1]	268	1			T11	1		T24	1		T26	1
auto[180:183]	auto[0]	496	1			T3	7		T6	2		T8	3
auto[180:183]	auto[1]	1347	1			T2	2		T3	3		T6	1
auto[184:187]	auto[0]	505	1			T3	7		T6	4		T8	1
auto[184:187]	auto[1]	895	1			T2	5		T3	4		T6	8
auto[188:191]	auto[0]	80	1			T11	2		T19	1		T119	2
auto[188:191]	auto[1]	234	1			T2	1		T11	4		T42	3
auto[192:195]	auto[0]	82	1			T3	3		T6	2		T11	2
auto[192:195]	auto[1]	185	1			T6	2		T42	2		T41	1
auto[196:199]	auto[0]	87	1			T3	2		T6	1		T8	2
auto[196:199]	auto[1]	243	1			T2	1		T3	2		T6	2
auto[200:203]	auto[0]	84	1			T6	3		T11	5		T24	1
auto[200:203]	auto[1]	260	1			T2	7		T8	1		T11	4
auto[204:207]	auto[0]	80	1			T3	1		T6	2		T8	2
auto[204:207]	auto[1]	220	1			T2	1		T6	3		T8	1
auto[208:211]	auto[0]	82	1			T3	1		T24	3		T101	2
auto[208:211]	auto[1]	279	1			T2	2		T3	1		T6	2
auto[212:215]	auto[0]	74	1			T6	3		T31	1		T18	1
auto[212:215]	auto[1]	268	1			T2	5		T6	1		T8	1
auto[216:219]	auto[0]	88	1			T6	2		T31	2		T38	2
auto[216:219]	auto[1]	226	1			T2	1		T6	2		T11	1
auto[220:223]	auto[0]	77	1			T24	1		T31	2		T39	2
auto[220:223]	auto[1]	230	1			T2	4		T3	4		T6	1
auto[224:227]	auto[0]	71	1			T6	2		T11	5		T24	1
auto[224:227]	auto[1]	242	1			T2	3		T8	2		T11	2
auto[228:231]	auto[0]	68	1			T11	2		T17	2		T211	2
auto[228:231]	auto[1]	234	1			T6	1		T11	2		T30	2
auto[232:235]	auto[0]	896	1			T1	1		T3	16		T6	8
auto[232:235]	auto[1]	1969	1			T1	1		T2	14		T3	8
auto[236:239]	auto[0]	76	1			T3	3		T6	1		T11	2
auto[236:239]	auto[1]	268	1			T2	3		T11	3		T30	2
auto[240:243]	auto[0]	81	1			T134	1		T31	1		T18	2
auto[240:243]	auto[1]	273	1			T3	1		T11	4		T24	2
auto[244:247]	auto[0]	89	1			T3	3		T6	1		T11	7
auto[244:247]	auto[1]	222	1			T2	1		T26	1		T42	1
auto[248:251]	auto[0]	86	1			T6	4		T11	1		T38	2
auto[248:251]	auto[1]	238	1			T2	2		T6	2		T11	1
auto[252:255]	auto[0]	96	1			T3	2		T11	7		T24	2
auto[252:255]	auto[1]	213	1			T2	5		T3	2		T6	3