Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	489	1			T1	6		T3	2		T6	5
auto[ReadAddrCrossIntoMailbox]	330	1			T3	5		T6	7		T8	6
auto[ReadAddrCrossOutOfMailbox]	345	1			T3	6		T6	3		T8	2
auto[ReadAddrCrossAllMailbox]	233	1			T3	3		T8	3		T11	3
auto[ReadAddrOutsideMailbox]	3697	1			T3	44		T6	41		T8	5

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2470

1

T1

3

T3

29

T6

27

auto[1]

2624

1

T1

3

T3

31

T6

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	846	1			T3	11		T6	12		T8	4
read_ops[0x0b]	835	1			T3	11		T6	11		T8	4
read_ops[0x3b]	842	1			T3	8		T6	8		T8	2
read_ops[0x6b]	820	1			T1	4		T3	7		T6	7
read_ops[0xbb]	885	1			T3	10		T6	11		T8	1
read_ops[0xeb]	866	1			T1	2		T3	13		T6	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T6	1		T24	1		T228	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T8	1		T11	2		T31	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T6	1		T8	2		T11	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T6	2		T8	1		T11	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T16	1		T39	1		T189	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	41	1			T3	1		T31	2		T39	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T17	1		T189	3		T251	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T3	1		T178	1		T202	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T3	1		T6	7		T11	7
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T3	8		T6	1		T11	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T6	1		T38	1		T39	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T11	2		T16	1		T17	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T6	1		T38	1		T17	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T3	2		T6	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T8	1		T11	2		T221	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T3	2		T16	1		T39	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T3	1		T8	1		T11	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T38	1		T207	1		T202	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T3	2		T6	5		T8	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	321	1			T3	4		T6	3		T8	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T31	1		T17	1		T119	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T6	1		T11	1		T17	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T24	1		T31	1		T17	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T6	1		T8	1		T11	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T17	1		T189	1		T203	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T3	1		T11	1		T142	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T17	1		T189	1		T203	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T8	1		T38	1		T176	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T3	5		T6	2		T11	8
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	320	1			T3	2		T6	4		T11	8
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T1	2		T9	2		T24	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T1	2		T6	1		T9	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T3	1		T39	2		T213	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T8	1		T11	1		T18	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T3	1		T6	1		T11	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T6	1		T8	1		T17	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T200	1		T142	1		T211	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T38	1		T200	1		T39	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T3	4		T6	1		T11	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T3	1		T6	3		T11	7
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T3	1		T11	2		T24	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T6	1		T11	1		T24	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T3	1		T6	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T200	1		T211	1		T252	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T3	1		T11	1		T24	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T11	1		T200	2		T196	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T3	1		T119	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T24	1		T31	1		T69	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	314	1			T3	3		T6	2		T8	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T3	3		T6	7		T9	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T1	1		T3	1		T11	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T1	1		T36	1		T24	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T3	1		T11	1		T39	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T8	1		T31	2		T17	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T6	1		T17	3		T213	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T11	2		T31	1		T17	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T11	1		T18	1		T142	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T8	1		T31	1		T39	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T3	5		T6	3		T11	8
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T3	6		T6	3		T8	2