Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4610	1			T3	40		T6	40		T11	23
values[1]	3909	1			T3	40		T6	20		T7	16
values[2]	3542	1			T1	6		T3	129		T6	60
values[3]	4256	1			T3	50		T6	20		T8	24
values[4]	3431	1			T3	47		T6	40		T11	44
values[5]	4403	1			T6	20		T11	66		T24	20
values[6]	3887	1			T3	75		T6	20		T8	20
values[7]	3403	1			T3	20		T6	20		T11	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3988	1			T3	40		T6	20		T11	20
values[1]	4577	1			T3	27		T6	60		T8	24
values[2]	3394	1			T3	98		T6	20		T7	16
values[3]	4490	1			T3	70		T6	20		T11	108
values[4]	3378	1			T1	6		T6	20		T8	20
values[5]	3719	1			T3	51		T6	40		T8	77
values[6]	3520	1			T3	75		T6	20		T11	64
values[7]	4375	1			T3	40		T6	40		T8	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30604

1

T1

6

T3

392

T6

231

auto[1]

837

1

T3

9

T6

9

T8

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	614	1			T3	18		T31	19		T38	21
auto[0]	values[0]	values[1]	668	1			T39	40		T17	39		T193	19
auto[0]	values[0]	values[2]	567	1			T36	4		T18	45		T213	25
auto[0]	values[0]	values[3]	600	1			T6	20		T11	22		T189	20
auto[0]	values[0]	values[4]	408	1			T189	21		T250	12		T253	195
auto[0]	values[0]	values[5]	624	1			T6	20		T17	20		T193	20
auto[0]	values[0]	values[6]	419	1			T193	14		T196	125		T254	10
auto[0]	values[0]	values[7]	562	1			T3	20		T16	20		T143	23
auto[0]	values[1]	values[0]	179	1			T19	20		T211	25		T255	14
auto[0]	values[1]	values[1]	604	1			T6	20		T31	17		T38	20
auto[0]	values[1]	values[2]	381	1			T7	16		T17	20		T256	12
auto[0]	values[1]	values[3]	407	1			T242	8		T17	21		T18	20
auto[0]	values[1]	values[4]	478	1			T24	70		T142	97		T224	2
auto[0]	values[1]	values[5]	630	1			T3	20		T8	76		T11	24
auto[0]	values[1]	values[6]	441	1			T11	21		T257	10		T206	23
auto[0]	values[1]	values[7]	678	1			T3	20		T11	19		T39	25
auto[0]	values[2]	values[0]	591	1			T19	33		T258	2		T211	20
auto[0]	values[2]	values[1]	327	1			T11	21		T24	20		T135	4
auto[0]	values[2]	values[2]	424	1			T3	74		T6	20		T8	27
auto[0]	values[2]	values[3]	455	1			T3	20		T11	15		T16	20
auto[0]	values[2]	values[4]	389	1			T1	6		T8	18		T11	40
auto[0]	values[2]	values[5]	414	1			T3	29		T6	17		T9	8
auto[0]	values[2]	values[6]	361	1			T6	19		T213	20		T202	34
auto[0]	values[2]	values[7]	477	1			T200	18		T222	6		T18	20
auto[0]	values[3]	values[0]	467	1			T3	20		T6	20		T11	17
auto[0]	values[3]	values[1]	836	1			T8	24		T48	6		T233	16
auto[0]	values[3]	values[2]	496	1			T11	44		T187	20		T196	30
auto[0]	values[3]	values[3]	561	1			T3	29		T31	20		T193	19
auto[0]	values[3]	values[4]	446	1			T17	20		T18	20		T238	14
auto[0]	values[3]	values[5]	603	1			T11	42		T24	22		T207	6
auto[0]	values[3]	values[6]	252	1			T39	20		T189	21		T197	63
auto[0]	values[3]	values[7]	479	1			T11	40		T134	10		T100	6
auto[0]	values[4]	values[0]	777	1			T37	10		T24	20		T18	20
auto[0]	values[4]	values[1]	450	1			T3	27		T6	20		T11	40
auto[0]	values[4]	values[2]	246	1			T3	20		T13	6		T259	10
auto[0]	values[4]	values[3]	338	1			T220	6		T16	24		T17	27
auto[0]	values[4]	values[4]	466	1			T6	18		T17	20		T18	20
auto[0]	values[4]	values[5]	231	1			T31	19		T206	20		T196	22
auto[0]	values[4]	values[6]	390	1			T196	50		T202	48		T185	20
auto[0]	values[4]	values[7]	429	1			T241	6		T178	20		T189	20
auto[0]	values[5]	values[0]	473	1			T142	20		T181	40		T260	18
auto[0]	values[5]	values[1]	508	1			T118	20		T193	20		T178	20
auto[0]	values[5]	values[2]	616	1			T11	20		T142	20		T143	20
auto[0]	values[5]	values[3]	682	1			T11	21		T38	21		T213	20
auto[0]	values[5]	values[4]	526	1			T31	37		T150	2		T38	20
auto[0]	values[5]	values[5]	381	1			T261	2		T225	21		T230	78
auto[0]	values[5]	values[6]	501	1			T11	22		T262	18		T196	55
auto[0]	values[5]	values[7]	633	1			T6	20		T24	20		T17	25
auto[0]	values[6]	values[0]	404	1			T16	20		T178	23		T143	48
auto[0]	values[6]	values[1]	722	1			T6	19		T24	31		T178	24
auto[0]	values[6]	values[2]	202	1			T17	20		T206	21		T82	20
auto[0]	values[6]	values[3]	952	1			T11	20		T31	39		T18	83
auto[0]	values[6]	values[4]	227	1			T199	12		T194	4		T206	26
auto[0]	values[6]	values[5]	410	1			T11	26		T24	29		T19	50
auto[0]	values[6]	values[6]	485	1			T3	75		T11	19		T24	20
auto[0]	values[6]	values[7]	393	1			T8	20		T101	10		T196	18
auto[0]	values[7]	values[0]	378	1			T50	8		T237	8		T142	20
auto[0]	values[7]	values[1]	332	1			T219	8		T196	20		T82	20
auto[0]	values[7]	values[2]	368	1			T17	24		T19	23		T178	24
auto[0]	values[7]	values[3]	378	1			T3	20		T11	20		T38	23
auto[0]	values[7]	values[4]	344	1			T195	20		T239	20		T230	20
auto[0]	values[7]	values[5]	327	1			T99	10		T39	26		T17	20
auto[0]	values[7]	values[6]	581	1			T35	8		T228	2		T39	20
auto[0]	values[7]	values[7]	616	1			T6	18		T211	24		T203	24
auto[1]	values[0]	values[0]	16	1			T3	2		T31	1		T38	1
auto[1]	values[0]	values[1]	27	1			T39	1		T17	1		T193	1
auto[1]	values[0]	values[2]	19	1			T18	3		T213	2		T185	1
auto[1]	values[0]	values[3]	17	1			T11	1		T189	1		T263	1
auto[1]	values[0]	values[4]	16	1			T189	1		T231	6		T264	1
auto[1]	values[0]	values[5]	11	1			T265	2		T266	1		T267	3
auto[1]	values[0]	values[6]	19	1			T193	6		T196	3		T185	3
auto[1]	values[0]	values[7]	23	1			T143	3		T187	2		T216	3
auto[1]	values[1]	values[0]	7	1			T211	1		T255	2		T268	1
auto[1]	values[1]	values[1]	18	1			T31	3		T38	1		T178	1
auto[1]	values[1]	values[2]	11	1			T256	2		T244	5		T269	2
auto[1]	values[1]	values[3]	8	1			T19	2		T212	4		T270	1
auto[1]	values[1]	values[4]	13	1			T142	2		T181	1		T176	2
auto[1]	values[1]	values[5]	18	1			T8	1		T119	1		T82	2
auto[1]	values[1]	values[6]	12	1			T69	1		T230	1		T271	3
auto[1]	values[1]	values[7]	24	1			T11	1		T39	1		T193	1
auto[1]	values[2]	values[0]	15	1			T19	1		T231	3		T183	2
auto[1]	values[2]	values[1]	9	1			T11	3		T17	1		T272	1
auto[1]	values[2]	values[2]	19	1			T3	4		T8	1		T31	2
auto[1]	values[2]	values[3]	17	1			T11	7		T16	1		T18	1
auto[1]	values[2]	values[4]	10	1			T8	2		T234	1		T273	4
auto[1]	values[2]	values[5]	15	1			T3	2		T6	3		T178	1
auto[1]	values[2]	values[6]	9	1			T6	1		T202	2		T209	2
auto[1]	values[2]	values[7]	10	1			T189	2		T69	1		T263	2
auto[1]	values[3]	values[0]	16	1			T11	3		T189	4		T225	2
auto[1]	values[3]	values[1]	19	1			T193	1		T213	4		T187	2
auto[1]	values[3]	values[2]	10	1			T11	1		T196	1		T249	1
auto[1]	values[3]	values[3]	16	1			T3	1		T193	1		T142	1
auto[1]	values[3]	values[4]	13	1			T234	2		T266	2		T274	3
auto[1]	values[3]	values[5]	21	1			T11	2		T195	2		T82	2
auto[1]	values[3]	values[6]	8	1			T197	2		T234	1		T272	2
auto[1]	values[3]	values[7]	13	1			T166	1		T197	1		T149	3
auto[1]	values[4]	values[0]	25	1			T37	4		T185	2		T69	3
auto[1]	values[4]	values[1]	17	1			T11	4		T69	2		T272	3
auto[1]	values[4]	values[2]	7	1			T18	2		T82	3		T275	2
auto[1]	values[4]	values[3]	8	1			T17	2		T149	3		T267	3
auto[1]	values[4]	values[4]	10	1			T6	2		T202	2		T176	1
auto[1]	values[4]	values[5]	13	1			T31	1		T196	1		T82	1
auto[1]	values[4]	values[6]	14	1			T196	2		T202	1		T69	2
auto[1]	values[4]	values[7]	10	1			T143	1		T276	2		T239	2
auto[1]	values[5]	values[0]	9	1			T260	2		T277	1		T45	2
auto[1]	values[5]	values[1]	12	1			T189	1		T181	3		T225	1
auto[1]	values[5]	values[2]	13	1			T206	3		T69	1		T176	1
auto[1]	values[5]	values[3]	13	1			T11	2		T38	1		T249	1
auto[1]	values[5]	values[4]	13	1			T31	3		T17	3		T189	1
auto[1]	values[5]	values[5]	4	1			T230	2		T274	2		-	-
auto[1]	values[5]	values[6]	9	1			T11	1		T196	1		T176	1
auto[1]	values[5]	values[7]	10	1			T17	1		T267	3		T278	2
auto[1]	values[6]	values[0]	14	1			T16	1		T143	1		T196	1
auto[1]	values[6]	values[1]	17	1			T6	1		T24	1		T178	3
auto[1]	values[6]	values[2]	6	1			T246	6		-	-		-	-
auto[1]	values[6]	values[3]	19	1			T31	1		T19	2		T213	4
auto[1]	values[6]	values[4]	8	1			T176	2		T279	1		T271	1
auto[1]	values[6]	values[5]	10	1			T19	1		T187	1		T266	1
auto[1]	values[6]	values[6]	8	1			T11	1		T39	1		T82	1
auto[1]	values[6]	values[7]	10	1			T196	2		T202	1		T234	2
auto[1]	values[7]	values[0]	3	1			T234	1		T176	1		T280	1
auto[1]	values[7]	values[1]	11	1			T266	1		T281	6		T46	1
auto[1]	values[7]	values[2]	9	1			T176	2		T243	2		T282	2
auto[1]	values[7]	values[3]	19	1			T243	4		T279	2		T283	7
auto[1]	values[7]	values[4]	11	1			T284	2		T260	2		T192	3
auto[1]	values[7]	values[5]	7	1			T244	1		T285	1		T283	5
auto[1]	values[7]	values[6]	11	1			T18	1		T189	1		T211	3
auto[1]	values[7]	values[7]	8	1			T6	2		T249	1		T176	1