Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	767	1			T3	14		T12	20		T15	7
all_values[1]	767	1			T3	14		T12	20		T15	7
all_values[2]	767	1			T3	14		T12	20		T15	7
all_values[3]	767	1			T3	14		T12	20		T15	7
all_values[4]	767	1			T3	14		T12	20		T15	7
all_values[5]	767	1			T3	14		T12	20		T15	7
all_values[6]	767	1			T3	14		T12	20		T15	7
all_values[7]	767	1			T3	14		T12	20		T15	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3190

1

T3

55

T12

67

T15

27

auto[1]

2946

1

T3

57

T12

93

T15

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2478

1

T3

48

T12

71

T15

18

auto[1]

3658

1

T3

64

T12

89

T15

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3511

1

T3

66

T12

94

T15

30

auto[1]

2625

1

T3

46

T12

66

T15

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	149	1			T3	2		T12	2		T15	2
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T3	2		T12	1		T15	2
all_values[0]	auto[0]	auto[1]	auto[0]	126	1			T3	5		T12	4		T16	4
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T12	2		T16	3		T19	1
all_values[0]	auto[1]	auto[0]	auto[1]	164	1			T3	2		T12	1		T15	2
all_values[0]	auto[1]	auto[1]	auto[1]	173	1			T3	3		T12	10		T15	1
all_values[1]	auto[0]	auto[0]	auto[0]	127	1			T3	2		T12	1		T16	4
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T12	2		T15	2		T19	1
all_values[1]	auto[0]	auto[1]	auto[0]	152	1			T3	4		T12	5		T16	4
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T3	1		T12	4		T16	1
all_values[1]	auto[1]	auto[0]	auto[1]	182	1			T3	4		T12	4		T15	2
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T3	3		T12	4		T15	3
all_values[2]	auto[0]	auto[0]	auto[0]	147	1			T3	2		T12	5		T15	4
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T3	1		T12	1		T16	1
all_values[2]	auto[0]	auto[1]	auto[0]	132	1			T3	2		T12	7		T16	3
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T3	1		T12	1		T15	1
all_values[2]	auto[1]	auto[0]	auto[1]	184	1			T3	5		T12	5		T15	1
all_values[2]	auto[1]	auto[1]	auto[1]	156	1			T3	3		T12	1		T15	1
all_values[3]	auto[0]	auto[0]	auto[0]	165	1			T3	5		T12	1		T16	2
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T3	1		T12	1		T15	1
all_values[3]	auto[0]	auto[1]	auto[0]	134	1			T3	2		T12	7		T16	3
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T3	2		T12	2		T15	2
all_values[3]	auto[1]	auto[0]	auto[1]	173	1			T3	4		T12	3		T15	1
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T12	6		T15	3		T16	3
all_values[4]	auto[0]	auto[0]	auto[0]	154	1			T3	2		T12	5		T15	1
all_values[4]	auto[0]	auto[0]	auto[1]	63	1			T3	1		T12	1		T19	2
all_values[4]	auto[0]	auto[1]	auto[0]	152	1			T3	3		T12	4		T15	2
all_values[4]	auto[0]	auto[1]	auto[1]	70	1			T3	2		T12	2		T142	2
all_values[4]	auto[1]	auto[0]	auto[1]	159	1			T3	2		T12	3		T15	1
all_values[4]	auto[1]	auto[1]	auto[1]	169	1			T3	4		T12	5		T15	3
all_values[5]	auto[0]	auto[0]	auto[0]	250	1			T3	5		T12	6		T15	2
all_values[5]	auto[0]	auto[1]	auto[0]	198	1			T3	5		T12	5		T15	1
all_values[5]	auto[1]	auto[0]	auto[1]	169	1			T3	2		T12	5		T15	2
all_values[5]	auto[1]	auto[1]	auto[1]	150	1			T3	2		T12	4		T15	2
all_values[6]	auto[0]	auto[0]	auto[0]	138	1			T3	2		T12	3		T16	2
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T3	4		T12	2		T15	2
all_values[6]	auto[0]	auto[1]	auto[0]	147	1			T12	5		T15	1		T16	4
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T3	1		T12	1		T15	1
all_values[6]	auto[1]	auto[0]	auto[1]	166	1			T3	3		T12	6		T15	2
all_values[6]	auto[1]	auto[1]	auto[1]	151	1			T3	4		T12	3		T15	1
all_values[7]	auto[0]	auto[0]	auto[0]	163	1			T3	1		T12	5		T16	7
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T3	1		T12	1		T19	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T3	6		T12	6		T15	5
all_values[7]	auto[0]	auto[1]	auto[1]	70	1			T3	1		T12	2		T15	1
all_values[7]	auto[1]	auto[0]	auto[1]	185	1			T3	2		T12	3		T16	4
all_values[7]	auto[1]	auto[1]	auto[1]	135	1			T3	3		T12	3		T15	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal