Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1928

1

T3

2

T5

2

T11

20

auto[1]

1804

1

T3

6

T11

15

T14

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2091

1

T3

8

T5

2

T11

28

auto[1]

1641

1

T11

7

T14

4

T25

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2936

1

T3

7

T11

25

T14

4

auto[1]

796

1

T3

1

T5

2

T11

10

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	729	1			T3	3		T11	6		T14	1
valid[1]	741	1			T3	1		T11	5		T24	3
valid[2]	739	1			T3	2		T5	1		T11	7
valid[3]	758	1			T3	1		T5	1		T11	9
valid[4]	765	1			T3	1		T11	8		T24	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	124	1			T11	3		T24	1		T26	1
auto[0]	auto[0]	valid[0]	auto[1]	161	1			T28	2		T41	2		T78	1
auto[0]	auto[0]	valid[1]	auto[0]	121	1			T11	2		T24	1		T41	2
auto[0]	auto[0]	valid[1]	auto[1]	188	1			T28	2		T77	1		T155	1
auto[0]	auto[0]	valid[2]	auto[0]	132	1			T3	1		T11	2		T49	5
auto[0]	auto[0]	valid[2]	auto[1]	176	1			T11	1		T14	1		T25	1
auto[0]	auto[0]	valid[3]	auto[0]	133	1			T3	1		T11	1		T24	1
auto[0]	auto[0]	valid[3]	auto[1]	169	1			T11	2		T28	1		T80	1
auto[0]	auto[0]	valid[4]	auto[0]	154	1			T11	1		T41	1		T49	3
auto[0]	auto[0]	valid[4]	auto[1]	194	1			T11	3		T25	1		T41	1
auto[0]	auto[1]	valid[0]	auto[0]	134	1			T3	3		T11	1		T24	2
auto[0]	auto[1]	valid[0]	auto[1]	141	1			T14	1		T79	1		T17	1
auto[0]	auto[1]	valid[1]	auto[0]	129	1			T3	1		T11	1		T24	1
auto[0]	auto[1]	valid[1]	auto[1]	149	1			T11	1		T25	2		T28	2
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T3	1		T11	3		T24	2
auto[0]	auto[1]	valid[2]	auto[1]	137	1			T14	1		T300	1		T307	1
auto[0]	auto[1]	valid[3]	auto[0]	130	1			T11	2		T24	1		T49	3
auto[0]	auto[1]	valid[3]	auto[1]	169	1			T14	1		T17	1		T308	2
auto[0]	auto[1]	valid[4]	auto[0]	118	1			T11	2		T26	1		T153	1
auto[0]	auto[1]	valid[4]	auto[1]	157	1			T25	1		T28	1		T307	1
auto[1]	auto[0]	valid[0]	auto[0]	77	1			T49	1		T16	1		T39	1
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T11	1		T71	1		T16	1
auto[1]	auto[0]	valid[2]	auto[0]	79	1			T5	1		T41	1		T71	1
auto[1]	auto[0]	valid[3]	auto[0]	71	1			T5	1		T11	3		T41	1
auto[1]	auto[0]	valid[4]	auto[0]	68	1			T11	1		T24	2		T41	1
auto[1]	auto[1]	valid[0]	auto[0]	92	1			T11	2		T24	2		T26	1
auto[1]	auto[1]	valid[1]	auto[0]	73	1			T24	1		T41	1		T49	1
auto[1]	auto[1]	valid[2]	auto[0]	95	1			T11	1		T24	1		T16	2
auto[1]	auto[1]	valid[3]	auto[0]	86	1			T11	1		T41	2		T49	2
auto[1]	auto[1]	valid[4]	auto[0]	74	1			T3	1		T11	1		T49	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal