Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51650

1

T3

421

T5

118

T10

8

auto[1]

18112

1

T11

149

T14

4

T25

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51045

1

T3

277

T5

70

T10

4

auto[1]

18717

1

T3

144

T5

48

T10

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35954	1			T3	237		T5	62		T10	3
others[1]	6039	1			T3	40		T5	11		T11	85
others[2]	5890	1			T3	34		T5	7		T10	1
others[3]	6565	1			T3	27		T5	14		T11	78
interest[1]	3825	1			T3	15		T5	9		T10	2
interest[4]	23452	1			T3	143		T5	41		T10	2
interest[64]	11489	1			T3	68		T5	15		T10	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16846	1			T3	158		T5	37		T10	2
auto[0]	auto[0]	others[1]	2937	1			T3	27		T5	8		T11	37
auto[0]	auto[0]	others[2]	2719	1			T3	21		T5	4		T11	37
auto[0]	auto[0]	others[3]	3114	1			T3	17		T5	8		T11	36
auto[0]	auto[0]	interest[1]	1866	1			T3	9		T5	7		T11	26
auto[0]	auto[0]	interest[4]	10935	1			T3	95		T5	24		T10	1
auto[0]	auto[0]	interest[64]	5451	1			T3	45		T5	6		T10	2
auto[0]	auto[1]	others[0]	9446	1			T11	72		T14	4		T25	5
auto[0]	auto[1]	others[1]	1522	1			T11	16		T28	8		T41	5
auto[0]	auto[1]	others[2]	1541	1			T11	17		T28	12		T41	6
auto[0]	auto[1]	others[3]	1690	1			T11	11		T28	12		T41	6
auto[0]	auto[1]	interest[1]	972	1			T11	6		T28	9		T41	6
auto[0]	auto[1]	interest[4]	6193	1			T11	51		T14	4		T25	5
auto[0]	auto[1]	interest[64]	2941	1			T11	27		T28	17		T41	5
auto[1]	auto[0]	others[0]	9662	1			T3	79		T5	25		T10	1
auto[1]	auto[0]	others[1]	1580	1			T3	13		T5	3		T11	32
auto[1]	auto[0]	others[2]	1630	1			T3	13		T5	3		T10	1
auto[1]	auto[0]	others[3]	1761	1			T3	10		T5	6		T11	31
auto[1]	auto[0]	interest[1]	987	1			T3	6		T5	2		T10	2
auto[1]	auto[0]	interest[4]	6324	1			T3	48		T5	17		T10	1
auto[1]	auto[0]	interest[64]	3097	1			T3	23		T5	9		T11	31

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal