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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
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T156 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2699725836 Aug 07 06:24:04 PM PDT 24 Aug 07 06:24:24 PM PDT 24 299639032 ps
T89 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2427640127 Aug 07 06:24:23 PM PDT 24 Aug 07 06:24:25 PM PDT 24 70781521 ps
T108 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1595213983 Aug 07 06:24:18 PM PDT 24 Aug 07 06:24:45 PM PDT 24 22616210186 ps
T1029 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1789089032 Aug 07 06:24:32 PM PDT 24 Aug 07 06:24:33 PM PDT 24 122322039 ps
T1030 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1053556119 Aug 07 06:24:37 PM PDT 24 Aug 07 06:24:38 PM PDT 24 75981702 ps
T109 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4009743122 Aug 07 06:24:10 PM PDT 24 Aug 07 06:24:11 PM PDT 24 161049337 ps
T1031 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.889995790 Aug 07 06:24:33 PM PDT 24 Aug 07 06:24:35 PM PDT 24 260279149 ps
T140 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3914026739 Aug 07 06:24:06 PM PDT 24 Aug 07 06:24:08 PM PDT 24 50023126 ps
T110 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3169765799 Aug 07 06:24:08 PM PDT 24 Aug 07 06:24:29 PM PDT 24 308242804 ps
T161 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1414666211 Aug 07 06:24:10 PM PDT 24 Aug 07 06:24:26 PM PDT 24 574637955 ps
T111 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1090196260 Aug 07 06:24:25 PM PDT 24 Aug 07 06:24:28 PM PDT 24 34971899 ps
T141 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1507327544 Aug 07 06:24:08 PM PDT 24 Aug 07 06:24:24 PM PDT 24 4320156240 ps
T91 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1951207606 Aug 07 06:24:22 PM PDT 24 Aug 07 06:24:25 PM PDT 24 164456568 ps
T1032 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1962992675 Aug 07 06:24:17 PM PDT 24 Aug 07 06:24:20 PM PDT 24 54485634 ps
T74 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1042123046 Aug 07 06:24:17 PM PDT 24 Aug 07 06:24:18 PM PDT 24 121392078 ps
T1033 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1325469659 Aug 07 06:24:37 PM PDT 24 Aug 07 06:24:38 PM PDT 24 24475784 ps
T1034 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1775966635 Aug 07 06:24:40 PM PDT 24 Aug 07 06:24:40 PM PDT 24 28375148 ps
T112 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2778670375 Aug 07 06:24:13 PM PDT 24 Aug 07 06:24:16 PM PDT 24 611433599 ps
T1035 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2359354867 Aug 07 06:24:13 PM PDT 24 Aug 07 06:24:15 PM PDT 24 110225649 ps
T1036 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2606444512 Aug 07 06:24:19 PM PDT 24 Aug 07 06:24:21 PM PDT 24 29729002 ps
T152 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2869964317 Aug 07 06:24:11 PM PDT 24 Aug 07 06:24:31 PM PDT 24 3743710124 ps
T162 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3518154776 Aug 07 06:24:29 PM PDT 24 Aug 07 06:24:36 PM PDT 24 2680938041 ps
T1037 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2921847708 Aug 07 06:24:03 PM PDT 24 Aug 07 06:24:05 PM PDT 24 354295314 ps
T1038 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1956905920 Aug 07 06:24:23 PM PDT 24 Aug 07 06:24:25 PM PDT 24 110045124 ps
T90 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1421987314 Aug 07 06:24:07 PM PDT 24 Aug 07 06:24:13 PM PDT 24 87934728 ps
T1039 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3408490351 Aug 07 06:24:09 PM PDT 24 Aug 07 06:24:10 PM PDT 24 10862186 ps
T95 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1495630946 Aug 07 06:24:13 PM PDT 24 Aug 07 06:24:17 PM PDT 24 134034979 ps
T1040 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.260416932 Aug 07 06:24:44 PM PDT 24 Aug 07 06:24:45 PM PDT 24 20957494 ps
T1041 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1295592849 Aug 07 06:24:30 PM PDT 24 Aug 07 06:24:31 PM PDT 24 27798090 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3456421952 Aug 07 06:24:09 PM PDT 24 Aug 07 06:24:13 PM PDT 24 150083599 ps
T1043 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4085493719 Aug 07 06:24:15 PM PDT 24 Aug 07 06:24:16 PM PDT 24 17701936 ps
T1044 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4060980476 Aug 07 06:24:18 PM PDT 24 Aug 07 06:24:19 PM PDT 24 22439656 ps
T1045 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3177231848 Aug 07 06:24:20 PM PDT 24 Aug 07 06:24:28 PM PDT 24 276163679 ps
T1046 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2308277295 Aug 07 06:24:29 PM PDT 24 Aug 07 06:24:30 PM PDT 24 27932902 ps
T158 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3577481301 Aug 07 06:24:20 PM PDT 24 Aug 07 06:24:34 PM PDT 24 3782832868 ps
T1047 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2421575768 Aug 07 06:24:02 PM PDT 24 Aug 07 06:24:04 PM PDT 24 209382026 ps
T113 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1174346701 Aug 07 06:24:13 PM PDT 24 Aug 07 06:24:14 PM PDT 24 70353507 ps
T114 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3060032992 Aug 07 06:24:06 PM PDT 24 Aug 07 06:24:08 PM PDT 24 57325147 ps
T1048 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2584075029 Aug 07 06:24:17 PM PDT 24 Aug 07 06:24:20 PM PDT 24 27595821 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1892427796 Aug 07 06:24:19 PM PDT 24 Aug 07 06:24:21 PM PDT 24 249204654 ps
T75 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2028847615 Aug 07 06:24:02 PM PDT 24 Aug 07 06:24:04 PM PDT 24 557175834 ps
T93 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3527003503 Aug 07 06:24:19 PM PDT 24 Aug 07 06:24:24 PM PDT 24 72687799 ps
T1050 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.21886769 Aug 07 06:24:30 PM PDT 24 Aug 07 06:24:34 PM PDT 24 220807767 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.569624539 Aug 07 06:24:04 PM PDT 24 Aug 07 06:24:07 PM PDT 24 171221799 ps
T1052 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3609277980 Aug 07 06:24:10 PM PDT 24 Aug 07 06:24:10 PM PDT 24 17526535 ps
T1053 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1356371621 Aug 07 06:24:33 PM PDT 24 Aug 07 06:24:34 PM PDT 24 95990606 ps
T1054 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3314799319 Aug 07 06:24:29 PM PDT 24 Aug 07 06:24:30 PM PDT 24 15563209 ps
T1055 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2451941626 Aug 07 06:24:32 PM PDT 24 Aug 07 06:24:33 PM PDT 24 50499681 ps
T1056 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1597635162 Aug 07 06:24:11 PM PDT 24 Aug 07 06:24:13 PM PDT 24 29666937 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1515088466 Aug 07 06:24:11 PM PDT 24 Aug 07 06:24:12 PM PDT 24 67093971 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.780006138 Aug 07 06:24:06 PM PDT 24 Aug 07 06:24:20 PM PDT 24 1389329964 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.212600766 Aug 07 06:24:20 PM PDT 24 Aug 07 06:24:22 PM PDT 24 165662496 ps
T1060 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3859884352 Aug 07 06:24:13 PM PDT 24 Aug 07 06:24:21 PM PDT 24 1358825980 ps
T1061 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3300473078 Aug 07 06:24:30 PM PDT 24 Aug 07 06:24:30 PM PDT 24 13372243 ps
T1062 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3927055106 Aug 07 06:24:17 PM PDT 24 Aug 07 06:24:19 PM PDT 24 253898254 ps
T1063 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1744233663 Aug 07 06:24:33 PM PDT 24 Aug 07 06:24:34 PM PDT 24 12277950 ps
T1064 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2722581387 Aug 07 06:24:18 PM PDT 24 Aug 07 06:24:21 PM PDT 24 139500233 ps
T1065 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3724213322 Aug 07 06:24:19 PM PDT 24 Aug 07 06:24:20 PM PDT 24 61555496 ps
T1066 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1557304863 Aug 07 06:24:31 PM PDT 24 Aug 07 06:24:35 PM PDT 24 591864803 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2543281651 Aug 07 06:24:22 PM PDT 24 Aug 07 06:24:27 PM PDT 24 584749279 ps
T1068 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.303361763 Aug 07 06:24:34 PM PDT 24 Aug 07 06:24:38 PM PDT 24 136714230 ps
T157 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2004253013 Aug 07 06:24:09 PM PDT 24 Aug 07 06:24:29 PM PDT 24 831662676 ps
T1069 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4214389738 Aug 07 06:24:32 PM PDT 24 Aug 07 06:24:33 PM PDT 24 36016990 ps
T1070 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2783583460 Aug 07 06:24:29 PM PDT 24 Aug 07 06:24:32 PM PDT 24 401240268 ps
T1071 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1428279048 Aug 07 06:24:13 PM PDT 24 Aug 07 06:24:14 PM PDT 24 38968677 ps
T1072 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1800062862 Aug 07 06:24:29 PM PDT 24 Aug 07 06:24:30 PM PDT 24 22658147 ps
T1073 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.582150422 Aug 07 06:24:11 PM PDT 24 Aug 07 06:24:15 PM PDT 24 563682950 ps
T94 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.681463692 Aug 07 06:24:36 PM PDT 24 Aug 07 06:24:42 PM PDT 24 692569515 ps
T1074 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.795524350 Aug 07 06:24:41 PM PDT 24 Aug 07 06:24:42 PM PDT 24 15810558 ps
T1075 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.909757439 Aug 07 06:24:36 PM PDT 24 Aug 07 06:24:37 PM PDT 24 11612558 ps
T1076 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4066984321 Aug 07 06:24:21 PM PDT 24 Aug 07 06:24:26 PM PDT 24 325940845 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3840420888 Aug 07 06:24:19 PM PDT 24 Aug 07 06:24:21 PM PDT 24 191917938 ps
T1078 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.55490951 Aug 07 06:24:21 PM PDT 24 Aug 07 06:24:24 PM PDT 24 168101084 ps
T1079 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1251807836 Aug 07 06:24:09 PM PDT 24 Aug 07 06:24:13 PM PDT 24 430481386 ps
T1080 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3562062122 Aug 07 06:24:15 PM PDT 24 Aug 07 06:24:17 PM PDT 24 123351199 ps
T163 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2785643116 Aug 07 06:24:12 PM PDT 24 Aug 07 06:24:26 PM PDT 24 759234844 ps
T1081 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3614613155 Aug 07 06:24:29 PM PDT 24 Aug 07 06:24:30 PM PDT 24 11479915 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.199054798 Aug 07 06:24:08 PM PDT 24 Aug 07 06:24:11 PM PDT 24 301739866 ps
T1083 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2885433156 Aug 07 06:24:10 PM PDT 24 Aug 07 06:24:12 PM PDT 24 82487816 ps
T1084 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3979197827 Aug 07 06:24:30 PM PDT 24 Aug 07 06:24:31 PM PDT 24 35840215 ps
T76 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.372048268 Aug 07 06:24:12 PM PDT 24 Aug 07 06:24:13 PM PDT 24 418195561 ps
T1085 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.819653781 Aug 07 06:24:24 PM PDT 24 Aug 07 06:24:25 PM PDT 24 28686812 ps
T1086 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.738989951 Aug 07 06:24:35 PM PDT 24 Aug 07 06:24:36 PM PDT 24 45677762 ps
T1087 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.988116330 Aug 07 06:24:22 PM PDT 24 Aug 07 06:24:24 PM PDT 24 260117285 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.762616117 Aug 07 06:24:06 PM PDT 24 Aug 07 06:24:18 PM PDT 24 828308160 ps
T164 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1038827814 Aug 07 06:24:19 PM PDT 24 Aug 07 06:24:31 PM PDT 24 709673774 ps
T1089 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1043604623 Aug 07 06:24:31 PM PDT 24 Aug 07 06:24:32 PM PDT 24 28790907 ps
T1090 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.305530323 Aug 07 06:24:17 PM PDT 24 Aug 07 06:24:21 PM PDT 24 1086151094 ps
T1091 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3361703935 Aug 07 06:24:25 PM PDT 24 Aug 07 06:24:28 PM PDT 24 823884477 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3710469374 Aug 07 06:24:19 PM PDT 24 Aug 07 06:24:20 PM PDT 24 40304283 ps
T1093 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4160536565 Aug 07 06:24:42 PM PDT 24 Aug 07 06:24:43 PM PDT 24 53173324 ps
T1094 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.799524677 Aug 07 06:24:29 PM PDT 24 Aug 07 06:24:32 PM PDT 24 105967591 ps
T159 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3770840029 Aug 07 06:24:26 PM PDT 24 Aug 07 06:24:39 PM PDT 24 1804980176 ps
T1095 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4149209486 Aug 07 06:24:15 PM PDT 24 Aug 07 06:24:17 PM PDT 24 63676036 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2638940067 Aug 07 06:24:20 PM PDT 24 Aug 07 06:24:21 PM PDT 24 57287272 ps
T160 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1700506373 Aug 07 06:24:09 PM PDT 24 Aug 07 06:24:28 PM PDT 24 1180362449 ps
T1097 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2309580815 Aug 07 06:24:05 PM PDT 24 Aug 07 06:24:24 PM PDT 24 591337780 ps
T1098 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.720230769 Aug 07 06:24:29 PM PDT 24 Aug 07 06:24:30 PM PDT 24 41561466 ps
T1099 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1263635764 Aug 07 06:24:11 PM PDT 24 Aug 07 06:24:12 PM PDT 24 120966296 ps
T1100 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2356163757 Aug 07 06:24:23 PM PDT 24 Aug 07 06:24:24 PM PDT 24 24066182 ps
T1101 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3911240439 Aug 07 06:24:28 PM PDT 24 Aug 07 06:24:31 PM PDT 24 305189055 ps
T1102 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1625514751 Aug 07 06:24:06 PM PDT 24 Aug 07 06:24:11 PM PDT 24 1351232882 ps
T1103 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.293032818 Aug 07 06:24:22 PM PDT 24 Aug 07 06:24:24 PM PDT 24 219484170 ps
T1104 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1321301270 Aug 07 06:24:32 PM PDT 24 Aug 07 06:24:33 PM PDT 24 38218493 ps
T1105 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3195073881 Aug 07 06:24:40 PM PDT 24 Aug 07 06:25:03 PM PDT 24 4129563249 ps
T1106 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1902602114 Aug 07 06:24:10 PM PDT 24 Aug 07 06:24:12 PM PDT 24 54261767 ps
T1107 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3129362510 Aug 07 06:24:29 PM PDT 24 Aug 07 06:24:31 PM PDT 24 236059362 ps
T1108 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1858899696 Aug 07 06:24:36 PM PDT 24 Aug 07 06:24:37 PM PDT 24 11614938 ps
T1109 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2221298293 Aug 07 06:24:14 PM PDT 24 Aug 07 06:24:16 PM PDT 24 339842083 ps
T1110 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2880660059 Aug 07 06:24:14 PM PDT 24 Aug 07 06:24:17 PM PDT 24 83835628 ps
T1111 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1008086896 Aug 07 06:24:06 PM PDT 24 Aug 07 06:24:30 PM PDT 24 1204144156 ps
T1112 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.241594676 Aug 07 06:24:28 PM PDT 24 Aug 07 06:24:30 PM PDT 24 341997220 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3505403368 Aug 07 06:24:17 PM PDT 24 Aug 07 06:24:17 PM PDT 24 78767031 ps
T1114 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2518182258 Aug 07 06:24:24 PM PDT 24 Aug 07 06:24:28 PM PDT 24 301662456 ps
T1115 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.233579892 Aug 07 06:24:14 PM PDT 24 Aug 07 06:24:14 PM PDT 24 15537656 ps
T1116 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1487291214 Aug 07 06:24:34 PM PDT 24 Aug 07 06:24:34 PM PDT 24 14411131 ps
T1117 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.71687113 Aug 07 06:24:33 PM PDT 24 Aug 07 06:24:34 PM PDT 24 36579700 ps
T1118 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2217516074 Aug 07 06:24:07 PM PDT 24 Aug 07 06:24:12 PM PDT 24 751306407 ps
T1119 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1593578812 Aug 07 06:24:05 PM PDT 24 Aug 07 06:24:07 PM PDT 24 205439246 ps
T1120 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2221563205 Aug 07 06:24:36 PM PDT 24 Aug 07 06:24:48 PM PDT 24 501582208 ps
T1121 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3054452267 Aug 07 06:24:25 PM PDT 24 Aug 07 06:24:28 PM PDT 24 241131251 ps
T1122 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.728780488 Aug 07 06:24:20 PM PDT 24 Aug 07 06:24:24 PM PDT 24 104878263 ps
T1123 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4127196917 Aug 07 06:24:22 PM PDT 24 Aug 07 06:24:23 PM PDT 24 36814607 ps
T1124 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.166467179 Aug 07 06:24:14 PM PDT 24 Aug 07 06:24:17 PM PDT 24 94186056 ps
T1125 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.880979450 Aug 07 06:24:16 PM PDT 24 Aug 07 06:24:29 PM PDT 24 8701626014 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3563434555 Aug 07 06:24:06 PM PDT 24 Aug 07 06:24:11 PM PDT 24 805391832 ps
T1127 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1936731031 Aug 07 06:24:03 PM PDT 24 Aug 07 06:24:04 PM PDT 24 26194254 ps
T1128 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1590840986 Aug 07 06:24:37 PM PDT 24 Aug 07 06:24:37 PM PDT 24 21511194 ps
T1129 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3875037388 Aug 07 06:24:22 PM PDT 24 Aug 07 06:24:24 PM PDT 24 31515870 ps
T1130 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4063304142 Aug 07 06:24:32 PM PDT 24 Aug 07 06:24:32 PM PDT 24 15910403 ps

Test location /workspace/coverage/default/43.spi_device_stress_all.246960404
Short name T3
Test name
Test status
Simulation time 23212533493 ps
CPU time 141.24 seconds
Started Aug 07 06:52:25 PM PDT 24
Finished Aug 07 06:54:46 PM PDT 24
Peak memory 271980 kb
Host smart-f78ffe7b-fc99-40a5-9718-8ac1af3fac8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246960404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.246960404
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4247395370
Short name T11
Test name
Test status
Simulation time 2330524811416 ps
CPU time 1564.3 seconds
Started Aug 07 06:52:12 PM PDT 24
Finished Aug 07 07:18:16 PM PDT 24
Peak memory 282432 kb
Host smart-8cc7813f-d6cd-4ea3-880c-f27fef53b3b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247395370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4247395370
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1693142204
Short name T55
Test name
Test status
Simulation time 271374101 ps
CPU time 3.57 seconds
Started Aug 07 06:24:09 PM PDT 24
Finished Aug 07 06:24:13 PM PDT 24
Peak memory 217916 kb
Host smart-6cb22f95-a94c-4cb2-88cd-1087bdfbd79a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693142204 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1693142204
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2944227100
Short name T19
Test name
Test status
Simulation time 51677905297 ps
CPU time 208.45 seconds
Started Aug 07 06:45:33 PM PDT 24
Finished Aug 07 06:49:02 PM PDT 24
Peak memory 266328 kb
Host smart-a98b2e0d-0ab1-4f7a-b619-7b38324bd39f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944227100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2944227100
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2975884016
Short name T56
Test name
Test status
Simulation time 46669209 ps
CPU time 0.75 seconds
Started Aug 07 06:45:28 PM PDT 24
Finished Aug 07 06:45:29 PM PDT 24
Peak memory 216448 kb
Host smart-a4dee7ea-8489-4f3a-8f43-4803de04fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975884016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2975884016
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4150365217
Short name T17
Test name
Test status
Simulation time 33794150986 ps
CPU time 465.48 seconds
Started Aug 07 06:51:59 PM PDT 24
Finished Aug 07 06:59:45 PM PDT 24
Peak memory 270032 kb
Host smart-a36d4f9e-a86b-45fd-92c5-72276710e1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150365217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4150365217
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2934784938
Short name T41
Test name
Test status
Simulation time 167871302879 ps
CPU time 379.88 seconds
Started Aug 07 06:46:49 PM PDT 24
Finished Aug 07 06:53:09 PM PDT 24
Peak memory 254300 kb
Host smart-72f71abe-a362-48e6-b53f-8dcbd5916ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934784938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2934784938
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3032078040
Short name T176
Test name
Test status
Simulation time 20216742227 ps
CPU time 206.38 seconds
Started Aug 07 06:46:21 PM PDT 24
Finished Aug 07 06:49:48 PM PDT 24
Peak memory 286276 kb
Host smart-a5896e6d-0449-4be4-9a81-e44638f68326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032078040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3032078040
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2699725836
Short name T156
Test name
Test status
Simulation time 299639032 ps
CPU time 19.2 seconds
Started Aug 07 06:24:04 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 215304 kb
Host smart-4a4a84fe-b642-4740-a2db-12f0ce017a14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699725836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2699725836
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2232214076
Short name T143
Test name
Test status
Simulation time 631227959904 ps
CPU time 482.6 seconds
Started Aug 07 06:46:30 PM PDT 24
Finished Aug 07 06:54:32 PM PDT 24
Peak memory 272700 kb
Host smart-8422ce32-51b3-4478-a1cd-ba92f7aedd39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232214076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2232214076
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4230807508
Short name T47
Test name
Test status
Simulation time 12798207 ps
CPU time 0.72 seconds
Started Aug 07 06:52:50 PM PDT 24
Finished Aug 07 06:52:51 PM PDT 24
Peak memory 205904 kb
Host smart-18ab9ee2-d354-4573-9868-14c327e82b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230807508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4230807508
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2308598949
Short name T34
Test name
Test status
Simulation time 369561093 ps
CPU time 3.74 seconds
Started Aug 07 06:45:38 PM PDT 24
Finished Aug 07 06:45:42 PM PDT 24
Peak memory 224964 kb
Host smart-efe3182e-bf0b-4e31-a8ae-97dc4b70b605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308598949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2308598949
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2412765147
Short name T18
Test name
Test status
Simulation time 42206233927 ps
CPU time 397.45 seconds
Started Aug 07 06:48:11 PM PDT 24
Finished Aug 07 06:54:49 PM PDT 24
Peak memory 265972 kb
Host smart-788ba89e-4698-4ec2-bc4f-aeaeb8405d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412765147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2412765147
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.4151047267
Short name T6
Test name
Test status
Simulation time 19949063634 ps
CPU time 128.5 seconds
Started Aug 07 06:48:56 PM PDT 24
Finished Aug 07 06:51:05 PM PDT 24
Peak memory 256624 kb
Host smart-fc44d38f-60ab-460e-9489-d4a74de94df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151047267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.4151047267
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1471228162
Short name T196
Test name
Test status
Simulation time 269178251344 ps
CPU time 542.7 seconds
Started Aug 07 06:46:38 PM PDT 24
Finished Aug 07 06:55:41 PM PDT 24
Peak memory 266156 kb
Host smart-86a23a56-64b8-4b5a-b484-de7542ab992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471228162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1471228162
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.365525572
Short name T73
Test name
Test status
Simulation time 33595769 ps
CPU time 1.13 seconds
Started Aug 07 06:24:21 PM PDT 24
Finished Aug 07 06:24:23 PM PDT 24
Peak memory 206788 kb
Host smart-5b818954-9d5b-489b-998d-f4a920c4f3f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365525572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.365525572
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3527003503
Short name T93
Test name
Test status
Simulation time 72687799 ps
CPU time 5.08 seconds
Started Aug 07 06:24:19 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 216272 kb
Host smart-bdb4152e-903f-46e1-95c6-89cc72f9c5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527003503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3527003503
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2648743140
Short name T260
Test name
Test status
Simulation time 36806002880 ps
CPU time 281.57 seconds
Started Aug 07 06:50:32 PM PDT 24
Finished Aug 07 06:55:14 PM PDT 24
Peak memory 265512 kb
Host smart-09b6944b-4e3a-4d26-9b8e-3c41ca200721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648743140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2648743140
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3285652869
Short name T189
Test name
Test status
Simulation time 13984661606 ps
CPU time 192.77 seconds
Started Aug 07 06:47:44 PM PDT 24
Finished Aug 07 06:50:57 PM PDT 24
Peak memory 267052 kb
Host smart-060c5635-3325-46d9-a7ce-cb4dc5d614ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285652869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3285652869
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3743926403
Short name T44
Test name
Test status
Simulation time 292902317034 ps
CPU time 728.49 seconds
Started Aug 07 06:46:46 PM PDT 24
Finished Aug 07 06:58:55 PM PDT 24
Peak memory 269948 kb
Host smart-c5da10ea-96ac-41f5-8482-956bcfe29ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743926403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3743926403
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3400919347
Short name T61
Test name
Test status
Simulation time 95901789 ps
CPU time 1.16 seconds
Started Aug 07 06:45:33 PM PDT 24
Finished Aug 07 06:45:34 PM PDT 24
Peak memory 237960 kb
Host smart-e6a8fad9-d375-4a06-8612-84662da04208
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400919347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3400919347
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2605594772
Short name T234
Test name
Test status
Simulation time 240830627200 ps
CPU time 422.83 seconds
Started Aug 07 06:51:51 PM PDT 24
Finished Aug 07 06:58:54 PM PDT 24
Peak memory 265904 kb
Host smart-5307d55b-2018-4fc0-9519-a67d13cb0a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605594772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2605594772
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1622063651
Short name T186
Test name
Test status
Simulation time 22374514819 ps
CPU time 83.69 seconds
Started Aug 07 06:50:56 PM PDT 24
Finished Aug 07 06:52:20 PM PDT 24
Peak memory 257844 kb
Host smart-a916df6e-28de-456c-af8e-2fa4fea88a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622063651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1622063651
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.66075273
Short name T244
Test name
Test status
Simulation time 38415020456 ps
CPU time 328 seconds
Started Aug 07 06:45:50 PM PDT 24
Finished Aug 07 06:51:18 PM PDT 24
Peak memory 257588 kb
Host smart-a3a32d63-dc48-4040-84b3-5c99d6b0d093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66075273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.66075273
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.4116492341
Short name T82
Test name
Test status
Simulation time 4074049187 ps
CPU time 80.37 seconds
Started Aug 07 06:46:01 PM PDT 24
Finished Aug 07 06:47:21 PM PDT 24
Peak memory 253448 kb
Host smart-e45c0df2-307f-41dd-8708-00e6919d24c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116492341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.4116492341
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3734298788
Short name T303
Test name
Test status
Simulation time 6578481868 ps
CPU time 39.46 seconds
Started Aug 07 06:47:35 PM PDT 24
Finished Aug 07 06:48:14 PM PDT 24
Peak memory 216692 kb
Host smart-62dd26a7-abdd-41b9-aff3-8470d293f6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734298788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3734298788
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2867870818
Short name T283
Test name
Test status
Simulation time 7441524046 ps
CPU time 161.97 seconds
Started Aug 07 06:48:15 PM PDT 24
Finished Aug 07 06:50:57 PM PDT 24
Peak memory 273332 kb
Host smart-694648cb-b8d2-492c-b6c0-a7072ecc01fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867870818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2867870818
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3364913224
Short name T26
Test name
Test status
Simulation time 1621946870 ps
CPU time 23.06 seconds
Started Aug 07 06:47:39 PM PDT 24
Finished Aug 07 06:48:03 PM PDT 24
Peak memory 254500 kb
Host smart-1c610515-68fa-4029-a7c1-84f163248fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364913224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3364913224
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3195073881
Short name T1105
Test name
Test status
Simulation time 4129563249 ps
CPU time 22.61 seconds
Started Aug 07 06:24:40 PM PDT 24
Finished Aug 07 06:25:03 PM PDT 24
Peak memory 215248 kb
Host smart-970da4a7-9c5e-41f2-8310-1adce199fd81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195073881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3195073881
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.633664481
Short name T290
Test name
Test status
Simulation time 913112810 ps
CPU time 16.36 seconds
Started Aug 07 06:47:04 PM PDT 24
Finished Aug 07 06:47:20 PM PDT 24
Peak memory 233156 kb
Host smart-a5806419-1f91-4e5e-ac6c-7a2a999c47b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633664481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.633664481
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3662804995
Short name T46
Test name
Test status
Simulation time 155807696975 ps
CPU time 447.65 seconds
Started Aug 07 06:51:22 PM PDT 24
Finished Aug 07 06:58:50 PM PDT 24
Peak memory 290076 kb
Host smart-a7bd9d28-7c02-484f-b7b9-8422729eb4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662804995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3662804995
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.555824579
Short name T230
Test name
Test status
Simulation time 19259497298 ps
CPU time 62.73 seconds
Started Aug 07 06:51:33 PM PDT 24
Finished Aug 07 06:52:36 PM PDT 24
Peak memory 249636 kb
Host smart-11732f6b-ba85-4a1c-bceb-abffbe0b9904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555824579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.555824579
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.4134841134
Short name T214
Test name
Test status
Simulation time 15591815124 ps
CPU time 131.12 seconds
Started Aug 07 06:51:47 PM PDT 24
Finished Aug 07 06:53:59 PM PDT 24
Peak memory 249808 kb
Host smart-0454d98a-6db9-4afd-b865-1fbaf08511c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134841134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.4134841134
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.844419585
Short name T88
Test name
Test status
Simulation time 137463600 ps
CPU time 3.98 seconds
Started Aug 07 06:24:20 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 215288 kb
Host smart-0c8f1251-87a9-42b4-a9cc-95eb2fc3a2a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844419585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.844419585
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2785643116
Short name T163
Test name
Test status
Simulation time 759234844 ps
CPU time 13.37 seconds
Started Aug 07 06:24:12 PM PDT 24
Finished Aug 07 06:24:26 PM PDT 24
Peak memory 215284 kb
Host smart-d0e96049-238e-4ba9-9ccf-65b186ab6cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785643116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2785643116
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4044278220
Short name T203
Test name
Test status
Simulation time 61936124487 ps
CPU time 80.36 seconds
Started Aug 07 06:49:23 PM PDT 24
Finished Aug 07 06:50:43 PM PDT 24
Peak memory 255088 kb
Host smart-df022718-f537-46bc-8a4b-9e96187dfaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044278220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4044278220
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2800649632
Short name T255
Test name
Test status
Simulation time 2604931347 ps
CPU time 6.89 seconds
Started Aug 07 06:49:30 PM PDT 24
Finished Aug 07 06:49:37 PM PDT 24
Peak memory 233176 kb
Host smart-82f689a4-aab1-431b-b227-2afd017ed8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800649632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2800649632
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2301077015
Short name T292
Test name
Test status
Simulation time 4070419434 ps
CPU time 15.3 seconds
Started Aug 07 06:46:02 PM PDT 24
Finished Aug 07 06:46:17 PM PDT 24
Peak memory 233924 kb
Host smart-64f6486a-f141-439b-b60b-54d35d7ad5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301077015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2301077015
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.817273190
Short name T137
Test name
Test status
Simulation time 4114806286 ps
CPU time 22.14 seconds
Started Aug 07 06:24:03 PM PDT 24
Finished Aug 07 06:24:25 PM PDT 24
Peak memory 223348 kb
Host smart-587aa9ec-1ba0-4706-b481-f84ed0f23d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817273190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.817273190
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3409028745
Short name T311
Test name
Test status
Simulation time 12925338224 ps
CPU time 36.19 seconds
Started Aug 07 06:47:21 PM PDT 24
Finished Aug 07 06:47:58 PM PDT 24
Peak memory 218296 kb
Host smart-81139ae9-ca35-4f4e-afed-25fc9b4cb839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409028745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3409028745
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1909496264
Short name T870
Test name
Test status
Simulation time 59826530877 ps
CPU time 502.42 seconds
Started Aug 07 06:47:33 PM PDT 24
Finished Aug 07 06:55:55 PM PDT 24
Peak memory 265216 kb
Host smart-3ff94b6b-1590-4816-a61a-645e30ea5484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909496264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1909496264
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3802961278
Short name T178
Test name
Test status
Simulation time 247362067710 ps
CPU time 575.12 seconds
Started Aug 07 06:47:33 PM PDT 24
Finished Aug 07 06:57:09 PM PDT 24
Peak memory 253672 kb
Host smart-bb5a3424-912c-4699-81cd-98598853b905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802961278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3802961278
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1264468486
Short name T174
Test name
Test status
Simulation time 51451775088 ps
CPU time 364.65 seconds
Started Aug 07 06:48:18 PM PDT 24
Finished Aug 07 06:54:23 PM PDT 24
Peak memory 253452 kb
Host smart-6ed3c406-5903-4ce0-876f-cfef3815a334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264468486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1264468486
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1030461833
Short name T246
Test name
Test status
Simulation time 20864808293 ps
CPU time 17.45 seconds
Started Aug 07 06:49:16 PM PDT 24
Finished Aug 07 06:49:33 PM PDT 24
Peak memory 233068 kb
Host smart-e7a306f3-ca29-4f85-a1ac-384a0fad193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030461833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1030461833
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3226523855
Short name T894
Test name
Test status
Simulation time 2130294069 ps
CPU time 13.94 seconds
Started Aug 07 06:49:48 PM PDT 24
Finished Aug 07 06:50:02 PM PDT 24
Peak memory 233160 kb
Host smart-942e13f8-b232-4731-a594-3a4881adfe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226523855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3226523855
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2174118313
Short name T118
Test name
Test status
Simulation time 50416413020 ps
CPU time 15.5 seconds
Started Aug 07 06:49:43 PM PDT 24
Finished Aug 07 06:49:59 PM PDT 24
Peak memory 233244 kb
Host smart-6821bbd1-751c-4556-842d-79497f5963ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174118313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2174118313
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1966618582
Short name T129
Test name
Test status
Simulation time 565312923 ps
CPU time 8.71 seconds
Started Aug 07 06:45:32 PM PDT 24
Finished Aug 07 06:45:41 PM PDT 24
Peak memory 220908 kb
Host smart-2667add2-24be-4986-9e98-61102c0ca1fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1966618582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1966618582
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1625514751
Short name T1102
Test name
Test status
Simulation time 1351232882 ps
CPU time 5.07 seconds
Started Aug 07 06:24:06 PM PDT 24
Finished Aug 07 06:24:11 PM PDT 24
Peak memory 216424 kb
Host smart-b7f02024-8b05-4172-addb-661e071cc669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625514751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
625514751
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.353835090
Short name T106
Test name
Test status
Simulation time 1219300151 ps
CPU time 21.31 seconds
Started Aug 07 06:24:07 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 215236 kb
Host smart-21cc34b5-b32b-4674-a7ac-32514050b235
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353835090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.353835090
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.762616117
Short name T1088
Test name
Test status
Simulation time 828308160 ps
CPU time 11.93 seconds
Started Aug 07 06:24:06 PM PDT 24
Finished Aug 07 06:24:18 PM PDT 24
Peak memory 206780 kb
Host smart-b5b962b1-8df8-494b-b9b5-21e6cfc41797
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762616117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.762616117
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2028847615
Short name T75
Test name
Test status
Simulation time 557175834 ps
CPU time 1.43 seconds
Started Aug 07 06:24:02 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 206956 kb
Host smart-d809a354-91d9-4c14-88a2-8554d8ebaebf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028847615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2028847615
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.569624539
Short name T1051
Test name
Test status
Simulation time 171221799 ps
CPU time 2.8 seconds
Started Aug 07 06:24:04 PM PDT 24
Finished Aug 07 06:24:07 PM PDT 24
Peak memory 216956 kb
Host smart-f97c5fdb-126c-491e-ae36-038705685046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569624539 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.569624539
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2921847708
Short name T1037
Test name
Test status
Simulation time 354295314 ps
CPU time 1.26 seconds
Started Aug 07 06:24:03 PM PDT 24
Finished Aug 07 06:24:05 PM PDT 24
Peak memory 215188 kb
Host smart-ffa7cc14-2d41-43ed-b62f-0bcdc1d984fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921847708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
921847708
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3505403368
Short name T1113
Test name
Test status
Simulation time 78767031 ps
CPU time 0.69 seconds
Started Aug 07 06:24:17 PM PDT 24
Finished Aug 07 06:24:17 PM PDT 24
Peak memory 203960 kb
Host smart-c16c4bd4-ebf3-4c8a-ac49-2c44ff94628a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505403368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
505403368
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2421575768
Short name T1047
Test name
Test status
Simulation time 209382026 ps
CPU time 1.84 seconds
Started Aug 07 06:24:02 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 215156 kb
Host smart-c0a58a13-9e4a-4401-8268-6a8abba51755
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421575768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2421575768
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.135190559
Short name T1017
Test name
Test status
Simulation time 12342734 ps
CPU time 0.65 seconds
Started Aug 07 06:24:07 PM PDT 24
Finished Aug 07 06:24:07 PM PDT 24
Peak memory 202848 kb
Host smart-464b8307-8986-419b-b075-6884813272a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135190559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.135190559
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3710469374
Short name T1092
Test name
Test status
Simulation time 40304283 ps
CPU time 1.65 seconds
Started Aug 07 06:24:19 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 215032 kb
Host smart-d1e2d574-5f5a-40f0-b7cd-4a6ef6f685d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710469374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3710469374
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3133910689
Short name T87
Test name
Test status
Simulation time 73803063 ps
CPU time 1.92 seconds
Started Aug 07 06:24:18 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 215228 kb
Host smart-c0e89c62-ce38-45c0-a2c0-950a0bd65f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133910689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
133910689
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2309580815
Short name T1097
Test name
Test status
Simulation time 591337780 ps
CPU time 18.53 seconds
Started Aug 07 06:24:05 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 215180 kb
Host smart-b3ff6348-445a-4698-b0ca-f4600cb59030
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309580815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2309580815
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.310284493
Short name T104
Test name
Test status
Simulation time 434458091 ps
CPU time 7.9 seconds
Started Aug 07 06:24:08 PM PDT 24
Finished Aug 07 06:24:16 PM PDT 24
Peak memory 207036 kb
Host smart-e3f37908-15a9-423d-a50b-7aa071d2eab3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310284493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.310284493
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.780006138
Short name T1058
Test name
Test status
Simulation time 1389329964 ps
CPU time 13.2 seconds
Started Aug 07 06:24:06 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 206960 kb
Host smart-c19696d1-88a7-41dc-80d7-f1779feab17a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780006138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.780006138
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1495630946
Short name T95
Test name
Test status
Simulation time 134034979 ps
CPU time 4.09 seconds
Started Aug 07 06:24:13 PM PDT 24
Finished Aug 07 06:24:17 PM PDT 24
Peak memory 218152 kb
Host smart-76cf706d-10e4-4194-a00b-b87c0676e08f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495630946 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1495630946
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3914026739
Short name T140
Test name
Test status
Simulation time 50023126 ps
CPU time 1.4 seconds
Started Aug 07 06:24:06 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 206204 kb
Host smart-41be9c41-fac0-4d43-977c-bb68a48f3ac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914026739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
914026739
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.105267906
Short name T1022
Test name
Test status
Simulation time 24098451 ps
CPU time 0.77 seconds
Started Aug 07 06:24:02 PM PDT 24
Finished Aug 07 06:24:03 PM PDT 24
Peak memory 203684 kb
Host smart-e6fe0783-bfdb-481f-acbc-44347d7b01bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105267906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.105267906
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1593578812
Short name T1119
Test name
Test status
Simulation time 205439246 ps
CPU time 2.12 seconds
Started Aug 07 06:24:05 PM PDT 24
Finished Aug 07 06:24:07 PM PDT 24
Peak memory 215140 kb
Host smart-8406be1e-9d93-4281-86dc-e404656a729c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593578812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1593578812
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2131708447
Short name T1009
Test name
Test status
Simulation time 50883360 ps
CPU time 0.66 seconds
Started Aug 07 06:24:09 PM PDT 24
Finished Aug 07 06:24:10 PM PDT 24
Peak memory 203956 kb
Host smart-dece8cd3-93b4-4a2f-82fe-6408a8d85cff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131708447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2131708447
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3456421952
Short name T1042
Test name
Test status
Simulation time 150083599 ps
CPU time 3.89 seconds
Started Aug 07 06:24:09 PM PDT 24
Finished Aug 07 06:24:13 PM PDT 24
Peak memory 215224 kb
Host smart-a356d509-64d6-4e18-85d3-dd7d2e91628c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456421952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3456421952
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3875037388
Short name T1129
Test name
Test status
Simulation time 31515870 ps
CPU time 2.09 seconds
Started Aug 07 06:24:22 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 216116 kb
Host smart-712366b7-f291-4e35-b6df-39f18029fb28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875037388 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3875037388
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1956905920
Short name T1038
Test name
Test status
Simulation time 110045124 ps
CPU time 2.51 seconds
Started Aug 07 06:24:23 PM PDT 24
Finished Aug 07 06:24:25 PM PDT 24
Peak memory 215168 kb
Host smart-3b2a23a5-ab9b-4589-a38e-84873b9b9390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956905920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1956905920
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.233579892
Short name T1115
Test name
Test status
Simulation time 15537656 ps
CPU time 0.81 seconds
Started Aug 07 06:24:14 PM PDT 24
Finished Aug 07 06:24:14 PM PDT 24
Peak memory 203656 kb
Host smart-0a6cb6e4-1815-4a31-8d5e-f4637d1b2bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233579892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.233579892
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3840420888
Short name T1077
Test name
Test status
Simulation time 191917938 ps
CPU time 1.79 seconds
Started Aug 07 06:24:19 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 206916 kb
Host smart-ec160195-917b-4721-8d2b-0f1a8d796a7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840420888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3840420888
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.166467179
Short name T1124
Test name
Test status
Simulation time 94186056 ps
CPU time 3.5 seconds
Started Aug 07 06:24:14 PM PDT 24
Finished Aug 07 06:24:17 PM PDT 24
Peak memory 215300 kb
Host smart-2f44b35b-dfc1-4eac-b0f9-ae63dbe8d639
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166467179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.166467179
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.380514155
Short name T53
Test name
Test status
Simulation time 196417720 ps
CPU time 11.82 seconds
Started Aug 07 06:24:15 PM PDT 24
Finished Aug 07 06:24:27 PM PDT 24
Peak memory 215216 kb
Host smart-34e0ac5e-51d5-4d9d-9716-5d83bc5d017d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380514155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.380514155
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2518182258
Short name T1114
Test name
Test status
Simulation time 301662456 ps
CPU time 3.86 seconds
Started Aug 07 06:24:24 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 217564 kb
Host smart-6dce7e43-0ac4-42c2-b7f2-11bb51ada39f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518182258 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2518182258
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3129362510
Short name T1107
Test name
Test status
Simulation time 236059362 ps
CPU time 2.03 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:31 PM PDT 24
Peak memory 206904 kb
Host smart-31c936f2-0a64-4916-b0a9-e611d796baa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129362510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3129362510
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2356163757
Short name T1100
Test name
Test status
Simulation time 24066182 ps
CPU time 0.72 seconds
Started Aug 07 06:24:23 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 203688 kb
Host smart-6558aae2-c3cb-480f-99c7-4fbb6b6b064c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356163757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2356163757
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2543281651
Short name T1067
Test name
Test status
Simulation time 584749279 ps
CPU time 4.12 seconds
Started Aug 07 06:24:22 PM PDT 24
Finished Aug 07 06:24:27 PM PDT 24
Peak memory 215120 kb
Host smart-35183fa0-0955-4f6e-b0cc-a53d5f23b67b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543281651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2543281651
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2427640127
Short name T89
Test name
Test status
Simulation time 70781521 ps
CPU time 2.4 seconds
Started Aug 07 06:24:23 PM PDT 24
Finished Aug 07 06:24:25 PM PDT 24
Peak memory 215332 kb
Host smart-a85b65ba-9e5d-4bfc-8048-65d947ed3430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427640127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2427640127
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2029477308
Short name T85
Test name
Test status
Simulation time 461271643 ps
CPU time 6.48 seconds
Started Aug 07 06:24:14 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 215504 kb
Host smart-deb5b6eb-deaf-4a39-ad99-c44778fccc89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029477308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2029477308
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3562062122
Short name T1080
Test name
Test status
Simulation time 123351199 ps
CPU time 1.64 seconds
Started Aug 07 06:24:15 PM PDT 24
Finished Aug 07 06:24:17 PM PDT 24
Peak memory 216228 kb
Host smart-279e494d-77f5-4f69-9a0b-e2b888fbf7e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562062122 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3562062122
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3927055106
Short name T1062
Test name
Test status
Simulation time 253898254 ps
CPU time 1.95 seconds
Started Aug 07 06:24:17 PM PDT 24
Finished Aug 07 06:24:19 PM PDT 24
Peak memory 215168 kb
Host smart-f0e728e3-1357-48ed-8c0b-50f4f12a6d7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927055106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3927055106
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1428279048
Short name T1071
Test name
Test status
Simulation time 38968677 ps
CPU time 0.72 seconds
Started Aug 07 06:24:13 PM PDT 24
Finished Aug 07 06:24:14 PM PDT 24
Peak memory 203964 kb
Host smart-24ec1112-685f-4a78-8f18-0fe4ca989c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428279048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1428279048
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3361703935
Short name T1091
Test name
Test status
Simulation time 823884477 ps
CPU time 3.12 seconds
Started Aug 07 06:24:25 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 215076 kb
Host smart-1c47fd85-717d-423d-a6ad-974627e1173c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361703935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3361703935
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2895153437
Short name T54
Test name
Test status
Simulation time 99894731 ps
CPU time 3 seconds
Started Aug 07 06:24:14 PM PDT 24
Finished Aug 07 06:24:17 PM PDT 24
Peak memory 215276 kb
Host smart-9018d828-9a58-4ed9-ad11-ba6caaeaa345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895153437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2895153437
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3177231848
Short name T1045
Test name
Test status
Simulation time 276163679 ps
CPU time 7.57 seconds
Started Aug 07 06:24:20 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 223312 kb
Host smart-6240bdcd-236e-4ef6-8ff4-9427c01e354a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177231848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3177231848
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.55490951
Short name T1078
Test name
Test status
Simulation time 168101084 ps
CPU time 2.55 seconds
Started Aug 07 06:24:21 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 215820 kb
Host smart-d86d4033-1a2a-43ee-9be6-cd939c6a2360
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55490951 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.55490951
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2778670375
Short name T112
Test name
Test status
Simulation time 611433599 ps
CPU time 2.47 seconds
Started Aug 07 06:24:13 PM PDT 24
Finished Aug 07 06:24:16 PM PDT 24
Peak memory 215164 kb
Host smart-1b2ec5b2-f413-4a3b-9140-a8bdafc2d89e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778670375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2778670375
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4060980476
Short name T1044
Test name
Test status
Simulation time 22439656 ps
CPU time 0.76 seconds
Started Aug 07 06:24:18 PM PDT 24
Finished Aug 07 06:24:19 PM PDT 24
Peak memory 203668 kb
Host smart-85c64f91-3f39-4a4f-82bc-00f7554ed19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060980476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
4060980476
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2359354867
Short name T1035
Test name
Test status
Simulation time 110225649 ps
CPU time 1.8 seconds
Started Aug 07 06:24:13 PM PDT 24
Finished Aug 07 06:24:15 PM PDT 24
Peak memory 206988 kb
Host smart-be4d430f-d6f6-4441-910c-1491f983f498
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359354867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2359354867
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1951207606
Short name T91
Test name
Test status
Simulation time 164456568 ps
CPU time 2.82 seconds
Started Aug 07 06:24:22 PM PDT 24
Finished Aug 07 06:24:25 PM PDT 24
Peak memory 215320 kb
Host smart-5f21f916-2523-4e12-bbee-229c39fc0552
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951207606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1951207606
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.303361763
Short name T1068
Test name
Test status
Simulation time 136714230 ps
CPU time 3.21 seconds
Started Aug 07 06:24:34 PM PDT 24
Finished Aug 07 06:24:38 PM PDT 24
Peak memory 217372 kb
Host smart-fadbc058-8c6f-44a6-841f-1e905a4828ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303361763 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.303361763
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1321301270
Short name T1104
Test name
Test status
Simulation time 38218493 ps
CPU time 1.27 seconds
Started Aug 07 06:24:32 PM PDT 24
Finished Aug 07 06:24:33 PM PDT 24
Peak memory 215228 kb
Host smart-5cf097b8-e504-4441-89e5-d62abb71d63e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321301270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1321301270
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4127196917
Short name T1123
Test name
Test status
Simulation time 36814607 ps
CPU time 0.7 seconds
Started Aug 07 06:24:22 PM PDT 24
Finished Aug 07 06:24:23 PM PDT 24
Peak memory 203988 kb
Host smart-d4b2ed61-7a37-474b-acf5-f36cfc1d4625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127196917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
4127196917
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2606444512
Short name T1036
Test name
Test status
Simulation time 29729002 ps
CPU time 1.94 seconds
Started Aug 07 06:24:19 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 215212 kb
Host smart-240cda19-a441-4e85-832c-eb0d23da4190
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606444512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2606444512
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3577481301
Short name T158
Test name
Test status
Simulation time 3782832868 ps
CPU time 14.1 seconds
Started Aug 07 06:24:20 PM PDT 24
Finished Aug 07 06:24:34 PM PDT 24
Peak memory 215484 kb
Host smart-5f7349da-c3e1-4ea2-850c-951c55c24545
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577481301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3577481301
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.728780488
Short name T1122
Test name
Test status
Simulation time 104878263 ps
CPU time 3.77 seconds
Started Aug 07 06:24:20 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 217596 kb
Host smart-630b954b-24c0-4c8c-a029-d142f77fb121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728780488 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.728780488
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1090196260
Short name T111
Test name
Test status
Simulation time 34971899 ps
CPU time 2.29 seconds
Started Aug 07 06:24:25 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 220208 kb
Host smart-2bf7ac7f-92a6-47f4-ae9d-28e3ec9498c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090196260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1090196260
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2308277295
Short name T1046
Test name
Test status
Simulation time 27932902 ps
CPU time 0.72 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 203652 kb
Host smart-18045074-d806-4ddb-8948-6f6cc72c796d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308277295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2308277295
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.21886769
Short name T1050
Test name
Test status
Simulation time 220807767 ps
CPU time 3.84 seconds
Started Aug 07 06:24:30 PM PDT 24
Finished Aug 07 06:24:34 PM PDT 24
Peak memory 215228 kb
Host smart-44d82715-13fd-4aeb-9e99-72736b27f54e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21886769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sp
i_device_same_csr_outstanding.21886769
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3973076553
Short name T92
Test name
Test status
Simulation time 52328916 ps
CPU time 3.25 seconds
Started Aug 07 06:24:25 PM PDT 24
Finished Aug 07 06:24:29 PM PDT 24
Peak memory 215312 kb
Host smart-36a5b407-a207-48e5-948b-82c7e28d3628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973076553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3973076553
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3770840029
Short name T159
Test name
Test status
Simulation time 1804980176 ps
CPU time 13.33 seconds
Started Aug 07 06:24:26 PM PDT 24
Finished Aug 07 06:24:39 PM PDT 24
Peak memory 215844 kb
Host smart-88a89cf0-6e7b-43eb-b4e5-cf1ba22a8c68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770840029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3770840029
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2462632706
Short name T1025
Test name
Test status
Simulation time 132936969 ps
CPU time 1.79 seconds
Started Aug 07 06:24:23 PM PDT 24
Finished Aug 07 06:24:25 PM PDT 24
Peak memory 216320 kb
Host smart-eda079fb-b0bc-419c-8a20-5ad123960bf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462632706 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2462632706
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3101797264
Short name T102
Test name
Test status
Simulation time 26472219 ps
CPU time 1.66 seconds
Started Aug 07 06:24:28 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 215160 kb
Host smart-f1115f91-e951-4b3a-972c-ad1cfa5411e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101797264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3101797264
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3314799319
Short name T1054
Test name
Test status
Simulation time 15563209 ps
CPU time 0.71 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 203676 kb
Host smart-abb1d5df-0d6a-4415-8cbd-60d1b0f1d72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314799319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3314799319
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1557304863
Short name T1066
Test name
Test status
Simulation time 591864803 ps
CPU time 3.98 seconds
Started Aug 07 06:24:31 PM PDT 24
Finished Aug 07 06:24:35 PM PDT 24
Peak memory 215196 kb
Host smart-3e593ffb-cbd0-4acc-a444-f32c40a85b59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557304863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1557304863
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1972708163
Short name T86
Test name
Test status
Simulation time 796673787 ps
CPU time 13 seconds
Started Aug 07 06:24:21 PM PDT 24
Finished Aug 07 06:24:34 PM PDT 24
Peak memory 215496 kb
Host smart-5b87ac43-974e-4e89-ac52-08784800fd39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972708163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1972708163
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2558939735
Short name T83
Test name
Test status
Simulation time 27778413 ps
CPU time 1.69 seconds
Started Aug 07 06:24:38 PM PDT 24
Finished Aug 07 06:24:40 PM PDT 24
Peak memory 216236 kb
Host smart-ece9b93c-a47b-4c04-aadf-64f5228aee26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558939735 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2558939735
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.988116330
Short name T1087
Test name
Test status
Simulation time 260117285 ps
CPU time 1.69 seconds
Started Aug 07 06:24:22 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 215184 kb
Host smart-714f6ffa-365a-4b0e-aa47-c9c70c144d2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988116330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.988116330
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1789089032
Short name T1029
Test name
Test status
Simulation time 122322039 ps
CPU time 0.71 seconds
Started Aug 07 06:24:32 PM PDT 24
Finished Aug 07 06:24:33 PM PDT 24
Peak memory 203680 kb
Host smart-e112db2f-d3e3-4c3d-8de7-2752bf139382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789089032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1789089032
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4145513432
Short name T125
Test name
Test status
Simulation time 993959242 ps
CPU time 2.92 seconds
Started Aug 07 06:24:20 PM PDT 24
Finished Aug 07 06:24:23 PM PDT 24
Peak memory 215160 kb
Host smart-1a789637-cbb6-4eb0-b0eb-6a586af9d44b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145513432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4145513432
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.254262344
Short name T84
Test name
Test status
Simulation time 216282682 ps
CPU time 1.89 seconds
Started Aug 07 06:24:27 PM PDT 24
Finished Aug 07 06:24:29 PM PDT 24
Peak memory 215300 kb
Host smart-2a06c4fa-5182-4b6d-b28b-79ce5df9bf18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254262344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.254262344
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3518154776
Short name T162
Test name
Test status
Simulation time 2680938041 ps
CPU time 7.38 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:36 PM PDT 24
Peak memory 215392 kb
Host smart-1408d13e-4b53-40f0-98ec-a01b86c7e083
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518154776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3518154776
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.241594676
Short name T1112
Test name
Test status
Simulation time 341997220 ps
CPU time 2.46 seconds
Started Aug 07 06:24:28 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 218076 kb
Host smart-2e3ca256-ae12-464d-aba5-f9923dfd74e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241594676 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.241594676
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3911240439
Short name T1101
Test name
Test status
Simulation time 305189055 ps
CPU time 2.08 seconds
Started Aug 07 06:24:28 PM PDT 24
Finished Aug 07 06:24:31 PM PDT 24
Peak memory 215156 kb
Host smart-6015442a-3249-4521-b36d-1298ee78d291
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911240439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3911240439
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3108870359
Short name T1013
Test name
Test status
Simulation time 14569906 ps
CPU time 0.73 seconds
Started Aug 07 06:24:25 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 203668 kb
Host smart-b4d2bd33-3236-49a1-b38d-e80cc2249ec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108870359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3108870359
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.305530323
Short name T1090
Test name
Test status
Simulation time 1086151094 ps
CPU time 3.94 seconds
Started Aug 07 06:24:17 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 215204 kb
Host smart-85104a79-88cc-4565-bcd9-94a8b167e6df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305530323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.305530323
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4066984321
Short name T1076
Test name
Test status
Simulation time 325940845 ps
CPU time 4.91 seconds
Started Aug 07 06:24:21 PM PDT 24
Finished Aug 07 06:24:26 PM PDT 24
Peak memory 215436 kb
Host smart-77d849a2-f980-4cbf-83fd-6d0e5d102757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066984321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4066984321
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2221563205
Short name T1120
Test name
Test status
Simulation time 501582208 ps
CPU time 12.79 seconds
Started Aug 07 06:24:36 PM PDT 24
Finished Aug 07 06:24:48 PM PDT 24
Peak memory 215192 kb
Host smart-809d712a-729b-487b-a693-694c0c5bb37c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221563205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2221563205
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.799524677
Short name T1094
Test name
Test status
Simulation time 105967591 ps
CPU time 2.66 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:32 PM PDT 24
Peak memory 216220 kb
Host smart-d7bd887f-d839-4f29-b4f9-a6696d23b446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799524677 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.799524677
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3054452267
Short name T1121
Test name
Test status
Simulation time 241131251 ps
CPU time 2.06 seconds
Started Aug 07 06:24:25 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 215240 kb
Host smart-603279c3-a926-4ec2-9480-f09189c3ed5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054452267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3054452267
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.738989951
Short name T1086
Test name
Test status
Simulation time 45677762 ps
CPU time 0.73 seconds
Started Aug 07 06:24:35 PM PDT 24
Finished Aug 07 06:24:36 PM PDT 24
Peak memory 203732 kb
Host smart-9a4c1347-f917-446d-9c35-c7ab8608e1db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738989951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.738989951
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.889995790
Short name T1031
Test name
Test status
Simulation time 260279149 ps
CPU time 2 seconds
Started Aug 07 06:24:33 PM PDT 24
Finished Aug 07 06:24:35 PM PDT 24
Peak memory 215164 kb
Host smart-7a7f5e3b-bd97-4e48-809c-2a9ddb872caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889995790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.889995790
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.681463692
Short name T94
Test name
Test status
Simulation time 692569515 ps
CPU time 5.73 seconds
Started Aug 07 06:24:36 PM PDT 24
Finished Aug 07 06:24:42 PM PDT 24
Peak memory 215360 kb
Host smart-4b5227e3-906a-4321-80b2-665e5c7a117d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681463692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.681463692
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3994829444
Short name T105
Test name
Test status
Simulation time 9165066040 ps
CPU time 21.99 seconds
Started Aug 07 06:24:17 PM PDT 24
Finished Aug 07 06:24:39 PM PDT 24
Peak memory 216328 kb
Host smart-dcb78154-26e2-4109-ac77-7a8ac6b19975
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994829444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3994829444
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1008086896
Short name T1111
Test name
Test status
Simulation time 1204144156 ps
CPU time 23.71 seconds
Started Aug 07 06:24:06 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 206984 kb
Host smart-40f36f41-b6a6-416d-b941-0d3df3ba495f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008086896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1008086896
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2638940067
Short name T1096
Test name
Test status
Simulation time 57287272 ps
CPU time 1.15 seconds
Started Aug 07 06:24:20 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 207104 kb
Host smart-51e2ec6d-b000-4051-8e68-f8d414549ed4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638940067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2638940067
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.674449774
Short name T98
Test name
Test status
Simulation time 106214805 ps
CPU time 1.6 seconds
Started Aug 07 06:24:07 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 214640 kb
Host smart-fe07b465-bb21-4b34-8e1c-8bb55613d190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674449774 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.674449774
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.212600766
Short name T1059
Test name
Test status
Simulation time 165662496 ps
CPU time 2.71 seconds
Started Aug 07 06:24:20 PM PDT 24
Finished Aug 07 06:24:22 PM PDT 24
Peak memory 215140 kb
Host smart-22960676-d0fb-4158-a545-ef61915f4f19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212600766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.212600766
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3408490351
Short name T1039
Test name
Test status
Simulation time 10862186 ps
CPU time 0.72 seconds
Started Aug 07 06:24:09 PM PDT 24
Finished Aug 07 06:24:10 PM PDT 24
Peak memory 203668 kb
Host smart-708d4164-bea5-4e6d-8f1a-a3fad39aa607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408490351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
408490351
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3060032992
Short name T114
Test name
Test status
Simulation time 57325147 ps
CPU time 1.88 seconds
Started Aug 07 06:24:06 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 215116 kb
Host smart-254251fb-f464-4ed5-ac45-1216002c9019
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060032992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3060032992
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1936731031
Short name T1127
Test name
Test status
Simulation time 26194254 ps
CPU time 0.74 seconds
Started Aug 07 06:24:03 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 203640 kb
Host smart-72a5ae88-ed28-4ca7-9dd1-0bd803682058
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936731031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1936731031
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2098094480
Short name T138
Test name
Test status
Simulation time 596151634 ps
CPU time 3.25 seconds
Started Aug 07 06:24:04 PM PDT 24
Finished Aug 07 06:24:07 PM PDT 24
Peak memory 215148 kb
Host smart-095a84ed-087e-4727-828a-1e640c9e6367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098094480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2098094480
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.199054798
Short name T1082
Test name
Test status
Simulation time 301739866 ps
CPU time 2.27 seconds
Started Aug 07 06:24:08 PM PDT 24
Finished Aug 07 06:24:11 PM PDT 24
Peak memory 215264 kb
Host smart-c7a30d9a-668f-4a6b-a24e-86a3a867049b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199054798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.199054798
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4214389738
Short name T1069
Test name
Test status
Simulation time 36016990 ps
CPU time 0.71 seconds
Started Aug 07 06:24:32 PM PDT 24
Finished Aug 07 06:24:33 PM PDT 24
Peak memory 203948 kb
Host smart-f4121bb0-5df2-426b-860f-10ee36aa1b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214389738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4214389738
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4063304142
Short name T1130
Test name
Test status
Simulation time 15910403 ps
CPU time 0.73 seconds
Started Aug 07 06:24:32 PM PDT 24
Finished Aug 07 06:24:32 PM PDT 24
Peak memory 203680 kb
Host smart-7f536cf9-33b6-4e1c-b453-42583efac5f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063304142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4063304142
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3143476936
Short name T1019
Test name
Test status
Simulation time 33407346 ps
CPU time 0.77 seconds
Started Aug 07 06:24:37 PM PDT 24
Finished Aug 07 06:24:38 PM PDT 24
Peak memory 203676 kb
Host smart-29ddf4bf-0c17-4c5d-bfa4-fa0747dc2bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143476936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3143476936
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2451941626
Short name T1055
Test name
Test status
Simulation time 50499681 ps
CPU time 0.73 seconds
Started Aug 07 06:24:32 PM PDT 24
Finished Aug 07 06:24:33 PM PDT 24
Peak memory 203724 kb
Host smart-526b83eb-d820-434f-b332-5f7e048ef3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451941626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2451941626
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1800062862
Short name T1072
Test name
Test status
Simulation time 22658147 ps
CPU time 0.72 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 203648 kb
Host smart-b341415d-b9a5-4b54-9c44-ea6ea90ec83b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800062862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1800062862
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1043604623
Short name T1089
Test name
Test status
Simulation time 28790907 ps
CPU time 0.79 seconds
Started Aug 07 06:24:31 PM PDT 24
Finished Aug 07 06:24:32 PM PDT 24
Peak memory 203960 kb
Host smart-0a8ff14b-a770-4901-a887-70c452db3f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043604623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1043604623
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3480594852
Short name T1028
Test name
Test status
Simulation time 15551567 ps
CPU time 0.76 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 204040 kb
Host smart-1c891a5e-44b4-42e6-ac29-95183d388429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480594852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3480594852
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1325469659
Short name T1033
Test name
Test status
Simulation time 24475784 ps
CPU time 0.79 seconds
Started Aug 07 06:24:37 PM PDT 24
Finished Aug 07 06:24:38 PM PDT 24
Peak memory 204036 kb
Host smart-d994c039-ddb1-4fa0-ac07-2d9a0542601e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325469659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1325469659
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.71687113
Short name T1117
Test name
Test status
Simulation time 36579700 ps
CPU time 0.73 seconds
Started Aug 07 06:24:33 PM PDT 24
Finished Aug 07 06:24:34 PM PDT 24
Peak memory 203656 kb
Host smart-feaad5ac-b4f3-4d5a-b9dd-4138a771aa79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71687113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.71687113
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1487291214
Short name T1116
Test name
Test status
Simulation time 14411131 ps
CPU time 0.76 seconds
Started Aug 07 06:24:34 PM PDT 24
Finished Aug 07 06:24:34 PM PDT 24
Peak memory 203648 kb
Host smart-13fadc95-1d2b-480a-8018-22a59294d398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487291214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1487291214
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3169765799
Short name T110
Test name
Test status
Simulation time 308242804 ps
CPU time 20.88 seconds
Started Aug 07 06:24:08 PM PDT 24
Finished Aug 07 06:24:29 PM PDT 24
Peak memory 215168 kb
Host smart-a15114c3-5725-4bca-b474-9ca2b7acce1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169765799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3169765799
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.880979450
Short name T1125
Test name
Test status
Simulation time 8701626014 ps
CPU time 13.44 seconds
Started Aug 07 06:24:16 PM PDT 24
Finished Aug 07 06:24:29 PM PDT 24
Peak memory 207096 kb
Host smart-855d9870-4861-4dac-bb6e-d967fde8b423
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880979450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.880979450
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1042123046
Short name T74
Test name
Test status
Simulation time 121392078 ps
CPU time 1.16 seconds
Started Aug 07 06:24:17 PM PDT 24
Finished Aug 07 06:24:18 PM PDT 24
Peak memory 206984 kb
Host smart-b76742e1-10c1-4fad-aa32-e8f0467cf7f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042123046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1042123046
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3587524687
Short name T97
Test name
Test status
Simulation time 77531851 ps
CPU time 2.69 seconds
Started Aug 07 06:24:21 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 217080 kb
Host smart-a04363e9-18ef-4f89-af03-88b51f307098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587524687 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3587524687
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1597635162
Short name T1056
Test name
Test status
Simulation time 29666937 ps
CPU time 1.9 seconds
Started Aug 07 06:24:11 PM PDT 24
Finished Aug 07 06:24:13 PM PDT 24
Peak memory 215144 kb
Host smart-4638d897-0f3b-4fcb-8d50-604516a96b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597635162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
597635162
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3724213322
Short name T1065
Test name
Test status
Simulation time 61555496 ps
CPU time 0.76 seconds
Started Aug 07 06:24:19 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 203644 kb
Host smart-4fef735b-67e3-4dc3-9a30-f316209fa3a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724213322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
724213322
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1515088466
Short name T1057
Test name
Test status
Simulation time 67093971 ps
CPU time 1.4 seconds
Started Aug 07 06:24:11 PM PDT 24
Finished Aug 07 06:24:12 PM PDT 24
Peak memory 215100 kb
Host smart-3c9d58f4-ca7c-4611-91c0-954288dc208c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515088466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1515088466
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3609277980
Short name T1052
Test name
Test status
Simulation time 17526535 ps
CPU time 0.68 seconds
Started Aug 07 06:24:10 PM PDT 24
Finished Aug 07 06:24:10 PM PDT 24
Peak memory 203604 kb
Host smart-0f1da930-7b63-4bf1-91d0-c9d1efe5be6e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609277980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3609277980
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2000831084
Short name T1024
Test name
Test status
Simulation time 821236315 ps
CPU time 3.83 seconds
Started Aug 07 06:24:11 PM PDT 24
Finished Aug 07 06:24:15 PM PDT 24
Peak memory 215252 kb
Host smart-b522693d-6307-4152-8364-f50d94f30317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000831084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2000831084
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3563434555
Short name T1126
Test name
Test status
Simulation time 805391832 ps
CPU time 4.21 seconds
Started Aug 07 06:24:06 PM PDT 24
Finished Aug 07 06:24:11 PM PDT 24
Peak memory 214564 kb
Host smart-91839e03-dad2-44bf-ad96-aabca912fd16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563434555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
563434555
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2004253013
Short name T157
Test name
Test status
Simulation time 831662676 ps
CPU time 19.44 seconds
Started Aug 07 06:24:09 PM PDT 24
Finished Aug 07 06:24:29 PM PDT 24
Peak memory 215192 kb
Host smart-9e59c11b-1170-4bf9-a01b-b6a45d040d27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004253013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2004253013
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.720230769
Short name T1098
Test name
Test status
Simulation time 41561466 ps
CPU time 0.76 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 203584 kb
Host smart-bdef3398-153f-4839-bf5e-fc356e85fed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720230769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.720230769
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1014195470
Short name T1016
Test name
Test status
Simulation time 15238184 ps
CPU time 0.76 seconds
Started Aug 07 06:24:30 PM PDT 24
Finished Aug 07 06:24:31 PM PDT 24
Peak memory 203952 kb
Host smart-01e5b871-c989-44c4-8ae9-ddf3677bccfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014195470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1014195470
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1744233663
Short name T1063
Test name
Test status
Simulation time 12277950 ps
CPU time 0.72 seconds
Started Aug 07 06:24:33 PM PDT 24
Finished Aug 07 06:24:34 PM PDT 24
Peak memory 203976 kb
Host smart-754dafe6-4c7d-4c98-8f6d-a773132a1f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744233663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1744233663
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4160536565
Short name T1093
Test name
Test status
Simulation time 53173324 ps
CPU time 0.73 seconds
Started Aug 07 06:24:42 PM PDT 24
Finished Aug 07 06:24:43 PM PDT 24
Peak memory 203676 kb
Host smart-93e3110b-3a7a-4100-8272-99e73e90375a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160536565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4160536565
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3300473078
Short name T1061
Test name
Test status
Simulation time 13372243 ps
CPU time 0.72 seconds
Started Aug 07 06:24:30 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 203956 kb
Host smart-007fbd21-63dc-4d34-bb41-00576f1ddef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300473078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3300473078
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1295592849
Short name T1041
Test name
Test status
Simulation time 27798090 ps
CPU time 0.68 seconds
Started Aug 07 06:24:30 PM PDT 24
Finished Aug 07 06:24:31 PM PDT 24
Peak memory 203660 kb
Host smart-0b385dcf-9610-429a-b1cc-80ed54eab07b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295592849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1295592849
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2830681436
Short name T1023
Test name
Test status
Simulation time 38440242 ps
CPU time 0.7 seconds
Started Aug 07 06:24:27 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 203680 kb
Host smart-ee7cdd2d-2f8b-452e-a02b-2663fb3d4788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830681436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2830681436
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1053556119
Short name T1030
Test name
Test status
Simulation time 75981702 ps
CPU time 0.72 seconds
Started Aug 07 06:24:37 PM PDT 24
Finished Aug 07 06:24:38 PM PDT 24
Peak memory 203672 kb
Host smart-9562bad9-51cf-4c79-9395-838b776d4ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053556119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1053556119
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1858899696
Short name T1108
Test name
Test status
Simulation time 11614938 ps
CPU time 0.72 seconds
Started Aug 07 06:24:36 PM PDT 24
Finished Aug 07 06:24:37 PM PDT 24
Peak memory 203684 kb
Host smart-ffe238e9-0d26-4f66-940b-82111240fa8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858899696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1858899696
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3176292062
Short name T1015
Test name
Test status
Simulation time 12725027 ps
CPU time 0.72 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:45 PM PDT 24
Peak memory 203672 kb
Host smart-61456b42-1452-4d32-91dc-b237c71c655f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176292062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3176292062
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.980989272
Short name T1018
Test name
Test status
Simulation time 995988294 ps
CPU time 15.86 seconds
Started Aug 07 06:24:11 PM PDT 24
Finished Aug 07 06:24:27 PM PDT 24
Peak memory 206900 kb
Host smart-5e25ca52-e9a8-4a10-8afe-cde244b78e31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980989272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.980989272
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1595213983
Short name T108
Test name
Test status
Simulation time 22616210186 ps
CPU time 26.55 seconds
Started Aug 07 06:24:18 PM PDT 24
Finished Aug 07 06:24:45 PM PDT 24
Peak memory 206984 kb
Host smart-d26971df-c35c-432a-9e86-684a5294fda8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595213983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1595213983
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.372048268
Short name T76
Test name
Test status
Simulation time 418195561 ps
CPU time 1.55 seconds
Started Aug 07 06:24:12 PM PDT 24
Finished Aug 07 06:24:13 PM PDT 24
Peak memory 207016 kb
Host smart-9a199ad4-dc5f-4776-9fb7-1bea7663b1fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372048268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.372048268
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1215543282
Short name T96
Test name
Test status
Simulation time 27391400 ps
CPU time 2.2 seconds
Started Aug 07 06:24:13 PM PDT 24
Finished Aug 07 06:24:15 PM PDT 24
Peak memory 216516 kb
Host smart-1db94432-3501-450e-bd1d-33bc289ae1cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215543282 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1215543282
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1174346701
Short name T113
Test name
Test status
Simulation time 70353507 ps
CPU time 1.39 seconds
Started Aug 07 06:24:13 PM PDT 24
Finished Aug 07 06:24:14 PM PDT 24
Peak memory 215176 kb
Host smart-799ef763-6aff-471d-95e0-8e6e0b2381c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174346701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
174346701
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.819653781
Short name T1085
Test name
Test status
Simulation time 28686812 ps
CPU time 0.73 seconds
Started Aug 07 06:24:24 PM PDT 24
Finished Aug 07 06:24:25 PM PDT 24
Peak memory 203664 kb
Host smart-83acec24-a4a3-4cb1-973d-fd596f23e307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819653781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.819653781
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.333008417
Short name T103
Test name
Test status
Simulation time 229940928 ps
CPU time 2.25 seconds
Started Aug 07 06:24:14 PM PDT 24
Finished Aug 07 06:24:16 PM PDT 24
Peak memory 215164 kb
Host smart-fe557312-75ce-4b6b-b799-b3d11cf2e709
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333008417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.333008417
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4276572472
Short name T1020
Test name
Test status
Simulation time 102106081 ps
CPU time 0.7 seconds
Started Aug 07 06:24:10 PM PDT 24
Finished Aug 07 06:24:11 PM PDT 24
Peak memory 203992 kb
Host smart-0d5c6f46-f9a0-48d2-b89e-69ae157b0aa7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276572472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4276572472
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1892427796
Short name T1049
Test name
Test status
Simulation time 249204654 ps
CPU time 1.71 seconds
Started Aug 07 06:24:19 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 215160 kb
Host smart-a295d081-cef4-44e1-b755-da2ba5ae1f8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892427796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1892427796
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4149209486
Short name T1095
Test name
Test status
Simulation time 63676036 ps
CPU time 1.51 seconds
Started Aug 07 06:24:15 PM PDT 24
Finished Aug 07 06:24:17 PM PDT 24
Peak memory 215220 kb
Host smart-c2800478-f46a-4a2d-a699-8c1d1912b394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149209486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
149209486
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1414666211
Short name T161
Test name
Test status
Simulation time 574637955 ps
CPU time 15.97 seconds
Started Aug 07 06:24:10 PM PDT 24
Finished Aug 07 06:24:26 PM PDT 24
Peak memory 215316 kb
Host smart-36f07ee4-443e-4e31-9385-134a1124a5bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414666211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1414666211
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1356371621
Short name T1053
Test name
Test status
Simulation time 95990606 ps
CPU time 0.77 seconds
Started Aug 07 06:24:33 PM PDT 24
Finished Aug 07 06:24:34 PM PDT 24
Peak memory 203672 kb
Host smart-dd41c49a-8ef1-448a-b4aa-20e434e1d952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356371621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1356371621
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1590840986
Short name T1128
Test name
Test status
Simulation time 21511194 ps
CPU time 0.7 seconds
Started Aug 07 06:24:37 PM PDT 24
Finished Aug 07 06:24:37 PM PDT 24
Peak memory 203676 kb
Host smart-4b3d8ed6-3c10-4f02-bb4a-efb115e3f76b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590840986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1590840986
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3614613155
Short name T1081
Test name
Test status
Simulation time 11479915 ps
CPU time 0.75 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:30 PM PDT 24
Peak memory 203964 kb
Host smart-fce06670-39c6-4af4-af19-42dc87c15dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614613155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3614613155
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.795524350
Short name T1074
Test name
Test status
Simulation time 15810558 ps
CPU time 0.69 seconds
Started Aug 07 06:24:41 PM PDT 24
Finished Aug 07 06:24:42 PM PDT 24
Peak memory 203688 kb
Host smart-27c3b887-0035-48d1-a2e0-d01d4ce9bd9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795524350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.795524350
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1775966635
Short name T1034
Test name
Test status
Simulation time 28375148 ps
CPU time 0.68 seconds
Started Aug 07 06:24:40 PM PDT 24
Finished Aug 07 06:24:40 PM PDT 24
Peak memory 203668 kb
Host smart-d5a793d6-131b-4f40-83e5-d4270f39f025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775966635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1775966635
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.260416932
Short name T1040
Test name
Test status
Simulation time 20957494 ps
CPU time 0.74 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:45 PM PDT 24
Peak memory 204004 kb
Host smart-f70d7ffb-2f5b-4142-a801-2782b8040ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260416932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.260416932
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.909757439
Short name T1075
Test name
Test status
Simulation time 11612558 ps
CPU time 0.73 seconds
Started Aug 07 06:24:36 PM PDT 24
Finished Aug 07 06:24:37 PM PDT 24
Peak memory 203588 kb
Host smart-2eb9d527-06b6-4760-b6f5-9832dce43972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909757439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.909757439
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2943084822
Short name T1026
Test name
Test status
Simulation time 16705862 ps
CPU time 0.75 seconds
Started Aug 07 06:24:46 PM PDT 24
Finished Aug 07 06:24:47 PM PDT 24
Peak memory 204000 kb
Host smart-f62cc81a-16e8-4dea-b445-37a6f457be49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943084822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2943084822
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1956087361
Short name T1014
Test name
Test status
Simulation time 11051754 ps
CPU time 0.7 seconds
Started Aug 07 06:24:30 PM PDT 24
Finished Aug 07 06:24:31 PM PDT 24
Peak memory 203944 kb
Host smart-78dbdcdc-6daa-4027-b3c8-b9027e004b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956087361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1956087361
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3979197827
Short name T1084
Test name
Test status
Simulation time 35840215 ps
CPU time 0.7 seconds
Started Aug 07 06:24:30 PM PDT 24
Finished Aug 07 06:24:31 PM PDT 24
Peak memory 203696 kb
Host smart-5cfb4321-304f-460d-a2d4-ff157e66ffa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979197827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3979197827
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2880660059
Short name T1110
Test name
Test status
Simulation time 83835628 ps
CPU time 2.34 seconds
Started Aug 07 06:24:14 PM PDT 24
Finished Aug 07 06:24:17 PM PDT 24
Peak memory 216264 kb
Host smart-8d29bcac-1eed-43b3-8f31-87762c15064c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880660059 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2880660059
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2126640787
Short name T1021
Test name
Test status
Simulation time 151370865 ps
CPU time 2.29 seconds
Started Aug 07 06:24:14 PM PDT 24
Finished Aug 07 06:24:16 PM PDT 24
Peak memory 215336 kb
Host smart-836cee5f-bb09-4fcc-b97c-1dd8df33894a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126640787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
126640787
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2240462811
Short name T1027
Test name
Test status
Simulation time 28163398 ps
CPU time 0.77 seconds
Started Aug 07 06:24:12 PM PDT 24
Finished Aug 07 06:24:13 PM PDT 24
Peak memory 203672 kb
Host smart-516f06df-df3d-4c26-82f5-455513eda7b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240462811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
240462811
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2715520741
Short name T136
Test name
Test status
Simulation time 825845745 ps
CPU time 4.22 seconds
Started Aug 07 06:24:24 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 215192 kb
Host smart-99292b00-d5cd-4618-aa9b-e7b76c26e0fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715520741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2715520741
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2217516074
Short name T1118
Test name
Test status
Simulation time 751306407 ps
CPU time 4.87 seconds
Started Aug 07 06:24:07 PM PDT 24
Finished Aug 07 06:24:12 PM PDT 24
Peak memory 215356 kb
Host smart-593189fa-cdcb-4a00-86f6-8f561c676352
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217516074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
217516074
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1038827814
Short name T164
Test name
Test status
Simulation time 709673774 ps
CPU time 12.53 seconds
Started Aug 07 06:24:19 PM PDT 24
Finished Aug 07 06:24:31 PM PDT 24
Peak memory 215156 kb
Host smart-0c2d7155-7e48-43ff-812f-b64c08b67511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038827814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1038827814
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1962992675
Short name T1032
Test name
Test status
Simulation time 54485634 ps
CPU time 2.06 seconds
Started Aug 07 06:24:17 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 216220 kb
Host smart-3f8591e9-2b41-4cd4-a4e4-06987f808157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962992675 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1962992675
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1396740419
Short name T107
Test name
Test status
Simulation time 256293565 ps
CPU time 2.39 seconds
Started Aug 07 06:24:10 PM PDT 24
Finished Aug 07 06:24:12 PM PDT 24
Peak memory 215144 kb
Host smart-13a9bee6-24d0-4bef-a748-1227145cef1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396740419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
396740419
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4085493719
Short name T1043
Test name
Test status
Simulation time 17701936 ps
CPU time 0.71 seconds
Started Aug 07 06:24:15 PM PDT 24
Finished Aug 07 06:24:16 PM PDT 24
Peak memory 203704 kb
Host smart-f8f2b722-7f48-4a78-a97a-eafa3d107cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085493719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
085493719
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2028607476
Short name T1012
Test name
Test status
Simulation time 210679183 ps
CPU time 3.79 seconds
Started Aug 07 06:24:10 PM PDT 24
Finished Aug 07 06:24:14 PM PDT 24
Peak memory 215232 kb
Host smart-a6e156c7-01ef-40ab-9850-97dbf64aba08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028607476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2028607476
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1902602114
Short name T1106
Test name
Test status
Simulation time 54261767 ps
CPU time 1.67 seconds
Started Aug 07 06:24:10 PM PDT 24
Finished Aug 07 06:24:12 PM PDT 24
Peak memory 216300 kb
Host smart-bca369e3-ee18-44ee-be9d-51ad6763e872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902602114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
902602114
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1700506373
Short name T160
Test name
Test status
Simulation time 1180362449 ps
CPU time 18.48 seconds
Started Aug 07 06:24:09 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 215244 kb
Host smart-f539f797-12d7-4e22-a6c1-a4748fc7aaee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700506373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1700506373
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4009743122
Short name T109
Test name
Test status
Simulation time 161049337 ps
CPU time 1.27 seconds
Started Aug 07 06:24:10 PM PDT 24
Finished Aug 07 06:24:11 PM PDT 24
Peak memory 206964 kb
Host smart-0638c48f-5d3c-4c44-9aee-ec9a6f8325ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009743122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
009743122
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2567074242
Short name T1010
Test name
Test status
Simulation time 39167631 ps
CPU time 0.73 seconds
Started Aug 07 06:24:09 PM PDT 24
Finished Aug 07 06:24:10 PM PDT 24
Peak memory 203664 kb
Host smart-dacdd4a4-dcbc-4203-9c9c-c9942ad014da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567074242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
567074242
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.582150422
Short name T1073
Test name
Test status
Simulation time 563682950 ps
CPU time 3.16 seconds
Started Aug 07 06:24:11 PM PDT 24
Finished Aug 07 06:24:15 PM PDT 24
Peak memory 215152 kb
Host smart-aae577ba-7d68-4df5-8ca9-611a47a16698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582150422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.582150422
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1251807836
Short name T1079
Test name
Test status
Simulation time 430481386 ps
CPU time 3.89 seconds
Started Aug 07 06:24:09 PM PDT 24
Finished Aug 07 06:24:13 PM PDT 24
Peak memory 215308 kb
Host smart-a1ebe54c-89ad-4dd2-a92c-b95ca13c505c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251807836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
251807836
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2869964317
Short name T152
Test name
Test status
Simulation time 3743710124 ps
CPU time 19.42 seconds
Started Aug 07 06:24:11 PM PDT 24
Finished Aug 07 06:24:31 PM PDT 24
Peak memory 215328 kb
Host smart-fe145556-2b34-46a7-8db0-0443fc0c48af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869964317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2869964317
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2722581387
Short name T1064
Test name
Test status
Simulation time 139500233 ps
CPU time 2.85 seconds
Started Aug 07 06:24:18 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 217708 kb
Host smart-223f276d-a431-4e73-a499-acd3623db82c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722581387 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2722581387
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2885433156
Short name T1083
Test name
Test status
Simulation time 82487816 ps
CPU time 2.43 seconds
Started Aug 07 06:24:10 PM PDT 24
Finished Aug 07 06:24:12 PM PDT 24
Peak memory 215188 kb
Host smart-8198f80e-90d7-426c-a10b-8c6029c25bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885433156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
885433156
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1263635764
Short name T1099
Test name
Test status
Simulation time 120966296 ps
CPU time 0.79 seconds
Started Aug 07 06:24:11 PM PDT 24
Finished Aug 07 06:24:12 PM PDT 24
Peak memory 203648 kb
Host smart-b729dd74-700f-4fc8-bcd8-10f58905607c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263635764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
263635764
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2584075029
Short name T1048
Test name
Test status
Simulation time 27595821 ps
CPU time 1.76 seconds
Started Aug 07 06:24:17 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 215196 kb
Host smart-6bd8a94c-20f8-4e37-856a-4a324ce567e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584075029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2584075029
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1421987314
Short name T90
Test name
Test status
Simulation time 87934728 ps
CPU time 5.14 seconds
Started Aug 07 06:24:07 PM PDT 24
Finished Aug 07 06:24:13 PM PDT 24
Peak memory 215248 kb
Host smart-11b32d11-7433-439e-b09f-f1e7b40bbe2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421987314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
421987314
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1507327544
Short name T141
Test name
Test status
Simulation time 4320156240 ps
CPU time 15.83 seconds
Started Aug 07 06:24:08 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 215296 kb
Host smart-ca6321ef-09b1-4ad2-af6a-0195c5b0eaee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507327544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1507327544
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2783583460
Short name T1070
Test name
Test status
Simulation time 401240268 ps
CPU time 2.6 seconds
Started Aug 07 06:24:29 PM PDT 24
Finished Aug 07 06:24:32 PM PDT 24
Peak memory 216280 kb
Host smart-a31e52a1-3333-445e-b9de-a645471ca8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783583460 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2783583460
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.293032818
Short name T1103
Test name
Test status
Simulation time 219484170 ps
CPU time 1.26 seconds
Started Aug 07 06:24:22 PM PDT 24
Finished Aug 07 06:24:24 PM PDT 24
Peak memory 215192 kb
Host smart-385e3d69-6b58-437f-83d7-f0bf843bf6bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293032818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.293032818
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1399461559
Short name T1011
Test name
Test status
Simulation time 20466611 ps
CPU time 0.69 seconds
Started Aug 07 06:24:28 PM PDT 24
Finished Aug 07 06:24:29 PM PDT 24
Peak memory 203976 kb
Host smart-ce9e943f-bd05-41c8-a8bc-7648a1d64816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399461559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
399461559
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1748499052
Short name T139
Test name
Test status
Simulation time 548401386 ps
CPU time 2.06 seconds
Started Aug 07 06:24:13 PM PDT 24
Finished Aug 07 06:24:15 PM PDT 24
Peak memory 215176 kb
Host smart-b96bf232-5a3a-4464-938e-499fcaa8fcac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748499052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1748499052
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2221298293
Short name T1109
Test name
Test status
Simulation time 339842083 ps
CPU time 1.84 seconds
Started Aug 07 06:24:14 PM PDT 24
Finished Aug 07 06:24:16 PM PDT 24
Peak memory 215380 kb
Host smart-cd509059-c81e-4ea6-bf53-3abde108d6c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221298293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
221298293
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3859884352
Short name T1060
Test name
Test status
Simulation time 1358825980 ps
CPU time 8.16 seconds
Started Aug 07 06:24:13 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 215172 kb
Host smart-b440884b-4c76-4d34-99b0-e6d296de6cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859884352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3859884352
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3484066582
Short name T749
Test name
Test status
Simulation time 65852202 ps
CPU time 0.72 seconds
Started Aug 07 06:45:34 PM PDT 24
Finished Aug 07 06:45:35 PM PDT 24
Peak memory 205872 kb
Host smart-a67cbb5a-74f0-4f5d-8331-54305077b387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484066582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
484066582
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3503302300
Short name T446
Test name
Test status
Simulation time 130757672 ps
CPU time 2.71 seconds
Started Aug 07 06:45:34 PM PDT 24
Finished Aug 07 06:45:37 PM PDT 24
Peak memory 224844 kb
Host smart-2888456d-b0bc-4b69-8344-c117fb03db3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503302300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3503302300
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1707945602
Short name T963
Test name
Test status
Simulation time 103260822 ps
CPU time 0.75 seconds
Started Aug 07 06:45:27 PM PDT 24
Finished Aug 07 06:45:28 PM PDT 24
Peak memory 205944 kb
Host smart-56f72c54-1187-4bc6-ad70-3d0addca5950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707945602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1707945602
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.406456457
Short name T264
Test name
Test status
Simulation time 13490662577 ps
CPU time 86.41 seconds
Started Aug 07 06:45:35 PM PDT 24
Finished Aug 07 06:47:01 PM PDT 24
Peak memory 241384 kb
Host smart-59c95e6c-55ba-4e56-83d8-e1749e97ee53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406456457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.406456457
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1197109789
Short name T270
Test name
Test status
Simulation time 80041765551 ps
CPU time 677.69 seconds
Started Aug 07 06:45:33 PM PDT 24
Finished Aug 07 06:56:51 PM PDT 24
Peak memory 274204 kb
Host smart-1aa67fae-2f77-4d1e-957e-c55b2621e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197109789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1197109789
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3135056974
Short name T342
Test name
Test status
Simulation time 111385077553 ps
CPU time 36.54 seconds
Started Aug 07 06:45:33 PM PDT 24
Finished Aug 07 06:46:10 PM PDT 24
Peak memory 219316 kb
Host smart-ee57c9a8-acf8-4b3b-a881-99124d652077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135056974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3135056974
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.179325788
Short name T887
Test name
Test status
Simulation time 1673677057 ps
CPU time 25.24 seconds
Started Aug 07 06:45:34 PM PDT 24
Finished Aug 07 06:45:59 PM PDT 24
Peak memory 233220 kb
Host smart-6b4517ad-686e-4370-981f-d027d814d3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179325788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.179325788
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3582150460
Short name T936
Test name
Test status
Simulation time 8515642839 ps
CPU time 56.85 seconds
Started Aug 07 06:45:33 PM PDT 24
Finished Aug 07 06:46:30 PM PDT 24
Peak memory 256864 kb
Host smart-88f82a80-c790-4995-b853-ede2344756f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582150460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3582150460
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3286780153
Short name T548
Test name
Test status
Simulation time 1384938506 ps
CPU time 15.59 seconds
Started Aug 07 06:45:33 PM PDT 24
Finished Aug 07 06:45:49 PM PDT 24
Peak memory 225104 kb
Host smart-223b723c-0ca6-4356-83cf-9930e35797c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286780153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3286780153
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1946101194
Short name T330
Test name
Test status
Simulation time 4677532143 ps
CPU time 11.33 seconds
Started Aug 07 06:45:28 PM PDT 24
Finished Aug 07 06:45:40 PM PDT 24
Peak memory 224980 kb
Host smart-02416220-b5ed-4e5e-916e-be1486953c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946101194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1946101194
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2892321146
Short name T248
Test name
Test status
Simulation time 353669428 ps
CPU time 3.09 seconds
Started Aug 07 06:45:32 PM PDT 24
Finished Aug 07 06:45:36 PM PDT 24
Peak memory 224876 kb
Host smart-765d7e1d-9cc8-4be4-935f-57287735e71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892321146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2892321146
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2335099324
Short name T528
Test name
Test status
Simulation time 37997896936 ps
CPU time 18.15 seconds
Started Aug 07 06:45:26 PM PDT 24
Finished Aug 07 06:45:44 PM PDT 24
Peak memory 224856 kb
Host smart-8d75d83a-596f-43f4-b74b-b4b9708cef59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335099324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2335099324
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.409592325
Short name T336
Test name
Test status
Simulation time 12369781 ps
CPU time 0.73 seconds
Started Aug 07 06:45:26 PM PDT 24
Finished Aug 07 06:45:27 PM PDT 24
Peak memory 206100 kb
Host smart-e2805960-cfc8-4aff-990a-d58884a2a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409592325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.409592325
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1738631103
Short name T712
Test name
Test status
Simulation time 1563074276 ps
CPU time 5.61 seconds
Started Aug 07 06:45:32 PM PDT 24
Finished Aug 07 06:45:38 PM PDT 24
Peak memory 216636 kb
Host smart-4ab27e20-c422-4fbd-a9c4-9202c68ed781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738631103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1738631103
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.694200170
Short name T957
Test name
Test status
Simulation time 91120431 ps
CPU time 0.86 seconds
Started Aug 07 06:45:26 PM PDT 24
Finished Aug 07 06:45:27 PM PDT 24
Peak memory 206868 kb
Host smart-a1941a1b-cc8c-4de3-8b9d-d63321c54a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694200170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.694200170
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2889235760
Short name T484
Test name
Test status
Simulation time 49033502 ps
CPU time 0.77 seconds
Started Aug 07 06:45:31 PM PDT 24
Finished Aug 07 06:45:32 PM PDT 24
Peak memory 206344 kb
Host smart-ca35c4e0-d4c1-4d96-b996-7430856421d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889235760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2889235760
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3013876312
Short name T223
Test name
Test status
Simulation time 883538143 ps
CPU time 7.15 seconds
Started Aug 07 06:45:34 PM PDT 24
Finished Aug 07 06:45:41 PM PDT 24
Peak memory 233356 kb
Host smart-398693ab-e737-4fbd-bf43-35c4006c247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013876312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3013876312
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3588296688
Short name T941
Test name
Test status
Simulation time 40272595 ps
CPU time 0.71 seconds
Started Aug 07 06:45:50 PM PDT 24
Finished Aug 07 06:45:51 PM PDT 24
Peak memory 206020 kb
Host smart-5b8ab7b5-fcfa-4e3c-9b85-548d8b74074f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588296688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
588296688
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1282865610
Short name T229
Test name
Test status
Simulation time 37477801 ps
CPU time 2.52 seconds
Started Aug 07 06:45:38 PM PDT 24
Finished Aug 07 06:45:40 PM PDT 24
Peak memory 233160 kb
Host smart-f4a4d8aa-eb31-4245-9c95-f391dc58c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282865610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1282865610
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1470433788
Short name T773
Test name
Test status
Simulation time 16278397 ps
CPU time 0.77 seconds
Started Aug 07 06:45:35 PM PDT 24
Finished Aug 07 06:45:35 PM PDT 24
Peak memory 207268 kb
Host smart-f09a0fa7-254e-4185-818b-a1c5a402fb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470433788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1470433788
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2111114674
Short name T985
Test name
Test status
Simulation time 6753770907 ps
CPU time 24.09 seconds
Started Aug 07 06:45:38 PM PDT 24
Finished Aug 07 06:46:03 PM PDT 24
Peak memory 225008 kb
Host smart-376ec247-2c48-426a-b1e0-a51524d34999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111114674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2111114674
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.4156889766
Short name T122
Test name
Test status
Simulation time 23765771752 ps
CPU time 268.95 seconds
Started Aug 07 06:45:38 PM PDT 24
Finished Aug 07 06:50:07 PM PDT 24
Peak memory 257740 kb
Host smart-3339ed01-437d-47b4-ba88-1934f73738c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156889766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.4156889766
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.714940055
Short name T205
Test name
Test status
Simulation time 106814539577 ps
CPU time 253.07 seconds
Started Aug 07 06:45:38 PM PDT 24
Finished Aug 07 06:49:51 PM PDT 24
Peak memory 249664 kb
Host smart-930cee12-7012-42b8-a93e-65a77e762639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714940055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
714940055
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3726918858
Short name T239
Test name
Test status
Simulation time 362911221859 ps
CPU time 582.74 seconds
Started Aug 07 06:45:38 PM PDT 24
Finished Aug 07 06:55:21 PM PDT 24
Peak memory 250660 kb
Host smart-ca285e97-3612-44dc-a1bb-96f0eeaad5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726918858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3726918858
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.265187233
Short name T184
Test name
Test status
Simulation time 5725434833 ps
CPU time 16.79 seconds
Started Aug 07 06:45:41 PM PDT 24
Finished Aug 07 06:45:58 PM PDT 24
Peak memory 219304 kb
Host smart-bebee3aa-2435-4502-9666-ae18c1b1dfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265187233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.265187233
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.891447975
Short name T366
Test name
Test status
Simulation time 109084880 ps
CPU time 2.38 seconds
Started Aug 07 06:45:42 PM PDT 24
Finished Aug 07 06:45:44 PM PDT 24
Peak memory 224616 kb
Host smart-cf80212c-7847-40bd-a745-2ace59dea96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891447975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.891447975
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2180140546
Short name T183
Test name
Test status
Simulation time 12264377402 ps
CPU time 19.57 seconds
Started Aug 07 06:45:38 PM PDT 24
Finished Aug 07 06:45:58 PM PDT 24
Peak memory 233172 kb
Host smart-9feff4bb-d8e4-48a2-8ce6-67cc6c5d06d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180140546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2180140546
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.616848650
Short name T345
Test name
Test status
Simulation time 3801585752 ps
CPU time 12.65 seconds
Started Aug 07 06:45:38 PM PDT 24
Finished Aug 07 06:45:51 PM PDT 24
Peak memory 225044 kb
Host smart-28dc4f13-f211-434c-bdf2-bf03ca9b5251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616848650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.616848650
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3571414064
Short name T960
Test name
Test status
Simulation time 8895014953 ps
CPU time 19.16 seconds
Started Aug 07 06:45:37 PM PDT 24
Finished Aug 07 06:45:57 PM PDT 24
Peak memory 222104 kb
Host smart-d815830d-cf53-4240-bd58-37953ab0803b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3571414064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3571414064
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2013137207
Short name T59
Test name
Test status
Simulation time 57373331 ps
CPU time 1.06 seconds
Started Aug 07 06:45:43 PM PDT 24
Finished Aug 07 06:45:44 PM PDT 24
Peak memory 235856 kb
Host smart-e46c9c5f-89f2-41a5-b0a3-e48cabaf804a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013137207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2013137207
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1346927809
Short name T680
Test name
Test status
Simulation time 101722901 ps
CPU time 1.05 seconds
Started Aug 07 06:45:44 PM PDT 24
Finished Aug 07 06:45:45 PM PDT 24
Peak memory 208084 kb
Host smart-bcd390a2-dfd2-4621-ab5b-642605eccb16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346927809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1346927809
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.379742549
Short name T461
Test name
Test status
Simulation time 5178573107 ps
CPU time 30.35 seconds
Started Aug 07 06:45:39 PM PDT 24
Finished Aug 07 06:46:09 PM PDT 24
Peak memory 216776 kb
Host smart-6a86f9d1-f7c2-4a80-a316-bdc2fb5d88b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379742549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.379742549
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2552812680
Short name T396
Test name
Test status
Simulation time 1526340530 ps
CPU time 7.55 seconds
Started Aug 07 06:45:39 PM PDT 24
Finished Aug 07 06:45:47 PM PDT 24
Peak memory 216668 kb
Host smart-79792c04-2c22-489c-864c-07d5c65a3093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552812680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2552812680
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1519053150
Short name T787
Test name
Test status
Simulation time 151754316 ps
CPU time 3.23 seconds
Started Aug 07 06:45:39 PM PDT 24
Finished Aug 07 06:45:42 PM PDT 24
Peak memory 216636 kb
Host smart-66a22def-29af-4e06-ba30-717ae2389093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519053150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1519053150
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2287404857
Short name T774
Test name
Test status
Simulation time 23003899 ps
CPU time 0.81 seconds
Started Aug 07 06:45:37 PM PDT 24
Finished Aug 07 06:45:38 PM PDT 24
Peak memory 206428 kb
Host smart-b54fb9c6-8291-4da5-8ebc-2818f4720a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287404857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2287404857
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4026716906
Short name T482
Test name
Test status
Simulation time 3357915277 ps
CPU time 8.06 seconds
Started Aug 07 06:45:38 PM PDT 24
Finished Aug 07 06:45:46 PM PDT 24
Peak memory 219288 kb
Host smart-2f6f1fdb-bae4-4af0-8152-86f1b450dc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026716906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4026716906
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2254911021
Short name T970
Test name
Test status
Simulation time 19628930 ps
CPU time 0.7 seconds
Started Aug 07 06:47:08 PM PDT 24
Finished Aug 07 06:47:09 PM PDT 24
Peak memory 205844 kb
Host smart-358ecba1-734b-4d02-8b60-0159df414ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254911021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2254911021
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3604345274
Short name T457
Test name
Test status
Simulation time 688332023 ps
CPU time 2.65 seconds
Started Aug 07 06:47:02 PM PDT 24
Finished Aug 07 06:47:05 PM PDT 24
Peak memory 224896 kb
Host smart-35006227-9a0c-4d7f-9507-7e8e0cbb44d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604345274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3604345274
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3457896405
Short name T133
Test name
Test status
Simulation time 50843978 ps
CPU time 0.74 seconds
Started Aug 07 06:46:57 PM PDT 24
Finished Aug 07 06:46:58 PM PDT 24
Peak memory 206256 kb
Host smart-ecd41d12-8f0d-4a97-980c-46f2915c8dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457896405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3457896405
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.340600243
Short name T492
Test name
Test status
Simulation time 40291414862 ps
CPU time 155.88 seconds
Started Aug 07 06:47:04 PM PDT 24
Finished Aug 07 06:49:40 PM PDT 24
Peak memory 269308 kb
Host smart-ca224f5f-2d05-4f78-a16b-2f3efd9205a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340600243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.340600243
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.872367071
Short name T857
Test name
Test status
Simulation time 15844449075 ps
CPU time 116.97 seconds
Started Aug 07 06:47:08 PM PDT 24
Finished Aug 07 06:49:05 PM PDT 24
Peak memory 270968 kb
Host smart-01e675fa-7aa3-440f-b3d5-6efe3c328883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872367071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.872367071
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2436004227
Short name T154
Test name
Test status
Simulation time 19938905527 ps
CPU time 214.47 seconds
Started Aug 07 06:47:08 PM PDT 24
Finished Aug 07 06:50:42 PM PDT 24
Peak memory 250656 kb
Host smart-a409c99e-2583-4638-a2a6-e7078805de21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436004227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2436004227
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.888055182
Short name T430
Test name
Test status
Simulation time 1983650347 ps
CPU time 11.71 seconds
Started Aug 07 06:47:02 PM PDT 24
Finished Aug 07 06:47:14 PM PDT 24
Peak memory 249552 kb
Host smart-9393023d-586c-4889-a5e5-c75650a36584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888055182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.888055182
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2481828958
Short name T530
Test name
Test status
Simulation time 634858934 ps
CPU time 7.84 seconds
Started Aug 07 06:46:57 PM PDT 24
Finished Aug 07 06:47:05 PM PDT 24
Peak memory 233124 kb
Host smart-06ec7495-2b46-4dc4-8cec-41ed1317e425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481828958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2481828958
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1570375758
Short name T455
Test name
Test status
Simulation time 287554413 ps
CPU time 2.29 seconds
Started Aug 07 06:47:02 PM PDT 24
Finished Aug 07 06:47:05 PM PDT 24
Peak memory 224496 kb
Host smart-74d11c01-2103-4455-8ed7-983b58ec11c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570375758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1570375758
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3618827420
Short name T557
Test name
Test status
Simulation time 219547590 ps
CPU time 4.33 seconds
Started Aug 07 06:46:57 PM PDT 24
Finished Aug 07 06:47:01 PM PDT 24
Peak memory 237296 kb
Host smart-4a1bcd0a-f18d-4a4a-89a6-c48aa7296ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618827420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3618827420
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3684742825
Short name T262
Test name
Test status
Simulation time 604586909 ps
CPU time 9.07 seconds
Started Aug 07 06:46:59 PM PDT 24
Finished Aug 07 06:47:08 PM PDT 24
Peak memory 241152 kb
Host smart-12072b1d-74f3-412c-9322-9e76df296be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684742825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3684742825
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.776632557
Short name T32
Test name
Test status
Simulation time 5716285254 ps
CPU time 14.57 seconds
Started Aug 07 06:47:04 PM PDT 24
Finished Aug 07 06:47:19 PM PDT 24
Peak memory 222280 kb
Host smart-959968f9-c3d7-430a-8bce-5e79afbe9b1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=776632557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.776632557
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3961045493
Short name T121
Test name
Test status
Simulation time 27953020134 ps
CPU time 253.09 seconds
Started Aug 07 06:47:08 PM PDT 24
Finished Aug 07 06:51:21 PM PDT 24
Peak memory 257052 kb
Host smart-ee255b7a-4c4a-4859-aec2-ad28321bd7d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961045493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3961045493
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3064527607
Short name T703
Test name
Test status
Simulation time 133224394406 ps
CPU time 44.58 seconds
Started Aug 07 06:46:57 PM PDT 24
Finished Aug 07 06:47:42 PM PDT 24
Peak memory 220564 kb
Host smart-188a3282-ebd2-49af-b798-cf97e17bb636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064527607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3064527607
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1685254517
Short name T739
Test name
Test status
Simulation time 1226038801 ps
CPU time 3.08 seconds
Started Aug 07 06:46:59 PM PDT 24
Finished Aug 07 06:47:02 PM PDT 24
Peak memory 216604 kb
Host smart-e6725bcc-e902-4a27-b1e6-4ef6fbe8b137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685254517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1685254517
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2796371174
Short name T918
Test name
Test status
Simulation time 19095185 ps
CPU time 1.07 seconds
Started Aug 07 06:46:58 PM PDT 24
Finished Aug 07 06:46:59 PM PDT 24
Peak memory 207868 kb
Host smart-2adc5031-e2ba-464c-9626-8a1398211c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796371174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2796371174
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.248270969
Short name T598
Test name
Test status
Simulation time 29125124 ps
CPU time 0.76 seconds
Started Aug 07 06:46:58 PM PDT 24
Finished Aug 07 06:46:58 PM PDT 24
Peak memory 206604 kb
Host smart-af37bca7-24ed-45ea-9e9b-61dee61eaa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248270969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.248270969
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.4097300709
Short name T791
Test name
Test status
Simulation time 205613191 ps
CPU time 2.54 seconds
Started Aug 07 06:47:03 PM PDT 24
Finished Aug 07 06:47:06 PM PDT 24
Peak memory 224860 kb
Host smart-a26a549c-b9de-4ab6-97a3-d5b2a254b257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097300709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4097300709
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.304119466
Short name T316
Test name
Test status
Simulation time 14180232 ps
CPU time 0.69 seconds
Started Aug 07 06:47:19 PM PDT 24
Finished Aug 07 06:47:20 PM PDT 24
Peak memory 206060 kb
Host smart-d9e6860b-b17a-46b8-8b47-ac676da89dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304119466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.304119466
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1658315355
Short name T522
Test name
Test status
Simulation time 57368347 ps
CPU time 2.41 seconds
Started Aug 07 06:47:14 PM PDT 24
Finished Aug 07 06:47:16 PM PDT 24
Peak memory 232824 kb
Host smart-b47fcc5e-3e77-47d5-a9e1-40e33151de2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658315355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1658315355
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1959334298
Short name T995
Test name
Test status
Simulation time 49106725 ps
CPU time 0.76 seconds
Started Aug 07 06:47:06 PM PDT 24
Finished Aug 07 06:47:07 PM PDT 24
Peak memory 205988 kb
Host smart-cb9692f0-12df-4822-805a-82cf008b220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959334298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1959334298
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3243483069
Short name T803
Test name
Test status
Simulation time 20611001 ps
CPU time 0.78 seconds
Started Aug 07 06:47:19 PM PDT 24
Finished Aug 07 06:47:20 PM PDT 24
Peak memory 216136 kb
Host smart-a6282210-4ec0-44bf-815c-a1823c5e0dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243483069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3243483069
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2194904542
Short name T170
Test name
Test status
Simulation time 4681186438 ps
CPU time 60.02 seconds
Started Aug 07 06:47:19 PM PDT 24
Finished Aug 07 06:48:19 PM PDT 24
Peak memory 251148 kb
Host smart-3cd1cb6f-de1f-4c52-be34-e7f1f8a40873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194904542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2194904542
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.991864881
Short name T758
Test name
Test status
Simulation time 4027613752 ps
CPU time 26.79 seconds
Started Aug 07 06:47:14 PM PDT 24
Finished Aug 07 06:47:40 PM PDT 24
Peak memory 224996 kb
Host smart-83048b22-0e02-4000-b123-5e451d5729f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991864881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.991864881
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.943017173
Short name T390
Test name
Test status
Simulation time 31361600 ps
CPU time 0.74 seconds
Started Aug 07 06:47:14 PM PDT 24
Finished Aug 07 06:47:15 PM PDT 24
Peak memory 216112 kb
Host smart-9f0c3e98-49ec-43f0-bd71-970fe28805c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943017173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.943017173
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.521857511
Short name T182
Test name
Test status
Simulation time 1428370450 ps
CPU time 16.54 seconds
Started Aug 07 06:47:11 PM PDT 24
Finished Aug 07 06:47:28 PM PDT 24
Peak memory 233128 kb
Host smart-1652267a-e33f-419b-bedb-2fcae1a33964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521857511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.521857511
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.524793830
Short name T634
Test name
Test status
Simulation time 44421842546 ps
CPU time 103.18 seconds
Started Aug 07 06:47:13 PM PDT 24
Finished Aug 07 06:48:57 PM PDT 24
Peak memory 233184 kb
Host smart-7b629e7a-6e03-49db-882a-1d8e9d286656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524793830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.524793830
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.970142250
Short name T767
Test name
Test status
Simulation time 4483295932 ps
CPU time 14.27 seconds
Started Aug 07 06:47:14 PM PDT 24
Finished Aug 07 06:47:28 PM PDT 24
Peak memory 233152 kb
Host smart-75ea7d2e-c0c1-45b2-99c5-b4dc135e903c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970142250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.970142250
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.331664318
Short name T552
Test name
Test status
Simulation time 2649070787 ps
CPU time 5.49 seconds
Started Aug 07 06:47:07 PM PDT 24
Finished Aug 07 06:47:13 PM PDT 24
Peak memory 224912 kb
Host smart-180f6926-3816-437f-a6ae-a614e8ad145c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331664318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.331664318
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1765655414
Short name T498
Test name
Test status
Simulation time 2189374390 ps
CPU time 13.68 seconds
Started Aug 07 06:47:17 PM PDT 24
Finished Aug 07 06:47:31 PM PDT 24
Peak memory 223192 kb
Host smart-a6cf5b21-18c9-40c0-9f27-87648a4b5b3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1765655414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1765655414
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1164260750
Short name T799
Test name
Test status
Simulation time 38052021937 ps
CPU time 88.95 seconds
Started Aug 07 06:47:18 PM PDT 24
Finished Aug 07 06:48:47 PM PDT 24
Peak memory 249588 kb
Host smart-852ec327-3d64-41ac-9d80-ed7f61c72fd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164260750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1164260750
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3053600147
Short name T994
Test name
Test status
Simulation time 990577681 ps
CPU time 12.63 seconds
Started Aug 07 06:47:07 PM PDT 24
Finished Aug 07 06:47:20 PM PDT 24
Peak memory 216708 kb
Host smart-488fe070-a016-4ab4-b8ed-ca3efd699f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053600147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3053600147
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.430243647
Short name T730
Test name
Test status
Simulation time 1312913159 ps
CPU time 2.57 seconds
Started Aug 07 06:47:08 PM PDT 24
Finished Aug 07 06:47:11 PM PDT 24
Peak memory 216632 kb
Host smart-f3060413-2c32-4eaf-98bc-bc54cf1c0656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430243647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.430243647
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2808459850
Short name T367
Test name
Test status
Simulation time 429473415 ps
CPU time 0.95 seconds
Started Aug 07 06:47:06 PM PDT 24
Finished Aug 07 06:47:07 PM PDT 24
Peak memory 206876 kb
Host smart-983cb031-a737-4df1-b557-c562e9444085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808459850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2808459850
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.891442820
Short name T796
Test name
Test status
Simulation time 32071801 ps
CPU time 0.7 seconds
Started Aug 07 06:47:10 PM PDT 24
Finished Aug 07 06:47:10 PM PDT 24
Peak memory 205988 kb
Host smart-613d90e9-b35e-44af-be41-802985a48ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891442820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.891442820
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2626123190
Short name T567
Test name
Test status
Simulation time 19938576970 ps
CPU time 25.27 seconds
Started Aug 07 06:47:13 PM PDT 24
Finished Aug 07 06:47:39 PM PDT 24
Peak memory 233200 kb
Host smart-7a7ac1ff-4423-473e-91c6-11ff80e1c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626123190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2626123190
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1757048474
Short name T827
Test name
Test status
Simulation time 19175125 ps
CPU time 0.73 seconds
Started Aug 07 06:47:35 PM PDT 24
Finished Aug 07 06:47:35 PM PDT 24
Peak memory 205816 kb
Host smart-ef25a548-562a-45e6-979c-6cb40c0ffa85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757048474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1757048474
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.229824498
Short name T651
Test name
Test status
Simulation time 2341955709 ps
CPU time 14.57 seconds
Started Aug 07 06:47:24 PM PDT 24
Finished Aug 07 06:47:39 PM PDT 24
Peak memory 224988 kb
Host smart-a37ae102-77cf-47be-903a-b2e4561473a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229824498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.229824498
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.61804723
Short name T520
Test name
Test status
Simulation time 30773118 ps
CPU time 0.76 seconds
Started Aug 07 06:47:19 PM PDT 24
Finished Aug 07 06:47:20 PM PDT 24
Peak memory 206940 kb
Host smart-9cd5554c-1943-415f-98d5-6bbe7243c585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61804723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.61804723
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.273537755
Short name T835
Test name
Test status
Simulation time 85238611213 ps
CPU time 127.4 seconds
Started Aug 07 06:47:24 PM PDT 24
Finished Aug 07 06:49:32 PM PDT 24
Peak memory 238952 kb
Host smart-27574914-e3bb-4e9e-bd0d-82b612058deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273537755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.273537755
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.153872714
Short name T276
Test name
Test status
Simulation time 77589461016 ps
CPU time 94.25 seconds
Started Aug 07 06:47:35 PM PDT 24
Finished Aug 07 06:49:09 PM PDT 24
Peak memory 249352 kb
Host smart-c2e34752-b2e8-46df-aa36-605479079474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153872714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.153872714
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1545035468
Short name T967
Test name
Test status
Simulation time 1710391255 ps
CPU time 29.35 seconds
Started Aug 07 06:47:23 PM PDT 24
Finished Aug 07 06:47:53 PM PDT 24
Peak memory 249508 kb
Host smart-af982883-450a-4982-9178-ca23f61b2e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545035468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1545035468
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.4272007839
Short name T621
Test name
Test status
Simulation time 17876300079 ps
CPU time 71.47 seconds
Started Aug 07 06:47:25 PM PDT 24
Finished Aug 07 06:48:36 PM PDT 24
Peak memory 249600 kb
Host smart-59dc699d-27ba-410a-9998-9f5a9e9c3506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272007839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.4272007839
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.273051938
Short name T549
Test name
Test status
Simulation time 1289404536 ps
CPU time 8.83 seconds
Started Aug 07 06:47:24 PM PDT 24
Finished Aug 07 06:47:33 PM PDT 24
Peak memory 233024 kb
Host smart-0e7f9691-6233-47d8-9f87-368740065114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273051938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.273051938
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1470257468
Short name T198
Test name
Test status
Simulation time 208209612 ps
CPU time 2.5 seconds
Started Aug 07 06:47:28 PM PDT 24
Finished Aug 07 06:47:31 PM PDT 24
Peak memory 233124 kb
Host smart-3bd65abf-df1e-4974-975d-b8d0b4915ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470257468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1470257468
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3473596777
Short name T241
Test name
Test status
Simulation time 17013102887 ps
CPU time 11.16 seconds
Started Aug 07 06:47:22 PM PDT 24
Finished Aug 07 06:47:34 PM PDT 24
Peak memory 224940 kb
Host smart-30480705-3a8f-42de-92ef-f4da75ae92e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473596777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3473596777
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.957710213
Short name T660
Test name
Test status
Simulation time 3768286728 ps
CPU time 5 seconds
Started Aug 07 06:47:24 PM PDT 24
Finished Aug 07 06:47:29 PM PDT 24
Peak memory 233244 kb
Host smart-00d9062f-2424-4369-bcf3-b605e4526e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957710213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.957710213
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.794462575
Short name T890
Test name
Test status
Simulation time 570713150 ps
CPU time 6.79 seconds
Started Aug 07 06:47:23 PM PDT 24
Finished Aug 07 06:47:30 PM PDT 24
Peak memory 223060 kb
Host smart-1fe1270f-0131-422e-8f00-439ff730d066
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=794462575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.794462575
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.379040907
Short name T43
Test name
Test status
Simulation time 17203984446 ps
CPU time 86.67 seconds
Started Aug 07 06:47:28 PM PDT 24
Finished Aug 07 06:48:55 PM PDT 24
Peak memory 256944 kb
Host smart-f6a61156-9fe3-4ff1-90e3-a440f785b4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379040907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.379040907
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3481382741
Short name T965
Test name
Test status
Simulation time 11018119496 ps
CPU time 17.09 seconds
Started Aug 07 06:47:20 PM PDT 24
Finished Aug 07 06:47:37 PM PDT 24
Peak memory 216720 kb
Host smart-397b6d21-221b-4712-9154-1bc032e902a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481382741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3481382741
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3910991387
Short name T928
Test name
Test status
Simulation time 12346309905 ps
CPU time 16.33 seconds
Started Aug 07 06:47:19 PM PDT 24
Finished Aug 07 06:47:35 PM PDT 24
Peak memory 216748 kb
Host smart-5f1ce634-b417-458e-aa69-20b7ab333557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910991387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3910991387
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2073363504
Short name T810
Test name
Test status
Simulation time 21924014 ps
CPU time 0.67 seconds
Started Aug 07 06:47:18 PM PDT 24
Finished Aug 07 06:47:19 PM PDT 24
Peak memory 205976 kb
Host smart-1d6557c9-c6be-4712-8c9e-61036f870a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073363504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2073363504
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3525519120
Short name T770
Test name
Test status
Simulation time 59933888 ps
CPU time 0.9 seconds
Started Aug 07 06:47:20 PM PDT 24
Finished Aug 07 06:47:21 PM PDT 24
Peak memory 206352 kb
Host smart-29015a85-ef82-46f0-9d63-adb1c7df59b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525519120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3525519120
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1307309965
Short name T547
Test name
Test status
Simulation time 280166356 ps
CPU time 5.57 seconds
Started Aug 07 06:47:23 PM PDT 24
Finished Aug 07 06:47:29 PM PDT 24
Peak memory 233112 kb
Host smart-37fcd683-b325-4f3a-9bd2-42717a186e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307309965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1307309965
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4098501459
Short name T344
Test name
Test status
Simulation time 44505746 ps
CPU time 0.73 seconds
Started Aug 07 06:47:39 PM PDT 24
Finished Aug 07 06:47:40 PM PDT 24
Peak memory 205808 kb
Host smart-7cb6f141-4c1c-4839-b1ae-23f54bfbed62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098501459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4098501459
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3656815563
Short name T261
Test name
Test status
Simulation time 173530190 ps
CPU time 4.34 seconds
Started Aug 07 06:47:34 PM PDT 24
Finished Aug 07 06:47:38 PM PDT 24
Peak memory 233092 kb
Host smart-9af19c4b-4793-4551-b103-3049d4dd1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656815563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3656815563
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3006245318
Short name T764
Test name
Test status
Simulation time 67111349 ps
CPU time 0.81 seconds
Started Aug 07 06:47:29 PM PDT 24
Finished Aug 07 06:47:30 PM PDT 24
Peak memory 206964 kb
Host smart-8e3e3059-8a4b-48cd-b323-9c359c4d94af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006245318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3006245318
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1160425120
Short name T195
Test name
Test status
Simulation time 34162153621 ps
CPU time 84.3 seconds
Started Aug 07 06:47:36 PM PDT 24
Finished Aug 07 06:49:00 PM PDT 24
Peak memory 256800 kb
Host smart-364edecc-0e81-478b-9f25-3e8e51138fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160425120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1160425120
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.824197584
Short name T355
Test name
Test status
Simulation time 328083787 ps
CPU time 4.9 seconds
Started Aug 07 06:47:33 PM PDT 24
Finished Aug 07 06:47:38 PM PDT 24
Peak memory 224956 kb
Host smart-28d853e6-e0f0-4748-8cda-d5e6b90a9064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824197584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.824197584
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3277466433
Short name T226
Test name
Test status
Simulation time 2575830225 ps
CPU time 21.12 seconds
Started Aug 07 06:47:33 PM PDT 24
Finished Aug 07 06:47:54 PM PDT 24
Peak memory 234744 kb
Host smart-8c3580f8-e611-48c2-a91a-99a3fb3947d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277466433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3277466433
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4179915977
Short name T150
Test name
Test status
Simulation time 3349195467 ps
CPU time 9.33 seconds
Started Aug 07 06:47:33 PM PDT 24
Finished Aug 07 06:47:42 PM PDT 24
Peak memory 224940 kb
Host smart-c6db9c6f-123b-4ef0-bd90-f7230379b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179915977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4179915977
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.236817885
Short name T828
Test name
Test status
Simulation time 7075273637 ps
CPU time 12.27 seconds
Started Aug 07 06:47:34 PM PDT 24
Finished Aug 07 06:47:46 PM PDT 24
Peak memory 233148 kb
Host smart-d00ff779-2fc0-4f95-ac42-5294152ff787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236817885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.236817885
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1533370092
Short name T240
Test name
Test status
Simulation time 12254166481 ps
CPU time 5.64 seconds
Started Aug 07 06:47:39 PM PDT 24
Finished Aug 07 06:47:45 PM PDT 24
Peak memory 225172 kb
Host smart-2736c148-87da-47c1-8cf4-009445dce2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533370092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1533370092
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2789682095
Short name T583
Test name
Test status
Simulation time 388428633 ps
CPU time 4.97 seconds
Started Aug 07 06:47:34 PM PDT 24
Finished Aug 07 06:47:39 PM PDT 24
Peak memory 233188 kb
Host smart-6289f0cb-77ea-420b-9196-a23a668abad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789682095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2789682095
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2881769719
Short name T131
Test name
Test status
Simulation time 1885725317 ps
CPU time 7.87 seconds
Started Aug 07 06:47:33 PM PDT 24
Finished Aug 07 06:47:41 PM PDT 24
Peak memory 223624 kb
Host smart-fdb9ec67-5b39-48d4-9a24-7c244baac07f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2881769719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2881769719
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3773228871
Short name T627
Test name
Test status
Simulation time 122363073 ps
CPU time 1.12 seconds
Started Aug 07 06:47:34 PM PDT 24
Finished Aug 07 06:47:35 PM PDT 24
Peak memory 207632 kb
Host smart-87b5fbd3-5cf1-4730-8f89-778c989933f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773228871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3773228871
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1153945043
Short name T422
Test name
Test status
Simulation time 1849553759 ps
CPU time 9.08 seconds
Started Aug 07 06:47:30 PM PDT 24
Finished Aug 07 06:47:39 PM PDT 24
Peak memory 216608 kb
Host smart-bc8280f0-f42f-4eb0-ad17-837293a3eeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153945043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1153945043
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.941349536
Short name T521
Test name
Test status
Simulation time 20211627 ps
CPU time 0.91 seconds
Started Aug 07 06:47:28 PM PDT 24
Finished Aug 07 06:47:29 PM PDT 24
Peak memory 207412 kb
Host smart-228f47ec-7d55-46e4-8623-efdc5de3c131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941349536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.941349536
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1916080844
Short name T569
Test name
Test status
Simulation time 302429963 ps
CPU time 0.87 seconds
Started Aug 07 06:47:35 PM PDT 24
Finished Aug 07 06:47:36 PM PDT 24
Peak memory 207372 kb
Host smart-3b07ad86-a724-4805-a0d3-5350a752b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916080844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1916080844
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3456153487
Short name T188
Test name
Test status
Simulation time 5014891674 ps
CPU time 9.5 seconds
Started Aug 07 06:47:33 PM PDT 24
Finished Aug 07 06:47:43 PM PDT 24
Peak memory 230008 kb
Host smart-f3dca2bc-2cb6-4e9b-92b9-e5ff1f9a1dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456153487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3456153487
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.960593935
Short name T320
Test name
Test status
Simulation time 25179957 ps
CPU time 0.7 seconds
Started Aug 07 06:47:44 PM PDT 24
Finished Aug 07 06:47:45 PM PDT 24
Peak memory 205260 kb
Host smart-96c7d79f-e83b-486f-8808-24b47b34e5d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960593935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.960593935
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.852744625
Short name T628
Test name
Test status
Simulation time 67729523 ps
CPU time 2.78 seconds
Started Aug 07 06:47:44 PM PDT 24
Finished Aug 07 06:47:47 PM PDT 24
Peak memory 233180 kb
Host smart-bec2d2ee-1f3e-47ec-9c33-e3f22cae6913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852744625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.852744625
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.561541022
Short name T525
Test name
Test status
Simulation time 33610442 ps
CPU time 0.78 seconds
Started Aug 07 06:47:33 PM PDT 24
Finished Aug 07 06:47:34 PM PDT 24
Peak memory 205996 kb
Host smart-e613f4d6-705f-416a-a294-144e6087f466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561541022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.561541022
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3286502586
Short name T451
Test name
Test status
Simulation time 5742903077 ps
CPU time 7.97 seconds
Started Aug 07 06:47:44 PM PDT 24
Finished Aug 07 06:47:53 PM PDT 24
Peak memory 234968 kb
Host smart-eea30238-6136-414e-bd04-361d7386a54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286502586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3286502586
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3529787543
Short name T779
Test name
Test status
Simulation time 235161730298 ps
CPU time 194.49 seconds
Started Aug 07 06:47:44 PM PDT 24
Finished Aug 07 06:50:59 PM PDT 24
Peak memory 249676 kb
Host smart-52ab5255-c271-4948-ad4f-9f1d12612017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529787543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3529787543
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.113147547
Short name T282
Test name
Test status
Simulation time 42516230505 ps
CPU time 391.12 seconds
Started Aug 07 06:47:44 PM PDT 24
Finished Aug 07 06:54:16 PM PDT 24
Peak memory 249692 kb
Host smart-468bb301-40ec-4cf3-9a8c-60a38669bf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113147547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.113147547
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3303830440
Short name T296
Test name
Test status
Simulation time 2352105230 ps
CPU time 11.32 seconds
Started Aug 07 06:47:47 PM PDT 24
Finished Aug 07 06:47:58 PM PDT 24
Peak memory 234876 kb
Host smart-95bf3952-7221-45ac-a3c2-80050cf00b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303830440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3303830440
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3261940187
Short name T649
Test name
Test status
Simulation time 34282365170 ps
CPU time 83.86 seconds
Started Aug 07 06:47:44 PM PDT 24
Finished Aug 07 06:49:08 PM PDT 24
Peak memory 257664 kb
Host smart-cf4061af-a744-4af3-b74e-43f32761a915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261940187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3261940187
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.577587380
Short name T762
Test name
Test status
Simulation time 37232685 ps
CPU time 2.87 seconds
Started Aug 07 06:47:39 PM PDT 24
Finished Aug 07 06:47:42 PM PDT 24
Peak memory 233108 kb
Host smart-b1d20ee2-38f6-4091-beec-f30b611bfd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577587380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.577587380
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2607014083
Short name T847
Test name
Test status
Simulation time 415987482 ps
CPU time 5.76 seconds
Started Aug 07 06:47:40 PM PDT 24
Finished Aug 07 06:47:45 PM PDT 24
Peak memory 224884 kb
Host smart-ac495ddb-4be5-4965-9346-de4f64a478b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607014083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2607014083
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3946905724
Short name T798
Test name
Test status
Simulation time 6102084627 ps
CPU time 14.11 seconds
Started Aug 07 06:47:40 PM PDT 24
Finished Aug 07 06:47:55 PM PDT 24
Peak memory 241292 kb
Host smart-24d39dcf-e9cb-499c-9fe9-e6e932a22629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946905724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3946905724
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1653473523
Short name T786
Test name
Test status
Simulation time 62469325 ps
CPU time 2.58 seconds
Started Aug 07 06:47:39 PM PDT 24
Finished Aug 07 06:47:42 PM PDT 24
Peak memory 233120 kb
Host smart-b45e34e0-ebd5-41b8-adf3-abcc741b9bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653473523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1653473523
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4275010426
Short name T831
Test name
Test status
Simulation time 211978251 ps
CPU time 3.31 seconds
Started Aug 07 06:47:44 PM PDT 24
Finished Aug 07 06:47:48 PM PDT 24
Peak memory 221052 kb
Host smart-9875cfb1-c3c1-4838-b3b8-74d5417b8561
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4275010426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4275010426
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.156586787
Short name T300
Test name
Test status
Simulation time 3845973269 ps
CPU time 27.24 seconds
Started Aug 07 06:47:41 PM PDT 24
Finished Aug 07 06:48:08 PM PDT 24
Peak memory 216812 kb
Host smart-e1d82c11-e6b8-4a8d-b422-231459773af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156586787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.156586787
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3186769212
Short name T991
Test name
Test status
Simulation time 1360327353 ps
CPU time 3.62 seconds
Started Aug 07 06:47:40 PM PDT 24
Finished Aug 07 06:47:44 PM PDT 24
Peak memory 216648 kb
Host smart-c99e69cf-7a7c-470e-a8f2-fb1eec3f9040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186769212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3186769212
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.569712040
Short name T953
Test name
Test status
Simulation time 148885244 ps
CPU time 2.02 seconds
Started Aug 07 06:47:40 PM PDT 24
Finished Aug 07 06:47:42 PM PDT 24
Peak memory 216600 kb
Host smart-c6c61231-8073-420f-943e-1a7400050744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569712040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.569712040
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3619183320
Short name T846
Test name
Test status
Simulation time 112346163 ps
CPU time 0.8 seconds
Started Aug 07 06:47:39 PM PDT 24
Finished Aug 07 06:47:40 PM PDT 24
Peak memory 206324 kb
Host smart-ed53a98b-81aa-4e58-8b0a-f86ddb81b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619183320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3619183320
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1882040270
Short name T218
Test name
Test status
Simulation time 8038444018 ps
CPU time 10.17 seconds
Started Aug 07 06:47:47 PM PDT 24
Finished Aug 07 06:47:57 PM PDT 24
Peak memory 233132 kb
Host smart-f71f1119-aa20-4c74-afe6-eb0fb242dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882040270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1882040270
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3514508481
Short name T52
Test name
Test status
Simulation time 14275978 ps
CPU time 0.72 seconds
Started Aug 07 06:47:56 PM PDT 24
Finished Aug 07 06:47:57 PM PDT 24
Peak memory 205280 kb
Host smart-2b703697-c08b-4017-b9d2-2cb6192b72a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514508481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3514508481
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.330102138
Short name T135
Test name
Test status
Simulation time 2522782167 ps
CPU time 11.58 seconds
Started Aug 07 06:47:54 PM PDT 24
Finished Aug 07 06:48:06 PM PDT 24
Peak memory 225028 kb
Host smart-aea7c185-8354-4945-94e1-1d5740da56bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330102138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.330102138
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1959256072
Short name T380
Test name
Test status
Simulation time 18940940 ps
CPU time 0.78 seconds
Started Aug 07 06:47:52 PM PDT 24
Finished Aug 07 06:47:53 PM PDT 24
Peak memory 206944 kb
Host smart-db9f26a6-e697-4aeb-98ec-7d7c68d7ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959256072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1959256072
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3702236663
Short name T708
Test name
Test status
Simulation time 6547040998 ps
CPU time 18.05 seconds
Started Aug 07 06:47:55 PM PDT 24
Finished Aug 07 06:48:14 PM PDT 24
Peak memory 224944 kb
Host smart-51df61f6-e0a2-4f11-a9c3-9510f73e4aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702236663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3702236663
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4176863801
Short name T502
Test name
Test status
Simulation time 74786101666 ps
CPU time 209.16 seconds
Started Aug 07 06:47:55 PM PDT 24
Finished Aug 07 06:51:24 PM PDT 24
Peak memory 255416 kb
Host smart-88faf811-8330-4b0b-a096-921e924fa83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176863801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4176863801
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.957680362
Short name T913
Test name
Test status
Simulation time 68109163046 ps
CPU time 373.23 seconds
Started Aug 07 06:47:55 PM PDT 24
Finished Aug 07 06:54:08 PM PDT 24
Peak memory 266032 kb
Host smart-489b73c0-2a70-49a0-b987-0857a761fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957680362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.957680362
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3609247494
Short name T319
Test name
Test status
Simulation time 815192527 ps
CPU time 5.92 seconds
Started Aug 07 06:47:55 PM PDT 24
Finished Aug 07 06:48:01 PM PDT 24
Peak memory 237668 kb
Host smart-755b8eb4-a931-42d4-b964-e141ecb36e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609247494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3609247494
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2193294021
Short name T568
Test name
Test status
Simulation time 58184392397 ps
CPU time 100 seconds
Started Aug 07 06:48:00 PM PDT 24
Finished Aug 07 06:49:41 PM PDT 24
Peak memory 249784 kb
Host smart-86cc90e9-0ab4-4489-9ebd-d89a3b18f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193294021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2193294021
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1549847621
Short name T444
Test name
Test status
Simulation time 213033790 ps
CPU time 4.67 seconds
Started Aug 07 06:47:55 PM PDT 24
Finished Aug 07 06:47:59 PM PDT 24
Peak memory 233152 kb
Host smart-cbb2e32d-292f-45b2-8e0d-a380ee355fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549847621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1549847621
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1222451345
Short name T584
Test name
Test status
Simulation time 20011792046 ps
CPU time 41.28 seconds
Started Aug 07 06:47:55 PM PDT 24
Finished Aug 07 06:48:37 PM PDT 24
Peak memory 224860 kb
Host smart-185adc77-17c0-470a-a7ba-a02de9b8a0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222451345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1222451345
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.345698117
Short name T848
Test name
Test status
Simulation time 1855691191 ps
CPU time 8.87 seconds
Started Aug 07 06:47:56 PM PDT 24
Finished Aug 07 06:48:05 PM PDT 24
Peak memory 233164 kb
Host smart-e75ff317-9f08-4655-b0a8-6e029d4a4139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345698117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.345698117
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1297394208
Short name T35
Test name
Test status
Simulation time 2285673226 ps
CPU time 9.27 seconds
Started Aug 07 06:47:55 PM PDT 24
Finished Aug 07 06:48:04 PM PDT 24
Peak memory 233148 kb
Host smart-514ded31-c1c1-44de-8acb-0617f59788c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297394208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1297394208
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2516215963
Short name T449
Test name
Test status
Simulation time 181334154 ps
CPU time 4.52 seconds
Started Aug 07 06:47:55 PM PDT 24
Finished Aug 07 06:48:00 PM PDT 24
Peak memory 223356 kb
Host smart-e8858431-8191-4fd6-b91d-da5a6a466228
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2516215963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2516215963
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3820344171
Short name T21
Test name
Test status
Simulation time 20110440582 ps
CPU time 74.72 seconds
Started Aug 07 06:48:01 PM PDT 24
Finished Aug 07 06:49:16 PM PDT 24
Peak memory 249864 kb
Host smart-7c593ff6-b4e4-48b1-8cb2-4b5c74169e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820344171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3820344171
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4122247658
Short name T5
Test name
Test status
Simulation time 3943250063 ps
CPU time 8.67 seconds
Started Aug 07 06:47:50 PM PDT 24
Finished Aug 07 06:47:59 PM PDT 24
Peak memory 216904 kb
Host smart-70b58620-0845-4bb8-a5aa-1a0881d9d97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122247658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4122247658
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1069311819
Short name T662
Test name
Test status
Simulation time 9463789561 ps
CPU time 7.22 seconds
Started Aug 07 06:47:50 PM PDT 24
Finished Aug 07 06:47:57 PM PDT 24
Peak memory 216684 kb
Host smart-e97ec680-3208-4a7d-b027-de43fe4a5908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069311819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1069311819
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.540214733
Short name T432
Test name
Test status
Simulation time 27035414 ps
CPU time 0.82 seconds
Started Aug 07 06:47:50 PM PDT 24
Finished Aug 07 06:47:51 PM PDT 24
Peak memory 206400 kb
Host smart-260b1bda-5d19-4557-86de-7bbce7b8c644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540214733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.540214733
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1806300014
Short name T348
Test name
Test status
Simulation time 252929022 ps
CPU time 0.85 seconds
Started Aug 07 06:47:51 PM PDT 24
Finished Aug 07 06:47:51 PM PDT 24
Peak memory 207320 kb
Host smart-5823694a-931f-4751-acc5-1721273a3a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806300014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1806300014
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1451076522
Short name T659
Test name
Test status
Simulation time 1463611005 ps
CPU time 7.2 seconds
Started Aug 07 06:47:56 PM PDT 24
Finished Aug 07 06:48:03 PM PDT 24
Peak memory 250100 kb
Host smart-5ef12b7f-133b-43cb-8f8a-c492a4c1ca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451076522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1451076522
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1159824157
Short name T940
Test name
Test status
Simulation time 20388957 ps
CPU time 0.7 seconds
Started Aug 07 06:48:12 PM PDT 24
Finished Aug 07 06:48:13 PM PDT 24
Peak memory 205164 kb
Host smart-f3c7d60b-e140-4720-b7b1-1633b5ccc736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159824157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1159824157
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4202633551
Short name T929
Test name
Test status
Simulation time 40690138 ps
CPU time 2.64 seconds
Started Aug 07 06:48:05 PM PDT 24
Finished Aug 07 06:48:08 PM PDT 24
Peak memory 233112 kb
Host smart-3fc54985-5584-4d35-8204-07fbab63c148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202633551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4202633551
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3042928681
Short name T590
Test name
Test status
Simulation time 36430711 ps
CPU time 0.82 seconds
Started Aug 07 06:48:00 PM PDT 24
Finished Aug 07 06:48:01 PM PDT 24
Peak memory 206972 kb
Host smart-d27e26ba-fbb8-4078-bdee-b2c2e2ae5af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042928681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3042928681
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3849636675
Short name T753
Test name
Test status
Simulation time 28366325598 ps
CPU time 201.07 seconds
Started Aug 07 06:48:06 PM PDT 24
Finished Aug 07 06:51:27 PM PDT 24
Peak memory 234180 kb
Host smart-25491f99-64f6-4983-a85e-5161e1f519e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849636675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3849636675
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.694403418
Short name T39
Test name
Test status
Simulation time 105693708553 ps
CPU time 570.65 seconds
Started Aug 07 06:48:14 PM PDT 24
Finished Aug 07 06:57:45 PM PDT 24
Peak memory 256992 kb
Host smart-99b7468a-33ae-403c-aa2c-155b387b9bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694403418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.694403418
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.513189804
Short name T404
Test name
Test status
Simulation time 12117675818 ps
CPU time 105.27 seconds
Started Aug 07 06:48:10 PM PDT 24
Finished Aug 07 06:49:55 PM PDT 24
Peak memory 257740 kb
Host smart-658f4dda-96ae-4ffa-932e-a5e83972c013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513189804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.513189804
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3936642643
Short name T469
Test name
Test status
Simulation time 1028219370 ps
CPU time 8.02 seconds
Started Aug 07 06:48:06 PM PDT 24
Finished Aug 07 06:48:14 PM PDT 24
Peak memory 233140 kb
Host smart-7fa45c0c-2019-4681-b258-1b1ebf08be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936642643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3936642643
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2534514592
Short name T30
Test name
Test status
Simulation time 36501464496 ps
CPU time 138.22 seconds
Started Aug 07 06:48:07 PM PDT 24
Finished Aug 07 06:50:25 PM PDT 24
Peak memory 257756 kb
Host smart-cbaac23c-3ac0-4b9f-983c-cd896be379b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534514592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2534514592
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1825655746
Short name T408
Test name
Test status
Simulation time 746144276 ps
CPU time 8.15 seconds
Started Aug 07 06:48:05 PM PDT 24
Finished Aug 07 06:48:14 PM PDT 24
Peak memory 224876 kb
Host smart-71410ccf-562d-46fb-ad56-8704ce2a9371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825655746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1825655746
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3129910120
Short name T221
Test name
Test status
Simulation time 24993253260 ps
CPU time 31.43 seconds
Started Aug 07 06:48:04 PM PDT 24
Finished Aug 07 06:48:35 PM PDT 24
Peak memory 239868 kb
Host smart-69faa0b2-793a-4459-bb96-590effc338dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129910120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3129910120
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.708979384
Short name T663
Test name
Test status
Simulation time 340025687 ps
CPU time 5.69 seconds
Started Aug 07 06:48:05 PM PDT 24
Finished Aug 07 06:48:11 PM PDT 24
Peak memory 241316 kb
Host smart-30431343-d659-4738-b4a3-676603fb743a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708979384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.708979384
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2845334683
Short name T1002
Test name
Test status
Simulation time 739913629 ps
CPU time 5.82 seconds
Started Aug 07 06:48:06 PM PDT 24
Finished Aug 07 06:48:12 PM PDT 24
Peak memory 241340 kb
Host smart-e82ddfe7-2f84-43b9-911c-6273c06e0be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845334683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2845334683
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3526976228
Short name T434
Test name
Test status
Simulation time 1148639282 ps
CPU time 14.13 seconds
Started Aug 07 06:48:04 PM PDT 24
Finished Aug 07 06:48:18 PM PDT 24
Peak memory 222520 kb
Host smart-30494769-125c-44b2-b843-e1574424fed6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3526976228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3526976228
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2417536778
Short name T407
Test name
Test status
Simulation time 7336109633 ps
CPU time 19.21 seconds
Started Aug 07 06:48:00 PM PDT 24
Finished Aug 07 06:48:20 PM PDT 24
Peak memory 216972 kb
Host smart-a5fa05c8-3198-47c2-b55f-af7f14534b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417536778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2417536778
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2106111744
Short name T494
Test name
Test status
Simulation time 14292494957 ps
CPU time 18.41 seconds
Started Aug 07 06:48:00 PM PDT 24
Finished Aug 07 06:48:19 PM PDT 24
Peak memory 216692 kb
Host smart-9688294b-152c-4ead-b7df-94594279249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106111744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2106111744
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1277092122
Short name T424
Test name
Test status
Simulation time 257911901 ps
CPU time 1.49 seconds
Started Aug 07 06:48:06 PM PDT 24
Finished Aug 07 06:48:08 PM PDT 24
Peak memory 216688 kb
Host smart-6cf02774-b716-4630-9e19-6ec30a060378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277092122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1277092122
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3672811757
Short name T456
Test name
Test status
Simulation time 337761292 ps
CPU time 1 seconds
Started Aug 07 06:48:04 PM PDT 24
Finished Aug 07 06:48:05 PM PDT 24
Peak memory 206328 kb
Host smart-a9d4f051-ce67-4089-a875-098e6662e612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672811757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3672811757
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1359536170
Short name T204
Test name
Test status
Simulation time 84328828107 ps
CPU time 27.99 seconds
Started Aug 07 06:48:05 PM PDT 24
Finished Aug 07 06:48:33 PM PDT 24
Peak memory 224948 kb
Host smart-800806c8-6a5f-457e-8ffa-e3cb4a862935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359536170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1359536170
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4235076330
Short name T314
Test name
Test status
Simulation time 14040581 ps
CPU time 0.73 seconds
Started Aug 07 06:48:16 PM PDT 24
Finished Aug 07 06:48:17 PM PDT 24
Peak memory 205800 kb
Host smart-aa937d7f-4dc5-420d-bdaf-bbe460a105c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235076330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4235076330
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3197149124
Short name T490
Test name
Test status
Simulation time 256840496 ps
CPU time 5.73 seconds
Started Aug 07 06:48:21 PM PDT 24
Finished Aug 07 06:48:26 PM PDT 24
Peak memory 233040 kb
Host smart-82c3d172-426a-4db6-bcec-fda1b7e01821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197149124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3197149124
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.777805265
Short name T347
Test name
Test status
Simulation time 48439566 ps
CPU time 0.78 seconds
Started Aug 07 06:48:12 PM PDT 24
Finished Aug 07 06:48:12 PM PDT 24
Peak memory 207292 kb
Host smart-b21e1c8a-c90c-42ce-a16e-fbddfa6cc707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777805265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.777805265
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3393737871
Short name T830
Test name
Test status
Simulation time 17270146562 ps
CPU time 34.05 seconds
Started Aug 07 06:48:17 PM PDT 24
Finished Aug 07 06:48:51 PM PDT 24
Peak memory 233428 kb
Host smart-c0211d1d-9f7f-46ed-8c35-44ce0fd7e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393737871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3393737871
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2601751345
Short name T401
Test name
Test status
Simulation time 6321259538 ps
CPU time 22.19 seconds
Started Aug 07 06:48:15 PM PDT 24
Finished Aug 07 06:48:37 PM PDT 24
Peak memory 233260 kb
Host smart-34559932-08c8-4daf-9fc3-e07b954cf02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601751345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2601751345
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1060309180
Short name T898
Test name
Test status
Simulation time 54846478316 ps
CPU time 282.82 seconds
Started Aug 07 06:48:15 PM PDT 24
Finished Aug 07 06:52:58 PM PDT 24
Peak memory 257044 kb
Host smart-e6e1586b-e01b-41f2-8e26-8ebad17541c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060309180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1060309180
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.415206951
Short name T931
Test name
Test status
Simulation time 958042032 ps
CPU time 19.4 seconds
Started Aug 07 06:48:16 PM PDT 24
Finished Aug 07 06:48:35 PM PDT 24
Peak memory 233180 kb
Host smart-2cce6ef2-3c25-437a-9fcb-7224ffd83af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415206951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.415206951
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3178718157
Short name T224
Test name
Test status
Simulation time 105372648 ps
CPU time 2.66 seconds
Started Aug 07 06:48:17 PM PDT 24
Finished Aug 07 06:48:20 PM PDT 24
Peak memory 233148 kb
Host smart-be6af45a-574f-4572-9fcb-15570c8a7cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178718157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3178718157
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.57292618
Short name T7
Test name
Test status
Simulation time 2109902150 ps
CPU time 27.99 seconds
Started Aug 07 06:48:16 PM PDT 24
Finished Aug 07 06:48:44 PM PDT 24
Peak memory 233152 kb
Host smart-f2ddf610-7175-4ffd-9f79-bed02476297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57292618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.57292618
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.311531966
Short name T212
Test name
Test status
Simulation time 6860528945 ps
CPU time 15 seconds
Started Aug 07 06:48:15 PM PDT 24
Finished Aug 07 06:48:30 PM PDT 24
Peak memory 236900 kb
Host smart-09a75291-48be-43a5-90ad-ecd792f36e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311531966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.311531966
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3993276437
Short name T582
Test name
Test status
Simulation time 1367836998 ps
CPU time 7.52 seconds
Started Aug 07 06:48:10 PM PDT 24
Finished Aug 07 06:48:18 PM PDT 24
Peak memory 224984 kb
Host smart-e824b2a6-5779-404d-9558-88ba3abe119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993276437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3993276437
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3348192502
Short name T127
Test name
Test status
Simulation time 6960334350 ps
CPU time 17.85 seconds
Started Aug 07 06:48:15 PM PDT 24
Finished Aug 07 06:48:33 PM PDT 24
Peak memory 219412 kb
Host smart-c91b6bd7-b8d2-4374-8846-9546e5e9a78c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3348192502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3348192502
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4172962237
Short name T606
Test name
Test status
Simulation time 1275197201 ps
CPU time 3.43 seconds
Started Aug 07 06:48:11 PM PDT 24
Finished Aug 07 06:48:15 PM PDT 24
Peak memory 217096 kb
Host smart-f1208047-5a0c-4586-9502-e3548acf2d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172962237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4172962237
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.135300519
Short name T28
Test name
Test status
Simulation time 14394012852 ps
CPU time 7.52 seconds
Started Aug 07 06:48:11 PM PDT 24
Finished Aug 07 06:48:19 PM PDT 24
Peak memory 216920 kb
Host smart-109036d8-e2c6-445c-adb7-5f41efd952cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135300519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.135300519
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1007204228
Short name T354
Test name
Test status
Simulation time 197143509 ps
CPU time 1.17 seconds
Started Aug 07 06:48:11 PM PDT 24
Finished Aug 07 06:48:12 PM PDT 24
Peak memory 216732 kb
Host smart-a0b4504b-302c-439e-838b-79d493698746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007204228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1007204228
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3114852044
Short name T665
Test name
Test status
Simulation time 138652332 ps
CPU time 0.84 seconds
Started Aug 07 06:48:11 PM PDT 24
Finished Aug 07 06:48:12 PM PDT 24
Peak memory 207368 kb
Host smart-4499fa6a-d59b-48c6-a1ea-7b04e622b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114852044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3114852044
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3252705753
Short name T68
Test name
Test status
Simulation time 1672673934 ps
CPU time 6.07 seconds
Started Aug 07 06:48:20 PM PDT 24
Finished Aug 07 06:48:26 PM PDT 24
Peak memory 233176 kb
Host smart-2ebdff30-76da-4b1c-a0aa-2acb08161a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252705753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3252705753
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3084901132
Short name T438
Test name
Test status
Simulation time 19927057 ps
CPU time 0.69 seconds
Started Aug 07 06:48:31 PM PDT 24
Finished Aug 07 06:48:32 PM PDT 24
Peak memory 205840 kb
Host smart-9bde61a9-5c21-4124-8d6f-8a91f1c475f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084901132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3084901132
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1252815634
Short name T881
Test name
Test status
Simulation time 1172506283 ps
CPU time 4.31 seconds
Started Aug 07 06:48:20 PM PDT 24
Finished Aug 07 06:48:25 PM PDT 24
Peak memory 224904 kb
Host smart-6b0efd1e-e39d-4c03-a4cf-8bc0056769cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252815634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1252815634
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.338409480
Short name T600
Test name
Test status
Simulation time 22649281 ps
CPU time 0.75 seconds
Started Aug 07 06:48:20 PM PDT 24
Finished Aug 07 06:48:21 PM PDT 24
Peak memory 205952 kb
Host smart-c66757e3-eea0-433c-9637-7af13b82bc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338409480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.338409480
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1029007061
Short name T389
Test name
Test status
Simulation time 24620340097 ps
CPU time 52.12 seconds
Started Aug 07 06:48:25 PM PDT 24
Finished Aug 07 06:49:17 PM PDT 24
Peak memory 250636 kb
Host smart-2540f61a-7271-4c87-ad9c-9558f52539c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029007061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1029007061
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3219971180
Short name T947
Test name
Test status
Simulation time 27358547323 ps
CPU time 230.71 seconds
Started Aug 07 06:48:25 PM PDT 24
Finished Aug 07 06:52:16 PM PDT 24
Peak memory 251588 kb
Host smart-2946e605-34d6-4c05-b7ed-4e0116092813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219971180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3219971180
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2242647152
Short name T736
Test name
Test status
Simulation time 22990846570 ps
CPU time 41.95 seconds
Started Aug 07 06:48:25 PM PDT 24
Finished Aug 07 06:49:07 PM PDT 24
Peak memory 239548 kb
Host smart-6569df96-74c0-486b-9b7d-e75d94633cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242647152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2242647152
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.827112183
Short name T845
Test name
Test status
Simulation time 9180016669 ps
CPU time 48.71 seconds
Started Aug 07 06:48:22 PM PDT 24
Finished Aug 07 06:49:11 PM PDT 24
Peak memory 241404 kb
Host smart-c3664181-c62a-4f8d-aeae-0d4d3e244bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827112183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.827112183
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1591389673
Short name T526
Test name
Test status
Simulation time 1766040260 ps
CPU time 41.32 seconds
Started Aug 07 06:48:25 PM PDT 24
Finished Aug 07 06:49:06 PM PDT 24
Peak memory 253084 kb
Host smart-85578e56-0247-4b07-9993-3f260c03cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591389673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1591389673
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3092618614
Short name T718
Test name
Test status
Simulation time 1387068024 ps
CPU time 6.55 seconds
Started Aug 07 06:48:21 PM PDT 24
Finished Aug 07 06:48:28 PM PDT 24
Peak memory 233156 kb
Host smart-e20d21f8-e151-4ecf-9678-758c54a8f48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092618614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3092618614
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1841515288
Short name T595
Test name
Test status
Simulation time 9673612290 ps
CPU time 92.15 seconds
Started Aug 07 06:48:21 PM PDT 24
Finished Aug 07 06:49:53 PM PDT 24
Peak memory 249524 kb
Host smart-bddca309-7ed4-4200-8fc7-b1cb60b7774b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841515288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1841515288
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2897589528
Short name T851
Test name
Test status
Simulation time 3137863995 ps
CPU time 10.52 seconds
Started Aug 07 06:48:24 PM PDT 24
Finished Aug 07 06:48:35 PM PDT 24
Peak memory 239728 kb
Host smart-89b0d9a1-03a1-454c-aaf3-db7422c04098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897589528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2897589528
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2198462304
Short name T237
Test name
Test status
Simulation time 3019633783 ps
CPU time 5.91 seconds
Started Aug 07 06:48:20 PM PDT 24
Finished Aug 07 06:48:27 PM PDT 24
Peak memory 224964 kb
Host smart-96d3a657-c76a-4335-978d-882447b39fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198462304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2198462304
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3265952537
Short name T379
Test name
Test status
Simulation time 75478555 ps
CPU time 4.09 seconds
Started Aug 07 06:48:25 PM PDT 24
Finished Aug 07 06:48:30 PM PDT 24
Peak memory 223472 kb
Host smart-ed26d8e7-bf36-4643-b8d3-778c838fd385
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3265952537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3265952537
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1087259280
Short name T527
Test name
Test status
Simulation time 8698300478 ps
CPU time 40.25 seconds
Started Aug 07 06:48:31 PM PDT 24
Finished Aug 07 06:49:11 PM PDT 24
Peak memory 224980 kb
Host smart-514151c3-4a47-4bd5-9da9-58e2728c0110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087259280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1087259280
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3480085114
Short name T364
Test name
Test status
Simulation time 2659892740 ps
CPU time 4.68 seconds
Started Aug 07 06:48:21 PM PDT 24
Finished Aug 07 06:48:26 PM PDT 24
Peak memory 216640 kb
Host smart-c92a3d7d-d0c2-470e-8261-6ee82cc09c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480085114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3480085114
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1829204953
Short name T580
Test name
Test status
Simulation time 12549388 ps
CPU time 0.71 seconds
Started Aug 07 06:48:16 PM PDT 24
Finished Aug 07 06:48:17 PM PDT 24
Peak memory 206056 kb
Host smart-906d1fe7-2f44-47e7-98cd-82a08ff86eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829204953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1829204953
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1227946289
Short name T321
Test name
Test status
Simulation time 10942884 ps
CPU time 0.7 seconds
Started Aug 07 06:48:21 PM PDT 24
Finished Aug 07 06:48:22 PM PDT 24
Peak memory 206044 kb
Host smart-07a8ec9e-48ac-45c2-8bac-7e1d339d6b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227946289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1227946289
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.65663807
Short name T1005
Test name
Test status
Simulation time 70292491 ps
CPU time 0.87 seconds
Started Aug 07 06:48:20 PM PDT 24
Finished Aug 07 06:48:21 PM PDT 24
Peak memory 206344 kb
Host smart-f60acbf7-5216-4cf6-b3c1-edf6fdc382b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65663807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.65663807
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3547101534
Short name T717
Test name
Test status
Simulation time 5741551827 ps
CPU time 5.91 seconds
Started Aug 07 06:48:24 PM PDT 24
Finished Aug 07 06:48:30 PM PDT 24
Peak memory 224728 kb
Host smart-e8fb8a03-9c6d-44c3-ab27-aa0bb9f3024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547101534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3547101534
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1126351695
Short name T907
Test name
Test status
Simulation time 37352612 ps
CPU time 0.76 seconds
Started Aug 07 06:48:41 PM PDT 24
Finished Aug 07 06:48:42 PM PDT 24
Peak memory 205844 kb
Host smart-864beb47-5ac1-4e1c-a2f1-37d4fc24341b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126351695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1126351695
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4253468739
Short name T219
Test name
Test status
Simulation time 481032826 ps
CPU time 3.3 seconds
Started Aug 07 06:48:39 PM PDT 24
Finished Aug 07 06:48:42 PM PDT 24
Peak memory 224956 kb
Host smart-40441c45-49ab-4ed8-9dfe-32ead21f679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253468739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4253468739
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.438118464
Short name T614
Test name
Test status
Simulation time 25460602 ps
CPU time 0.81 seconds
Started Aug 07 06:48:30 PM PDT 24
Finished Aug 07 06:48:31 PM PDT 24
Peak memory 207260 kb
Host smart-1616647f-1cb8-439c-b72c-1bcf62aff509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438118464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.438118464
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3861889005
Short name T838
Test name
Test status
Simulation time 24969384290 ps
CPU time 43.14 seconds
Started Aug 07 06:48:42 PM PDT 24
Finished Aug 07 06:49:25 PM PDT 24
Peak memory 225020 kb
Host smart-a5be644d-c357-4942-b5ef-bd554729ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861889005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3861889005
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1517216786
Short name T998
Test name
Test status
Simulation time 160411772522 ps
CPU time 743.84 seconds
Started Aug 07 06:48:43 PM PDT 24
Finished Aug 07 07:01:07 PM PDT 24
Peak memory 266040 kb
Host smart-1f8b5c89-1cd6-43b6-adfa-07f9060f576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517216786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1517216786
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.4089385540
Short name T927
Test name
Test status
Simulation time 29048973996 ps
CPU time 335.77 seconds
Started Aug 07 06:48:43 PM PDT 24
Finished Aug 07 06:54:19 PM PDT 24
Peak memory 257840 kb
Host smart-27fa8187-b375-4314-b3b4-ea4f5f62679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089385540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.4089385540
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.681215721
Short name T904
Test name
Test status
Simulation time 2255365254 ps
CPU time 33.88 seconds
Started Aug 07 06:48:36 PM PDT 24
Finished Aug 07 06:49:10 PM PDT 24
Peak memory 233236 kb
Host smart-89b9418d-7ca0-48e7-8426-028275317291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681215721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.681215721
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1358090712
Short name T210
Test name
Test status
Simulation time 9462850329 ps
CPU time 68.05 seconds
Started Aug 07 06:48:39 PM PDT 24
Finished Aug 07 06:49:47 PM PDT 24
Peak memory 225020 kb
Host smart-db168ad0-4fe6-451b-bb60-9b6e0627a347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358090712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1358090712
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.417068461
Short name T755
Test name
Test status
Simulation time 129285553 ps
CPU time 2.26 seconds
Started Aug 07 06:48:38 PM PDT 24
Finished Aug 07 06:48:41 PM PDT 24
Peak memory 219340 kb
Host smart-b1677aa0-e88c-4bf9-950a-1f5951222e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417068461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.417068461
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3405512904
Short name T885
Test name
Test status
Simulation time 1868605038 ps
CPU time 16.68 seconds
Started Aug 07 06:48:36 PM PDT 24
Finished Aug 07 06:48:52 PM PDT 24
Peak memory 233100 kb
Host smart-4c8e1881-4a57-4059-8749-0f079addd299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405512904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3405512904
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3621031452
Short name T944
Test name
Test status
Simulation time 9424353209 ps
CPU time 9.76 seconds
Started Aug 07 06:48:35 PM PDT 24
Finished Aug 07 06:48:45 PM PDT 24
Peak memory 224944 kb
Host smart-a26b6cdd-612b-43ae-99d6-84ae6d58705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621031452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3621031452
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4156318751
Short name T743
Test name
Test status
Simulation time 256187139 ps
CPU time 2.19 seconds
Started Aug 07 06:48:35 PM PDT 24
Finished Aug 07 06:48:37 PM PDT 24
Peak memory 224892 kb
Host smart-6b4786fd-5afb-436f-919f-c03d92628824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156318751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4156318751
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.211988445
Short name T406
Test name
Test status
Simulation time 2109190882 ps
CPU time 6.95 seconds
Started Aug 07 06:48:39 PM PDT 24
Finished Aug 07 06:48:46 PM PDT 24
Peak memory 223660 kb
Host smart-922ba259-24eb-445d-b7e3-5ce9d87d0f7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=211988445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.211988445
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3561539580
Short name T69
Test name
Test status
Simulation time 165454443508 ps
CPU time 470.73 seconds
Started Aug 07 06:48:41 PM PDT 24
Finished Aug 07 06:56:32 PM PDT 24
Peak memory 281632 kb
Host smart-6ae81410-6218-4e38-8c7f-f5cec9dfa8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561539580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3561539580
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4288657130
Short name T871
Test name
Test status
Simulation time 64250633 ps
CPU time 0.75 seconds
Started Aug 07 06:48:30 PM PDT 24
Finished Aug 07 06:48:31 PM PDT 24
Peak memory 206468 kb
Host smart-0a4ff1a8-b0e6-4223-affa-3d6181c754ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288657130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4288657130
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1869446763
Short name T572
Test name
Test status
Simulation time 15305289139 ps
CPU time 12.35 seconds
Started Aug 07 06:48:31 PM PDT 24
Finished Aug 07 06:48:44 PM PDT 24
Peak memory 216764 kb
Host smart-4181ac70-0ad3-4e5d-b7c4-69695a3a6c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869446763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1869446763
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2306546303
Short name T467
Test name
Test status
Simulation time 699639261 ps
CPU time 4.26 seconds
Started Aug 07 06:48:30 PM PDT 24
Finished Aug 07 06:48:34 PM PDT 24
Peak memory 216680 kb
Host smart-97c2a812-4d3f-4789-b32a-fe45e5793fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306546303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2306546303
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.634457134
Short name T719
Test name
Test status
Simulation time 46070326 ps
CPU time 0.81 seconds
Started Aug 07 06:48:31 PM PDT 24
Finished Aug 07 06:48:32 PM PDT 24
Peak memory 206284 kb
Host smart-823b69cd-fbc3-45f5-ba8f-fb074d3f5c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634457134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.634457134
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1369052429
Short name T232
Test name
Test status
Simulation time 5408495980 ps
CPU time 16.91 seconds
Started Aug 07 06:48:36 PM PDT 24
Finished Aug 07 06:48:53 PM PDT 24
Peak memory 233196 kb
Host smart-2fe029ab-e2b0-4ec6-bc14-84e006ee171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369052429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1369052429
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1048864995
Short name T820
Test name
Test status
Simulation time 38467062 ps
CPU time 0.74 seconds
Started Aug 07 06:45:55 PM PDT 24
Finished Aug 07 06:45:56 PM PDT 24
Peak memory 205792 kb
Host smart-df070236-aa8f-487d-aee9-267ab0e7a474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048864995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
048864995
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1604731553
Short name T809
Test name
Test status
Simulation time 4294549828 ps
CPU time 6.84 seconds
Started Aug 07 06:45:50 PM PDT 24
Finished Aug 07 06:45:57 PM PDT 24
Peak memory 233252 kb
Host smart-bdecc0d3-beb2-4811-9d38-324ca0864574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604731553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1604731553
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.625633532
Short name T625
Test name
Test status
Simulation time 92215476 ps
CPU time 0.79 seconds
Started Aug 07 06:45:44 PM PDT 24
Finished Aug 07 06:45:45 PM PDT 24
Peak memory 207260 kb
Host smart-fdf06213-535f-448e-9177-4c7160fb41d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625633532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.625633532
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.215872026
Short name T866
Test name
Test status
Simulation time 29870417 ps
CPU time 0.73 seconds
Started Aug 07 06:45:48 PM PDT 24
Finished Aug 07 06:45:49 PM PDT 24
Peak memory 216100 kb
Host smart-6fddbf9a-825c-4cc9-abc6-5fe187a60d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215872026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.215872026
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.552545687
Short name T49
Test name
Test status
Simulation time 7359687821 ps
CPU time 26.7 seconds
Started Aug 07 06:45:51 PM PDT 24
Finished Aug 07 06:46:18 PM PDT 24
Peak memory 218236 kb
Host smart-57e3e991-d679-43ee-84fa-084a028de4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552545687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.552545687
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2745823866
Short name T544
Test name
Test status
Simulation time 435937259 ps
CPU time 6.95 seconds
Started Aug 07 06:45:49 PM PDT 24
Finished Aug 07 06:45:56 PM PDT 24
Peak memory 224960 kb
Host smart-dfd6569b-7f29-415f-9df0-2aeec3fc7560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745823866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2745823866
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1449197408
Short name T215
Test name
Test status
Simulation time 18292876799 ps
CPU time 137.49 seconds
Started Aug 07 06:45:50 PM PDT 24
Finished Aug 07 06:48:07 PM PDT 24
Peak memory 249520 kb
Host smart-075e039c-b939-4665-8faa-80136efeff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449197408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1449197408
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2552065898
Short name T217
Test name
Test status
Simulation time 1430776069 ps
CPU time 14.77 seconds
Started Aug 07 06:45:46 PM PDT 24
Finished Aug 07 06:46:00 PM PDT 24
Peak memory 233100 kb
Host smart-7f4270c5-5a05-4601-a0cc-21b67fb7c8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552065898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2552065898
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3996300800
Short name T517
Test name
Test status
Simulation time 69557324 ps
CPU time 3.26 seconds
Started Aug 07 06:45:45 PM PDT 24
Finished Aug 07 06:45:48 PM PDT 24
Peak memory 233076 kb
Host smart-59d5d760-78f8-4f05-82ce-e66387356d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996300800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3996300800
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1315197389
Short name T966
Test name
Test status
Simulation time 399812030 ps
CPU time 2.49 seconds
Started Aug 07 06:45:43 PM PDT 24
Finished Aug 07 06:45:45 PM PDT 24
Peak memory 232812 kb
Host smart-8e55b0e3-7cf9-4ab9-a69a-a22f9a10b5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315197389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1315197389
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3105215920
Short name T812
Test name
Test status
Simulation time 32092868 ps
CPU time 2.13 seconds
Started Aug 07 06:45:43 PM PDT 24
Finished Aug 07 06:45:45 PM PDT 24
Peak memory 224880 kb
Host smart-61fb7999-b573-4750-9291-c33e93e81216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105215920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3105215920
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.373182243
Short name T487
Test name
Test status
Simulation time 437182419 ps
CPU time 5.19 seconds
Started Aug 07 06:45:49 PM PDT 24
Finished Aug 07 06:45:54 PM PDT 24
Peak memory 220700 kb
Host smart-3cc11bd1-d099-4a1b-af35-64476b0eabb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=373182243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.373182243
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2844769327
Short name T60
Test name
Test status
Simulation time 36341820 ps
CPU time 1.03 seconds
Started Aug 07 06:45:54 PM PDT 24
Finished Aug 07 06:45:55 PM PDT 24
Peak memory 236884 kb
Host smart-c98390d6-f775-46f3-aed4-08c7570dc188
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844769327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2844769327
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2805323305
Short name T274
Test name
Test status
Simulation time 25088061167 ps
CPU time 265.95 seconds
Started Aug 07 06:45:56 PM PDT 24
Finished Aug 07 06:50:23 PM PDT 24
Peak memory 298772 kb
Host smart-cdbc95e6-726a-4d61-bdbb-a5d2141a92d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805323305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2805323305
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.359119955
Short name T67
Test name
Test status
Simulation time 8622670165 ps
CPU time 53.69 seconds
Started Aug 07 06:45:50 PM PDT 24
Finished Aug 07 06:46:44 PM PDT 24
Peak memory 216976 kb
Host smart-f148c849-b6d9-44a3-9429-5bf5c05d4a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359119955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.359119955
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2760171009
Short name T744
Test name
Test status
Simulation time 16590687467 ps
CPU time 11.24 seconds
Started Aug 07 06:45:43 PM PDT 24
Finished Aug 07 06:45:55 PM PDT 24
Peak memory 216676 kb
Host smart-43a2a4fb-9e32-4853-b906-d496a45b1761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760171009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2760171009
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4005113374
Short name T969
Test name
Test status
Simulation time 42415052 ps
CPU time 0.92 seconds
Started Aug 07 06:45:45 PM PDT 24
Finished Aug 07 06:45:46 PM PDT 24
Peak memory 207420 kb
Host smart-198c1096-8568-4e6b-95db-270933f64285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005113374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4005113374
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2190442856
Short name T14
Test name
Test status
Simulation time 101274308 ps
CPU time 0.75 seconds
Started Aug 07 06:45:44 PM PDT 24
Finished Aug 07 06:45:44 PM PDT 24
Peak memory 206348 kb
Host smart-f4459d39-4659-42b3-a126-2da7e25d495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190442856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2190442856
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2924114967
Short name T713
Test name
Test status
Simulation time 210552159 ps
CPU time 3.41 seconds
Started Aug 07 06:45:50 PM PDT 24
Finished Aug 07 06:45:54 PM PDT 24
Peak memory 225092 kb
Host smart-c0fbf580-1092-4930-9e84-bef2ab7cbf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924114967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2924114967
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1353331549
Short name T555
Test name
Test status
Simulation time 35320811 ps
CPU time 0.75 seconds
Started Aug 07 06:48:51 PM PDT 24
Finished Aug 07 06:48:51 PM PDT 24
Peak memory 205896 kb
Host smart-5f3d3202-002c-463f-94a9-ceb96c64b22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353331549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1353331549
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1294818381
Short name T556
Test name
Test status
Simulation time 1021085802 ps
CPU time 9.64 seconds
Started Aug 07 06:48:46 PM PDT 24
Finished Aug 07 06:48:56 PM PDT 24
Peak memory 233108 kb
Host smart-b5cd881b-35a0-4cfe-8825-f262007d3fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294818381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1294818381
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2284430752
Short name T618
Test name
Test status
Simulation time 27156989 ps
CPU time 0.75 seconds
Started Aug 07 06:48:41 PM PDT 24
Finished Aug 07 06:48:42 PM PDT 24
Peak memory 205932 kb
Host smart-8a757322-b8c3-48dc-bceb-d63c6f9fd848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284430752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2284430752
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3462135156
Short name T352
Test name
Test status
Simulation time 36450370003 ps
CPU time 63.07 seconds
Started Aug 07 06:48:50 PM PDT 24
Finished Aug 07 06:49:53 PM PDT 24
Peak memory 241404 kb
Host smart-ab983d0a-e774-47da-af72-8d2ed894edab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462135156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3462135156
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2697179547
Short name T426
Test name
Test status
Simulation time 98493637897 ps
CPU time 237.46 seconds
Started Aug 07 06:48:50 PM PDT 24
Finished Aug 07 06:52:47 PM PDT 24
Peak memory 254384 kb
Host smart-ff2220d1-c55a-4a5b-880c-82c898839482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697179547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2697179547
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.883512113
Short name T988
Test name
Test status
Simulation time 39173514126 ps
CPU time 352.6 seconds
Started Aug 07 06:48:53 PM PDT 24
Finished Aug 07 06:54:45 PM PDT 24
Peak memory 265216 kb
Host smart-30be640d-ff72-4aa3-b93f-0aebfdcba6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883512113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.883512113
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2530510063
Short name T294
Test name
Test status
Simulation time 979721208 ps
CPU time 17.24 seconds
Started Aug 07 06:48:46 PM PDT 24
Finished Aug 07 06:49:03 PM PDT 24
Peak memory 224884 kb
Host smart-65222593-a22b-47f7-a706-5b8af22ef92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530510063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2530510063
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2609011505
Short name T425
Test name
Test status
Simulation time 36936438 ps
CPU time 0.75 seconds
Started Aug 07 06:48:45 PM PDT 24
Finished Aug 07 06:48:46 PM PDT 24
Peak memory 216140 kb
Host smart-84171d8d-1c74-442e-b504-911a83f43540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609011505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2609011505
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.703638519
Short name T705
Test name
Test status
Simulation time 5952863361 ps
CPU time 18.01 seconds
Started Aug 07 06:48:46 PM PDT 24
Finished Aug 07 06:49:04 PM PDT 24
Peak memory 219328 kb
Host smart-8d75e844-c5c9-4442-b51a-5398c3da29fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703638519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.703638519
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1946230406
Short name T376
Test name
Test status
Simulation time 241007142 ps
CPU time 2.31 seconds
Started Aug 07 06:48:46 PM PDT 24
Finished Aug 07 06:48:49 PM PDT 24
Peak memory 224592 kb
Host smart-d805cb32-d96c-4f86-a589-a047baa765e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946230406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1946230406
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1716176532
Short name T256
Test name
Test status
Simulation time 1559703487 ps
CPU time 9.03 seconds
Started Aug 07 06:48:46 PM PDT 24
Finished Aug 07 06:48:55 PM PDT 24
Peak memory 241248 kb
Host smart-d63b306f-f1d6-4c29-820f-9885745b6544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716176532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1716176532
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3754403938
Short name T199
Test name
Test status
Simulation time 2228923399 ps
CPU time 9.83 seconds
Started Aug 07 06:48:41 PM PDT 24
Finished Aug 07 06:48:51 PM PDT 24
Peak memory 241196 kb
Host smart-4cd216bc-4f56-4e29-ba15-9111a9db31bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754403938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3754403938
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.402095287
Short name T711
Test name
Test status
Simulation time 931128044 ps
CPU time 12.42 seconds
Started Aug 07 06:48:44 PM PDT 24
Finished Aug 07 06:48:57 PM PDT 24
Peak memory 222632 kb
Host smart-bb7974d1-7561-4515-adc9-073a336048ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=402095287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.402095287
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3949642907
Short name T123
Test name
Test status
Simulation time 95840746674 ps
CPU time 385.98 seconds
Started Aug 07 06:48:51 PM PDT 24
Finished Aug 07 06:55:17 PM PDT 24
Peak memory 274208 kb
Host smart-7a336988-8814-4072-a657-5bc68d1b2d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949642907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3949642907
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2851432161
Short name T309
Test name
Test status
Simulation time 8209202720 ps
CPU time 15.68 seconds
Started Aug 07 06:48:41 PM PDT 24
Finished Aug 07 06:48:57 PM PDT 24
Peak memory 216828 kb
Host smart-6e38321a-f445-489b-854a-fdff7691e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851432161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2851432161
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.942783421
Short name T382
Test name
Test status
Simulation time 903009755 ps
CPU time 6.17 seconds
Started Aug 07 06:48:43 PM PDT 24
Finished Aug 07 06:48:49 PM PDT 24
Peak memory 216720 kb
Host smart-94a75787-8804-4f76-b900-9166c12a40f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942783421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.942783421
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1712550365
Short name T597
Test name
Test status
Simulation time 1191647663 ps
CPU time 3.19 seconds
Started Aug 07 06:48:40 PM PDT 24
Finished Aug 07 06:48:43 PM PDT 24
Peak memory 216652 kb
Host smart-f8d64951-2904-48c9-9fd7-c9068fb189f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712550365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1712550365
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2611794286
Short name T415
Test name
Test status
Simulation time 25057310 ps
CPU time 0.74 seconds
Started Aug 07 06:48:40 PM PDT 24
Finished Aug 07 06:48:40 PM PDT 24
Peak memory 206296 kb
Host smart-1bef15d8-4716-420d-a3d1-c350145a7c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611794286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2611794286
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.430395508
Short name T872
Test name
Test status
Simulation time 1859142871 ps
CPU time 5.76 seconds
Started Aug 07 06:48:47 PM PDT 24
Finished Aug 07 06:48:53 PM PDT 24
Peak memory 233148 kb
Host smart-67db593d-058a-431b-93bf-b370906848f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430395508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.430395508
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3211787648
Short name T852
Test name
Test status
Simulation time 73951017 ps
CPU time 0.71 seconds
Started Aug 07 06:49:02 PM PDT 24
Finished Aug 07 06:49:03 PM PDT 24
Peak memory 205872 kb
Host smart-e9897249-60aa-4d3d-a60a-ad5746f14ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211787648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3211787648
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2324876524
Short name T800
Test name
Test status
Simulation time 223665471 ps
CPU time 6.04 seconds
Started Aug 07 06:48:58 PM PDT 24
Finished Aug 07 06:49:04 PM PDT 24
Peak memory 233148 kb
Host smart-0d2e669d-84ad-408d-9b15-6fd15818267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324876524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2324876524
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4160494204
Short name T411
Test name
Test status
Simulation time 45433971 ps
CPU time 0.75 seconds
Started Aug 07 06:48:49 PM PDT 24
Finished Aug 07 06:48:50 PM PDT 24
Peak memory 206248 kb
Host smart-a41f7a20-925c-4dd3-b4e1-93c5e0d464ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160494204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4160494204
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.671517708
Short name T285
Test name
Test status
Simulation time 205028486263 ps
CPU time 401.17 seconds
Started Aug 07 06:48:57 PM PDT 24
Finished Aug 07 06:55:38 PM PDT 24
Peak memory 272800 kb
Host smart-879ba528-848d-492d-8647-c1e2789b180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671517708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.671517708
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.771097120
Short name T459
Test name
Test status
Simulation time 65872348565 ps
CPU time 148.68 seconds
Started Aug 07 06:48:56 PM PDT 24
Finished Aug 07 06:51:25 PM PDT 24
Peak memory 241500 kb
Host smart-6b602bb7-1bf3-4103-a26b-5e00de0414bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771097120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.771097120
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2354603202
Short name T155
Test name
Test status
Simulation time 40413983318 ps
CPU time 346.3 seconds
Started Aug 07 06:48:56 PM PDT 24
Finished Aug 07 06:54:43 PM PDT 24
Peak memory 257864 kb
Host smart-b2c4afea-6dcc-4572-b864-dac097ae5f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354603202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2354603202
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.970195929
Short name T128
Test name
Test status
Simulation time 1130972111 ps
CPU time 9.81 seconds
Started Aug 07 06:48:57 PM PDT 24
Finished Aug 07 06:49:07 PM PDT 24
Peak memory 249588 kb
Host smart-26fa4345-56b1-4f57-b86f-6b7b12fedea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970195929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.970195929
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2042414821
Short name T563
Test name
Test status
Simulation time 322536006 ps
CPU time 2.55 seconds
Started Aug 07 06:48:57 PM PDT 24
Finished Aug 07 06:49:00 PM PDT 24
Peak memory 224948 kb
Host smart-b5d55740-6134-42dd-89b1-eae6d475663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042414821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2042414821
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.744547324
Short name T337
Test name
Test status
Simulation time 146568482 ps
CPU time 2.29 seconds
Started Aug 07 06:48:55 PM PDT 24
Finished Aug 07 06:48:57 PM PDT 24
Peak memory 224348 kb
Host smart-b71640ac-d570-4e4a-9002-b4d3797d00ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744547324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.744547324
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4142375456
Short name T495
Test name
Test status
Simulation time 210814851 ps
CPU time 5.01 seconds
Started Aug 07 06:48:55 PM PDT 24
Finished Aug 07 06:49:00 PM PDT 24
Peak memory 241292 kb
Host smart-6a0e5436-a9c6-41c9-b56a-8c82add291f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142375456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.4142375456
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2851637022
Short name T670
Test name
Test status
Simulation time 21354093630 ps
CPU time 5.55 seconds
Started Aug 07 06:48:55 PM PDT 24
Finished Aug 07 06:49:00 PM PDT 24
Peak memory 224936 kb
Host smart-20239ad6-d8ea-44e4-9acd-5cd537077348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851637022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2851637022
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1384169530
Short name T470
Test name
Test status
Simulation time 479937133 ps
CPU time 6.5 seconds
Started Aug 07 06:48:57 PM PDT 24
Finished Aug 07 06:49:04 PM PDT 24
Peak memory 223456 kb
Host smart-8853ece2-f08b-4904-b72a-9c6cb0660594
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1384169530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1384169530
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3332975253
Short name T15
Test name
Test status
Simulation time 55449441 ps
CPU time 1 seconds
Started Aug 07 06:49:04 PM PDT 24
Finished Aug 07 06:49:05 PM PDT 24
Peak memory 207360 kb
Host smart-a3a91a1d-1a3a-4d84-b13f-dfab91399fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332975253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3332975253
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2292275990
Short name T783
Test name
Test status
Simulation time 5257077803 ps
CPU time 33.92 seconds
Started Aug 07 06:48:49 PM PDT 24
Finished Aug 07 06:49:23 PM PDT 24
Peak memory 216564 kb
Host smart-b55c07a5-c8be-4cbb-97e5-44b98d6ce313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292275990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2292275990
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2437767856
Short name T570
Test name
Test status
Simulation time 673823049 ps
CPU time 3.84 seconds
Started Aug 07 06:48:51 PM PDT 24
Finished Aug 07 06:48:55 PM PDT 24
Peak memory 216704 kb
Host smart-1e338c91-1a09-4310-ae08-387d77895a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437767856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2437767856
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.676922950
Short name T341
Test name
Test status
Simulation time 493741726 ps
CPU time 1.88 seconds
Started Aug 07 06:48:51 PM PDT 24
Finished Aug 07 06:48:53 PM PDT 24
Peak memory 216628 kb
Host smart-49b142ba-5028-45be-8145-e5ace8743fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676922950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.676922950
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3841402639
Short name T608
Test name
Test status
Simulation time 22276259 ps
CPU time 0.74 seconds
Started Aug 07 06:48:50 PM PDT 24
Finished Aug 07 06:48:51 PM PDT 24
Peak memory 206360 kb
Host smart-08805722-e3f4-41b3-92cd-8f3e0ec02a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841402639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3841402639
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3857252359
Short name T1003
Test name
Test status
Simulation time 37472361 ps
CPU time 2.27 seconds
Started Aug 07 06:48:56 PM PDT 24
Finished Aug 07 06:48:58 PM PDT 24
Peak memory 224536 kb
Host smart-fa9cff61-fd58-45c4-b8ab-aa32fcc633ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857252359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3857252359
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3107733956
Short name T734
Test name
Test status
Simulation time 15750662 ps
CPU time 0.79 seconds
Started Aug 07 06:49:12 PM PDT 24
Finished Aug 07 06:49:13 PM PDT 24
Peak memory 205208 kb
Host smart-5978a1ab-9bbe-47f9-b88c-4c8d7694cd9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107733956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3107733956
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2699575234
Short name T939
Test name
Test status
Simulation time 8624301588 ps
CPU time 17.21 seconds
Started Aug 07 06:49:06 PM PDT 24
Finished Aug 07 06:49:23 PM PDT 24
Peak memory 233216 kb
Host smart-33c345d1-c728-4bba-a964-0c9918f33edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699575234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2699575234
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2102149855
Short name T387
Test name
Test status
Simulation time 21011130 ps
CPU time 0.78 seconds
Started Aug 07 06:49:00 PM PDT 24
Finished Aug 07 06:49:01 PM PDT 24
Peak memory 206980 kb
Host smart-b165a6ac-ec11-4152-a352-4cb56df3dd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102149855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2102149855
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.455857390
Short name T8
Test name
Test status
Simulation time 15215253447 ps
CPU time 52.79 seconds
Started Aug 07 06:49:08 PM PDT 24
Finished Aug 07 06:50:01 PM PDT 24
Peak memory 241376 kb
Host smart-7e0a384b-b6be-4ac4-9b2b-8b7c8301ce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455857390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.455857390
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3446641641
Short name T822
Test name
Test status
Simulation time 50154912753 ps
CPU time 145.45 seconds
Started Aug 07 06:49:12 PM PDT 24
Finished Aug 07 06:51:37 PM PDT 24
Peak memory 257656 kb
Host smart-6b99d2f3-153f-4e74-be3e-ef02b7729ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446641641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3446641641
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1821252631
Short name T825
Test name
Test status
Simulation time 91255851891 ps
CPU time 203.67 seconds
Started Aug 07 06:49:13 PM PDT 24
Finished Aug 07 06:52:37 PM PDT 24
Peak memory 257256 kb
Host smart-35639c07-4a76-4158-81af-47133f64e805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821252631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1821252631
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.381744033
Short name T882
Test name
Test status
Simulation time 593371258 ps
CPU time 6.02 seconds
Started Aug 07 06:49:06 PM PDT 24
Finished Aug 07 06:49:12 PM PDT 24
Peak memory 224976 kb
Host smart-4414cc6c-9f03-4066-a985-637acf5d5bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381744033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.381744033
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2236711189
Short name T889
Test name
Test status
Simulation time 2130357271 ps
CPU time 53.58 seconds
Started Aug 07 06:49:07 PM PDT 24
Finished Aug 07 06:50:00 PM PDT 24
Peak memory 265932 kb
Host smart-7c8bf102-ff67-4ebd-b869-19c38d39b633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236711189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2236711189
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.442083098
Short name T707
Test name
Test status
Simulation time 543649090 ps
CPU time 9.27 seconds
Started Aug 07 06:49:05 PM PDT 24
Finished Aug 07 06:49:15 PM PDT 24
Peak memory 231168 kb
Host smart-97c93ece-79b7-4e75-941c-567a4ed67dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442083098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.442083098
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1880767171
Short name T574
Test name
Test status
Simulation time 194212096 ps
CPU time 2.35 seconds
Started Aug 07 06:49:05 PM PDT 24
Finished Aug 07 06:49:08 PM PDT 24
Peak memory 233088 kb
Host smart-bcb4d30e-e1c5-4e5c-8182-b8402c7f5ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880767171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1880767171
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2082041296
Short name T699
Test name
Test status
Simulation time 221865805 ps
CPU time 3.76 seconds
Started Aug 07 06:49:07 PM PDT 24
Finished Aug 07 06:49:11 PM PDT 24
Peak memory 224932 kb
Host smart-abc3a828-89a7-40e5-b384-3d2af733f7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082041296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2082041296
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3868899309
Short name T541
Test name
Test status
Simulation time 1413134175 ps
CPU time 3.26 seconds
Started Aug 07 06:49:06 PM PDT 24
Finished Aug 07 06:49:10 PM PDT 24
Peak memory 233336 kb
Host smart-16ce3465-cd85-4bc1-a510-c6397eeec125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868899309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3868899309
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1145757520
Short name T911
Test name
Test status
Simulation time 1871757476 ps
CPU time 16.02 seconds
Started Aug 07 06:49:06 PM PDT 24
Finished Aug 07 06:49:23 PM PDT 24
Peak memory 223612 kb
Host smart-88af37c2-8a6f-4c71-8f86-d80bde99aa4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1145757520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1145757520
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2586513786
Short name T850
Test name
Test status
Simulation time 206848812 ps
CPU time 1.07 seconds
Started Aug 07 06:49:11 PM PDT 24
Finished Aug 07 06:49:12 PM PDT 24
Peak memory 215472 kb
Host smart-5d67e852-9637-4901-b4e1-b891c19a18b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586513786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2586513786
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.551146272
Short name T992
Test name
Test status
Simulation time 2574222201 ps
CPU time 17.17 seconds
Started Aug 07 06:49:01 PM PDT 24
Finished Aug 07 06:49:18 PM PDT 24
Peak memory 218688 kb
Host smart-ffe3ed21-b642-4d53-a7ab-8b726aea60a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551146272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.551146272
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3319308252
Short name T841
Test name
Test status
Simulation time 3471922596 ps
CPU time 10.34 seconds
Started Aug 07 06:49:00 PM PDT 24
Finished Aug 07 06:49:11 PM PDT 24
Peak memory 216692 kb
Host smart-4b821b24-fdf0-4bec-84de-6ed043737e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319308252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3319308252
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.606736422
Short name T435
Test name
Test status
Simulation time 72595738 ps
CPU time 1.61 seconds
Started Aug 07 06:49:08 PM PDT 24
Finished Aug 07 06:49:10 PM PDT 24
Peak memory 216668 kb
Host smart-c52ce07e-9239-4fb6-bf0f-8fe71aa2b554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606736422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.606736422
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1429397816
Short name T80
Test name
Test status
Simulation time 21170165 ps
CPU time 0.82 seconds
Started Aug 07 06:49:03 PM PDT 24
Finished Aug 07 06:49:03 PM PDT 24
Peak memory 206368 kb
Host smart-c776ae06-0b85-470b-b44e-0f8dd5226001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429397816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1429397816
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3704859086
Short name T134
Test name
Test status
Simulation time 325755441 ps
CPU time 3.83 seconds
Started Aug 07 06:49:07 PM PDT 24
Finished Aug 07 06:49:11 PM PDT 24
Peak memory 233128 kb
Host smart-5a4dacbf-2c8a-40be-9669-4ef9d174aa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704859086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3704859086
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1396663499
Short name T445
Test name
Test status
Simulation time 13688924 ps
CPU time 0.71 seconds
Started Aug 07 06:49:23 PM PDT 24
Finished Aug 07 06:49:24 PM PDT 24
Peak memory 205260 kb
Host smart-da165edc-1f33-4e3c-9e1c-c1f940727301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396663499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1396663499
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2943162694
Short name T497
Test name
Test status
Simulation time 4602366597 ps
CPU time 9.58 seconds
Started Aug 07 06:49:17 PM PDT 24
Finished Aug 07 06:49:27 PM PDT 24
Peak memory 224932 kb
Host smart-7062f0b4-b8a0-4375-bd65-f4b2e744510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943162694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2943162694
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1915397469
Short name T869
Test name
Test status
Simulation time 20332869 ps
CPU time 0.78 seconds
Started Aug 07 06:49:12 PM PDT 24
Finished Aug 07 06:49:13 PM PDT 24
Peak memory 207260 kb
Host smart-86e00c67-de1e-43f0-966e-965ef2c1c9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915397469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1915397469
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2891223618
Short name T252
Test name
Test status
Simulation time 10291462587 ps
CPU time 46.8 seconds
Started Aug 07 06:49:22 PM PDT 24
Finished Aug 07 06:50:09 PM PDT 24
Peak memory 233208 kb
Host smart-39271889-2e66-49bc-bf35-b11dbead35dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891223618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2891223618
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.14866221
Short name T169
Test name
Test status
Simulation time 24333463047 ps
CPU time 216.65 seconds
Started Aug 07 06:49:23 PM PDT 24
Finished Aug 07 06:53:00 PM PDT 24
Peak memory 250056 kb
Host smart-b4802ab9-d42d-40d7-9f89-86176dcadbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14866221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.14866221
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2475968740
Short name T873
Test name
Test status
Simulation time 1186138217 ps
CPU time 20.44 seconds
Started Aug 07 06:49:16 PM PDT 24
Finished Aug 07 06:49:37 PM PDT 24
Peak memory 233020 kb
Host smart-c9f1ae73-e096-4be6-ba61-2107a3846514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475968740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2475968740
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3228681226
Short name T959
Test name
Test status
Simulation time 81177240553 ps
CPU time 583.43 seconds
Started Aug 07 06:49:16 PM PDT 24
Finished Aug 07 06:59:00 PM PDT 24
Peak memory 257768 kb
Host smart-ed6a15b8-38c1-4547-917f-98d1cb70a139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228681226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3228681226
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.646124969
Short name T36
Test name
Test status
Simulation time 4677803980 ps
CPU time 12.28 seconds
Started Aug 07 06:49:17 PM PDT 24
Finished Aug 07 06:49:29 PM PDT 24
Peak memory 233188 kb
Host smart-f46aa682-4e26-4ab6-9f8b-b7701d448b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646124969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.646124969
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2958254502
Short name T733
Test name
Test status
Simulation time 29286569213 ps
CPU time 70.85 seconds
Started Aug 07 06:49:15 PM PDT 24
Finished Aug 07 06:50:26 PM PDT 24
Peak memory 238296 kb
Host smart-4392a16d-2108-4992-9ecc-2406556b0050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958254502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2958254502
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.260542089
Short name T236
Test name
Test status
Simulation time 11675833659 ps
CPU time 22.67 seconds
Started Aug 07 06:49:12 PM PDT 24
Finished Aug 07 06:49:35 PM PDT 24
Peak memory 239412 kb
Host smart-69c79687-742d-4cdb-929b-aab3a3bf4d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260542089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.260542089
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.976117564
Short name T837
Test name
Test status
Simulation time 435187512 ps
CPU time 4.3 seconds
Started Aug 07 06:49:23 PM PDT 24
Finished Aug 07 06:49:27 PM PDT 24
Peak memory 220336 kb
Host smart-1fdb3903-e609-4e7c-91a2-776f249461e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=976117564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.976117564
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3804951713
Short name T124
Test name
Test status
Simulation time 40559615799 ps
CPU time 188.64 seconds
Started Aug 07 06:49:23 PM PDT 24
Finished Aug 07 06:52:32 PM PDT 24
Peak memory 249608 kb
Host smart-6c4679dd-0ee4-4193-9864-24a78276d824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804951713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3804951713
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1661246724
Short name T573
Test name
Test status
Simulation time 2403729189 ps
CPU time 14.96 seconds
Started Aug 07 06:49:13 PM PDT 24
Finished Aug 07 06:49:29 PM PDT 24
Peak memory 216856 kb
Host smart-685604b9-e4ee-41f6-b062-80add63a9856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661246724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1661246724
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1014208580
Short name T921
Test name
Test status
Simulation time 2174331797 ps
CPU time 6.71 seconds
Started Aug 07 06:49:12 PM PDT 24
Finished Aug 07 06:49:19 PM PDT 24
Peak memory 216700 kb
Host smart-4cddbb4c-34a3-44bd-8ffa-a95489ed00ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014208580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1014208580
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1943428223
Short name T537
Test name
Test status
Simulation time 2682526293 ps
CPU time 6.63 seconds
Started Aug 07 06:49:12 PM PDT 24
Finished Aug 07 06:49:19 PM PDT 24
Peak memory 216712 kb
Host smart-ae05bf75-ae01-4f9c-af50-57d2e0e99b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943428223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1943428223
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1728016474
Short name T365
Test name
Test status
Simulation time 10274931 ps
CPU time 0.71 seconds
Started Aug 07 06:49:13 PM PDT 24
Finished Aug 07 06:49:14 PM PDT 24
Peak memory 206000 kb
Host smart-dccb4eaf-076d-41ea-b79d-e7cf361306a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728016474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1728016474
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2969409143
Short name T933
Test name
Test status
Simulation time 1852655512 ps
CPU time 11.32 seconds
Started Aug 07 06:49:16 PM PDT 24
Finished Aug 07 06:49:27 PM PDT 24
Peak memory 241328 kb
Host smart-bf87a835-96b7-4b9a-b79c-8ca9d23496c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969409143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2969409143
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.820238175
Short name T511
Test name
Test status
Simulation time 55273467 ps
CPU time 0.68 seconds
Started Aug 07 06:49:33 PM PDT 24
Finished Aug 07 06:49:34 PM PDT 24
Peak memory 205272 kb
Host smart-d40036de-76ff-4630-9a3d-21b7b4a86ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820238175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.820238175
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.928356829
Short name T586
Test name
Test status
Simulation time 657513528 ps
CPU time 7.1 seconds
Started Aug 07 06:49:27 PM PDT 24
Finished Aug 07 06:49:34 PM PDT 24
Peak memory 224936 kb
Host smart-d3d39248-831f-45cd-ba84-fddd45d6b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928356829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.928356829
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1114787413
Short name T536
Test name
Test status
Simulation time 200170041 ps
CPU time 0.79 seconds
Started Aug 07 06:49:22 PM PDT 24
Finished Aug 07 06:49:23 PM PDT 24
Peak memory 206976 kb
Host smart-52de95da-6db9-43f3-b0fc-6b6a225c241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114787413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1114787413
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3675587769
Short name T589
Test name
Test status
Simulation time 32163498 ps
CPU time 0.73 seconds
Started Aug 07 06:49:32 PM PDT 24
Finished Aug 07 06:49:33 PM PDT 24
Peak memory 216096 kb
Host smart-c2b984b0-6f92-4dc3-9d2d-0f4b4c54adf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675587769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3675587769
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1093550887
Short name T695
Test name
Test status
Simulation time 25560277355 ps
CPU time 141.94 seconds
Started Aug 07 06:49:33 PM PDT 24
Finished Aug 07 06:51:55 PM PDT 24
Peak memory 265996 kb
Host smart-86d23d80-b720-413d-901f-cf9784cdb7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093550887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1093550887
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2022489569
Short name T213
Test name
Test status
Simulation time 61954937859 ps
CPU time 273.18 seconds
Started Aug 07 06:49:34 PM PDT 24
Finished Aug 07 06:54:07 PM PDT 24
Peak memory 252964 kb
Host smart-d5585b23-dabf-4639-a77c-abb965ed39b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022489569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2022489569
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.741874546
Short name T474
Test name
Test status
Simulation time 212081013 ps
CPU time 4.77 seconds
Started Aug 07 06:49:29 PM PDT 24
Finished Aug 07 06:49:34 PM PDT 24
Peak memory 241260 kb
Host smart-aa919ca9-cb55-4236-999f-25a9559d4a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741874546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.741874546
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.328695056
Short name T901
Test name
Test status
Simulation time 10962418721 ps
CPU time 38.77 seconds
Started Aug 07 06:49:33 PM PDT 24
Finished Aug 07 06:50:12 PM PDT 24
Peak memory 241392 kb
Host smart-361cbd09-3700-4f6c-b7e8-911c268d9e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328695056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.328695056
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.928131269
Short name T738
Test name
Test status
Simulation time 594658223 ps
CPU time 9.02 seconds
Started Aug 07 06:49:27 PM PDT 24
Finished Aug 07 06:49:36 PM PDT 24
Peak memory 224984 kb
Host smart-f89a0717-03e2-45fe-857a-365ade2806c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928131269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.928131269
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4018651680
Short name T821
Test name
Test status
Simulation time 314456481 ps
CPU time 10.72 seconds
Started Aug 07 06:49:27 PM PDT 24
Finished Aug 07 06:49:38 PM PDT 24
Peak memory 224904 kb
Host smart-944846a6-b24a-46ca-92cf-e4770d72c25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018651680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4018651680
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3825859736
Short name T951
Test name
Test status
Simulation time 24881733818 ps
CPU time 66.3 seconds
Started Aug 07 06:49:26 PM PDT 24
Finished Aug 07 06:50:33 PM PDT 24
Peak memory 253284 kb
Host smart-0272d60e-4173-45ad-b04b-b08bf90a9a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825859736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3825859736
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.611138121
Short name T980
Test name
Test status
Simulation time 1936639280 ps
CPU time 3.86 seconds
Started Aug 07 06:49:31 PM PDT 24
Finished Aug 07 06:49:35 PM PDT 24
Peak memory 223308 kb
Host smart-a5fb6e2a-1ce4-4658-a181-cd37ff6f81a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=611138121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.611138121
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1314608188
Short name T148
Test name
Test status
Simulation time 54595701 ps
CPU time 1.06 seconds
Started Aug 07 06:49:32 PM PDT 24
Finished Aug 07 06:49:33 PM PDT 24
Peak memory 207516 kb
Host smart-1c222041-b690-4469-9807-2d215a514876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314608188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1314608188
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3920363660
Short name T844
Test name
Test status
Simulation time 1620927282 ps
CPU time 7.94 seconds
Started Aug 07 06:49:28 PM PDT 24
Finished Aug 07 06:49:36 PM PDT 24
Peak memory 216864 kb
Host smart-598ba485-9a83-46ad-bb15-5d974ddc2418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920363660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3920363660
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4164060690
Short name T778
Test name
Test status
Simulation time 2627226768 ps
CPU time 4.02 seconds
Started Aug 07 06:49:28 PM PDT 24
Finished Aug 07 06:49:32 PM PDT 24
Peak memory 216724 kb
Host smart-b9fdf3e8-5753-412b-9e74-dafcf6a0dc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164060690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4164060690
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.238359997
Short name T794
Test name
Test status
Simulation time 250319911 ps
CPU time 4.97 seconds
Started Aug 07 06:49:28 PM PDT 24
Finished Aug 07 06:49:33 PM PDT 24
Peak memory 216608 kb
Host smart-56f2b5ee-a4c3-41c4-9480-f4b21d2c75eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238359997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.238359997
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3299773326
Short name T912
Test name
Test status
Simulation time 54849439 ps
CPU time 0.92 seconds
Started Aug 07 06:49:28 PM PDT 24
Finished Aug 07 06:49:29 PM PDT 24
Peak memory 206360 kb
Host smart-883a53a1-ebf9-4a35-9e34-52d7c8c8692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299773326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3299773326
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1650200958
Short name T370
Test name
Test status
Simulation time 183668731 ps
CPU time 2.11 seconds
Started Aug 07 06:49:27 PM PDT 24
Finished Aug 07 06:49:30 PM PDT 24
Peak memory 224228 kb
Host smart-0c4ba64c-349d-48b9-98c9-9376def2a0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650200958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1650200958
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.438945809
Short name T757
Test name
Test status
Simulation time 24664700 ps
CPU time 0.73 seconds
Started Aug 07 06:49:44 PM PDT 24
Finished Aug 07 06:49:44 PM PDT 24
Peak memory 205284 kb
Host smart-ac67843e-c32e-4d3f-ad99-36fc1a34bcba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438945809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.438945809
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.694898696
Short name T684
Test name
Test status
Simulation time 519684827 ps
CPU time 2.84 seconds
Started Aug 07 06:49:38 PM PDT 24
Finished Aug 07 06:49:41 PM PDT 24
Peak memory 233192 kb
Host smart-9033c642-705c-4d14-8fdb-572f19bfb535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694898696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.694898696
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4113466922
Short name T972
Test name
Test status
Simulation time 17378448 ps
CPU time 0.79 seconds
Started Aug 07 06:49:32 PM PDT 24
Finished Aug 07 06:49:33 PM PDT 24
Peak memory 207000 kb
Host smart-9ba108e0-8022-46c4-a82c-8fcb1e4aa259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113466922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4113466922
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.202773034
Short name T532
Test name
Test status
Simulation time 9515947188 ps
CPU time 19.65 seconds
Started Aug 07 06:49:37 PM PDT 24
Finished Aug 07 06:49:57 PM PDT 24
Peak memory 224992 kb
Host smart-83c955c6-c791-4dc0-a3d4-d4c6dfee245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202773034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.202773034
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.306350124
Short name T279
Test name
Test status
Simulation time 324152305479 ps
CPU time 702.23 seconds
Started Aug 07 06:49:38 PM PDT 24
Finished Aug 07 07:01:20 PM PDT 24
Peak memory 271200 kb
Host smart-a549069c-9709-4527-8bab-00ad5eb6521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306350124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.306350124
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3741829024
Short name T706
Test name
Test status
Simulation time 9875563270 ps
CPU time 40.73 seconds
Started Aug 07 06:49:38 PM PDT 24
Finished Aug 07 06:50:19 PM PDT 24
Peak memory 253052 kb
Host smart-28db4871-32c6-4c8f-8a6d-e51da04a4512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741829024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3741829024
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1225220177
Short name T644
Test name
Test status
Simulation time 4608431980 ps
CPU time 10.08 seconds
Started Aug 07 06:49:38 PM PDT 24
Finished Aug 07 06:49:49 PM PDT 24
Peak memory 233176 kb
Host smart-99851dc8-e27e-41a6-aa1d-74271df4029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225220177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1225220177
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3111289526
Short name T263
Test name
Test status
Simulation time 7352128840 ps
CPU time 29.13 seconds
Started Aug 07 06:49:38 PM PDT 24
Finished Aug 07 06:50:07 PM PDT 24
Peak memory 249596 kb
Host smart-b0050e1e-2cad-491e-b7f0-6d13b4a0a571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111289526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3111289526
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.583119784
Short name T518
Test name
Test status
Simulation time 2014399281 ps
CPU time 10.26 seconds
Started Aug 07 06:49:37 PM PDT 24
Finished Aug 07 06:49:48 PM PDT 24
Peak memory 224936 kb
Host smart-ec5d7abf-c398-45db-96bc-aaa5326e3770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583119784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.583119784
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3920519367
Short name T714
Test name
Test status
Simulation time 8699758535 ps
CPU time 18.01 seconds
Started Aug 07 06:49:39 PM PDT 24
Finished Aug 07 06:49:57 PM PDT 24
Peak memory 233128 kb
Host smart-5f45f4cd-ce8a-4aa2-85c6-0c8f2e9bb7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920519367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3920519367
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.812167474
Short name T789
Test name
Test status
Simulation time 31355371742 ps
CPU time 24.88 seconds
Started Aug 07 06:49:37 PM PDT 24
Finished Aug 07 06:50:02 PM PDT 24
Peak memory 241416 kb
Host smart-665c0358-defc-4ce4-ad54-2b9d07d2b5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812167474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.812167474
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.953188073
Short name T647
Test name
Test status
Simulation time 155276134 ps
CPU time 3.14 seconds
Started Aug 07 06:49:38 PM PDT 24
Finished Aug 07 06:49:41 PM PDT 24
Peak memory 233136 kb
Host smart-17715332-0be1-41ac-a1b5-6a1bb4211f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953188073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.953188073
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1792371237
Short name T801
Test name
Test status
Simulation time 5699150602 ps
CPU time 8.04 seconds
Started Aug 07 06:49:37 PM PDT 24
Finished Aug 07 06:49:46 PM PDT 24
Peak memory 222776 kb
Host smart-819dbf7e-55fb-4f0c-abf5-a53c5ce5aa67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1792371237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1792371237
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3952239285
Short name T802
Test name
Test status
Simulation time 63258196 ps
CPU time 1.09 seconds
Started Aug 07 06:49:43 PM PDT 24
Finished Aug 07 06:49:44 PM PDT 24
Peak memory 207252 kb
Host smart-67277208-f315-459d-9376-b5ec020e1630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952239285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3952239285
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1444143932
Short name T524
Test name
Test status
Simulation time 5606763262 ps
CPU time 35.64 seconds
Started Aug 07 06:49:33 PM PDT 24
Finished Aug 07 06:50:09 PM PDT 24
Peak memory 216844 kb
Host smart-1c3c0368-cef1-4cbf-a06f-f00d24fd21f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444143932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1444143932
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2403396957
Short name T79
Test name
Test status
Simulation time 439402214 ps
CPU time 1.9 seconds
Started Aug 07 06:49:33 PM PDT 24
Finished Aug 07 06:49:35 PM PDT 24
Peak memory 208280 kb
Host smart-f07141fe-2346-4115-8ecc-0a0b6d4c98a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403396957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2403396957
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3753940850
Short name T592
Test name
Test status
Simulation time 149218954 ps
CPU time 2.05 seconds
Started Aug 07 06:49:38 PM PDT 24
Finished Aug 07 06:49:40 PM PDT 24
Peak memory 216704 kb
Host smart-1dcdd2f8-d009-4506-8ad6-d9c03a6092ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753940850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3753940850
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3402910262
Short name T460
Test name
Test status
Simulation time 226582737 ps
CPU time 0.79 seconds
Started Aug 07 06:49:38 PM PDT 24
Finished Aug 07 06:49:39 PM PDT 24
Peak memory 206340 kb
Host smart-facef170-c1ef-4096-b015-96a6cdb493c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402910262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3402910262
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.515202062
Short name T531
Test name
Test status
Simulation time 13500028605 ps
CPU time 24.08 seconds
Started Aug 07 06:49:38 PM PDT 24
Finished Aug 07 06:50:02 PM PDT 24
Peak memory 224932 kb
Host smart-7f6c50dd-481e-4c1e-bb19-fdf9f5fd4381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515202062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.515202062
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1143740281
Short name T338
Test name
Test status
Simulation time 39844322 ps
CPU time 0.68 seconds
Started Aug 07 06:49:47 PM PDT 24
Finished Aug 07 06:49:48 PM PDT 24
Peak memory 205176 kb
Host smart-11dd5fdc-ceb2-414b-b09e-defd7421ad23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143740281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1143740281
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3384872951
Short name T100
Test name
Test status
Simulation time 164314307 ps
CPU time 2.56 seconds
Started Aug 07 06:49:50 PM PDT 24
Finished Aug 07 06:49:53 PM PDT 24
Peak memory 233060 kb
Host smart-7a585c2a-dbf3-4a42-ab53-ff3519e43658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384872951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3384872951
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2766533296
Short name T384
Test name
Test status
Simulation time 117946017 ps
CPU time 0.73 seconds
Started Aug 07 06:49:42 PM PDT 24
Finished Aug 07 06:49:43 PM PDT 24
Peak memory 207288 kb
Host smart-2e25b02a-bf47-435e-b4a8-1b8a5e915f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766533296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2766533296
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.472620540
Short name T694
Test name
Test status
Simulation time 3100189532 ps
CPU time 15.21 seconds
Started Aug 07 06:49:48 PM PDT 24
Finished Aug 07 06:50:03 PM PDT 24
Peak memory 224960 kb
Host smart-c3740d72-0efc-4444-b92e-9d4cd7497538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472620540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.472620540
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3965164155
Short name T491
Test name
Test status
Simulation time 1884684440 ps
CPU time 21.84 seconds
Started Aug 07 06:49:49 PM PDT 24
Finished Aug 07 06:50:10 PM PDT 24
Peak memory 224940 kb
Host smart-b0e7ec67-6945-4679-a205-54eda6cd68e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965164155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3965164155
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1640824667
Short name T954
Test name
Test status
Simulation time 64478424428 ps
CPU time 622.34 seconds
Started Aug 07 06:49:48 PM PDT 24
Finished Aug 07 07:00:10 PM PDT 24
Peak memory 265976 kb
Host smart-422b7183-16bd-4b93-8593-b5b87fca05f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640824667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1640824667
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.919483954
Short name T1007
Test name
Test status
Simulation time 120283324488 ps
CPU time 113.24 seconds
Started Aug 07 06:49:49 PM PDT 24
Finished Aug 07 06:51:42 PM PDT 24
Peak memory 257752 kb
Host smart-f78e347b-9708-4480-a275-c6d16ffe3283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919483954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.919483954
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.106514644
Short name T639
Test name
Test status
Simulation time 132926866 ps
CPU time 4.6 seconds
Started Aug 07 06:49:43 PM PDT 24
Finished Aug 07 06:49:47 PM PDT 24
Peak memory 224872 kb
Host smart-d6208b27-7226-41c4-b13c-147f7ce64669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106514644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.106514644
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1779730868
Short name T515
Test name
Test status
Simulation time 1489855959 ps
CPU time 14.14 seconds
Started Aug 07 06:49:43 PM PDT 24
Finished Aug 07 06:49:57 PM PDT 24
Peak memory 233096 kb
Host smart-e53b36a8-57da-44fc-88f8-e9642dc4acbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779730868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1779730868
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3393890866
Short name T935
Test name
Test status
Simulation time 1217302493 ps
CPU time 6.44 seconds
Started Aug 07 06:49:42 PM PDT 24
Finished Aug 07 06:49:48 PM PDT 24
Peak memory 224992 kb
Host smart-5e3f2cb3-0190-4112-a1c1-a8ef80091330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393890866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3393890866
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4027611386
Short name T997
Test name
Test status
Simulation time 592447000 ps
CPU time 4.57 seconds
Started Aug 07 06:49:48 PM PDT 24
Finished Aug 07 06:49:53 PM PDT 24
Peak memory 223664 kb
Host smart-e135b459-ad68-48dd-9dea-040256899a14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4027611386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4027611386
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1667535580
Short name T149
Test name
Test status
Simulation time 15488033671 ps
CPU time 122.59 seconds
Started Aug 07 06:49:50 PM PDT 24
Finished Aug 07 06:51:52 PM PDT 24
Peak memory 267032 kb
Host smart-b238b02a-1c08-48f2-8d96-013f6cfad22a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667535580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1667535580
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2481027671
Short name T63
Test name
Test status
Simulation time 7494178640 ps
CPU time 9.11 seconds
Started Aug 07 06:49:44 PM PDT 24
Finished Aug 07 06:49:53 PM PDT 24
Peak memory 216676 kb
Host smart-f1fa119c-2b2a-4f55-90c5-c00c0403bf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481027671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2481027671
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4058554843
Short name T813
Test name
Test status
Simulation time 1548172280 ps
CPU time 6.48 seconds
Started Aug 07 06:49:44 PM PDT 24
Finished Aug 07 06:49:51 PM PDT 24
Peak memory 216600 kb
Host smart-9bbdf444-739b-4f65-9539-977f8cbcaa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058554843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4058554843
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2749905877
Short name T562
Test name
Test status
Simulation time 168569154 ps
CPU time 1.23 seconds
Started Aug 07 06:49:42 PM PDT 24
Finished Aug 07 06:49:44 PM PDT 24
Peak memory 216588 kb
Host smart-f433c1ea-8943-463e-8775-1a2c7c1d0057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749905877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2749905877
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.905920616
Short name T362
Test name
Test status
Simulation time 40910581 ps
CPU time 0.66 seconds
Started Aug 07 06:49:42 PM PDT 24
Finished Aug 07 06:49:43 PM PDT 24
Peak memory 205964 kb
Host smart-9be391f1-9d30-4401-811c-98263ba67871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905920616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.905920616
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2578963791
Short name T701
Test name
Test status
Simulation time 662570702 ps
CPU time 3.19 seconds
Started Aug 07 06:49:43 PM PDT 24
Finished Aug 07 06:49:46 PM PDT 24
Peak memory 233088 kb
Host smart-ff0f6e13-ff7a-4eb0-9009-82254a87dc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578963791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2578963791
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3284546274
Short name T51
Test name
Test status
Simulation time 35776910 ps
CPU time 0.7 seconds
Started Aug 07 06:50:04 PM PDT 24
Finished Aug 07 06:50:05 PM PDT 24
Peak memory 205872 kb
Host smart-8f37b5fb-dda4-4001-aa12-934832d37351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284546274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3284546274
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1886479204
Short name T361
Test name
Test status
Simulation time 13732535138 ps
CPU time 32.6 seconds
Started Aug 07 06:49:53 PM PDT 24
Finished Aug 07 06:50:26 PM PDT 24
Peak memory 224948 kb
Host smart-9e4e7445-84bb-479a-adbb-789aca995ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886479204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1886479204
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3894350753
Short name T427
Test name
Test status
Simulation time 54085756 ps
CPU time 0.78 seconds
Started Aug 07 06:49:48 PM PDT 24
Finished Aug 07 06:49:49 PM PDT 24
Peak memory 206952 kb
Host smart-cd0514bb-fffb-4880-a970-5cca236ae868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894350753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3894350753
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3629627089
Short name T523
Test name
Test status
Simulation time 11779996465 ps
CPU time 45.33 seconds
Started Aug 07 06:49:59 PM PDT 24
Finished Aug 07 06:50:44 PM PDT 24
Peak memory 241380 kb
Host smart-39ef040a-8cda-44ba-a155-d3172dacfbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629627089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3629627089
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.4109866048
Short name T298
Test name
Test status
Simulation time 964870049 ps
CPU time 18.51 seconds
Started Aug 07 06:49:58 PM PDT 24
Finished Aug 07 06:50:17 PM PDT 24
Peak memory 235832 kb
Host smart-db204ff5-2eec-4a6a-b924-081c1f29b8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109866048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4109866048
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2121897706
Short name T895
Test name
Test status
Simulation time 15561390327 ps
CPU time 64.2 seconds
Started Aug 07 06:49:59 PM PDT 24
Finished Aug 07 06:51:04 PM PDT 24
Peak memory 249580 kb
Host smart-c214ce11-94f3-4c0c-b5ae-fb820ba516b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121897706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2121897706
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3764233618
Short name T679
Test name
Test status
Simulation time 446774424 ps
CPU time 6.78 seconds
Started Aug 07 06:49:59 PM PDT 24
Finished Aug 07 06:50:06 PM PDT 24
Peak memory 233144 kb
Host smart-e33573aa-93a7-48e6-80d0-77d2c518d8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764233618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3764233618
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.173490371
Short name T151
Test name
Test status
Simulation time 20294402099 ps
CPU time 144.89 seconds
Started Aug 07 06:49:59 PM PDT 24
Finished Aug 07 06:52:25 PM PDT 24
Peak memory 250604 kb
Host smart-495fcb87-f24c-4c45-8390-3dce5625faca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173490371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.173490371
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3629411969
Short name T50
Test name
Test status
Simulation time 13702083790 ps
CPU time 30.26 seconds
Started Aug 07 06:49:55 PM PDT 24
Finished Aug 07 06:50:25 PM PDT 24
Peak memory 233164 kb
Host smart-77e52aef-a4e9-453a-8be1-a6c3078bab2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629411969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3629411969
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.312105708
Short name T689
Test name
Test status
Simulation time 247961030 ps
CPU time 4.82 seconds
Started Aug 07 06:49:54 PM PDT 24
Finished Aug 07 06:49:58 PM PDT 24
Peak memory 233080 kb
Host smart-10d4ea6b-9984-472d-aab6-dcbb9896fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312105708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.312105708
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.872313284
Short name T273
Test name
Test status
Simulation time 312118455 ps
CPU time 3.94 seconds
Started Aug 07 06:49:54 PM PDT 24
Finished Aug 07 06:49:58 PM PDT 24
Peak memory 224880 kb
Host smart-9b10bf8a-994d-4950-902a-629c8c1b1dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872313284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.872313284
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1426065216
Short name T409
Test name
Test status
Simulation time 386326451 ps
CPU time 5.52 seconds
Started Aug 07 06:49:53 PM PDT 24
Finished Aug 07 06:49:59 PM PDT 24
Peak memory 233092 kb
Host smart-f367c358-709f-46ce-8b81-62a3c2e587d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426065216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1426065216
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2506540459
Short name T416
Test name
Test status
Simulation time 13831455162 ps
CPU time 16.83 seconds
Started Aug 07 06:49:59 PM PDT 24
Finished Aug 07 06:50:16 PM PDT 24
Peak memory 223092 kb
Host smart-7607fed8-15de-413e-a584-f54c1c974e23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2506540459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2506540459
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2344049609
Short name T147
Test name
Test status
Simulation time 3938841934 ps
CPU time 84.45 seconds
Started Aug 07 06:50:00 PM PDT 24
Finished Aug 07 06:51:24 PM PDT 24
Peak memory 249700 kb
Host smart-23bec956-caf8-4edf-aa6d-b4ac1a898bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344049609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2344049609
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2530003064
Short name T833
Test name
Test status
Simulation time 19771837650 ps
CPU time 17.67 seconds
Started Aug 07 06:49:47 PM PDT 24
Finished Aug 07 06:50:05 PM PDT 24
Peak memory 216712 kb
Host smart-fcbbb56d-20d5-4517-8c60-a945e09054bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530003064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2530003064
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3142871491
Short name T876
Test name
Test status
Simulation time 2721679553 ps
CPU time 8.56 seconds
Started Aug 07 06:49:48 PM PDT 24
Finished Aug 07 06:49:57 PM PDT 24
Peak memory 216644 kb
Host smart-ef9ac39a-aeca-4a18-a727-1fd4a19d47c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142871491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3142871491
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2531401434
Short name T368
Test name
Test status
Simulation time 157493387 ps
CPU time 1.53 seconds
Started Aug 07 06:49:55 PM PDT 24
Finished Aug 07 06:49:56 PM PDT 24
Peak memory 216672 kb
Host smart-624a059c-5e13-45bc-976b-bb2130772703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531401434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2531401434
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1734164470
Short name T78
Test name
Test status
Simulation time 41238200 ps
CPU time 0.7 seconds
Started Aug 07 06:49:54 PM PDT 24
Finished Aug 07 06:49:55 PM PDT 24
Peak memory 206316 kb
Host smart-b955bb29-0eec-4ad9-8a26-3a6c2b5ca642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734164470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1734164470
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2229188325
Short name T463
Test name
Test status
Simulation time 1813827556 ps
CPU time 13.42 seconds
Started Aug 07 06:49:55 PM PDT 24
Finished Aug 07 06:50:09 PM PDT 24
Peak memory 251952 kb
Host smart-34827cc3-71c9-48e5-a4e4-bba936d30c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229188325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2229188325
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1838490869
Short name T945
Test name
Test status
Simulation time 28393837 ps
CPU time 0.69 seconds
Started Aug 07 06:50:11 PM PDT 24
Finished Aug 07 06:50:12 PM PDT 24
Peak memory 205860 kb
Host smart-3a788fc2-bcd8-4a5e-9cde-7c8cd0e0eff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838490869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1838490869
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.386589073
Short name T81
Test name
Test status
Simulation time 47297120 ps
CPU time 2.59 seconds
Started Aug 07 06:50:12 PM PDT 24
Finished Aug 07 06:50:15 PM PDT 24
Peak memory 233148 kb
Host smart-ce62a9cf-a8a6-44a0-bb4b-0c9e22e2c00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386589073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.386589073
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.625933037
Short name T690
Test name
Test status
Simulation time 26071158 ps
CPU time 0.76 seconds
Started Aug 07 06:50:05 PM PDT 24
Finished Aug 07 06:50:06 PM PDT 24
Peak memory 207056 kb
Host smart-be9b7041-aafd-4eb4-9d4d-ef3493356bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625933037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.625933037
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.455610004
Short name T888
Test name
Test status
Simulation time 79456050 ps
CPU time 0.81 seconds
Started Aug 07 06:50:10 PM PDT 24
Finished Aug 07 06:50:11 PM PDT 24
Peak memory 216208 kb
Host smart-8d2dfc68-4039-4926-a840-c0dd63ed7b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455610004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.455610004
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.7862746
Short name T692
Test name
Test status
Simulation time 10754860925 ps
CPU time 34.97 seconds
Started Aug 07 06:50:09 PM PDT 24
Finished Aug 07 06:50:44 PM PDT 24
Peak memory 241440 kb
Host smart-662c5a57-5b91-4b11-bd3a-662b2a52f349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7862746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.7862746
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3458261891
Short name T585
Test name
Test status
Simulation time 10399514718 ps
CPU time 73.02 seconds
Started Aug 07 06:50:10 PM PDT 24
Finished Aug 07 06:51:24 PM PDT 24
Peak memory 249644 kb
Host smart-2c7efd5a-d601-4019-9b48-703fc8d98a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458261891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3458261891
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.146784347
Short name T286
Test name
Test status
Simulation time 9819757324 ps
CPU time 25.49 seconds
Started Aug 07 06:50:10 PM PDT 24
Finished Aug 07 06:50:36 PM PDT 24
Peak memory 225044 kb
Host smart-be6dd8f6-2f88-483c-8ccf-3dc942b0d2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146784347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.146784347
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2323176949
Short name T943
Test name
Test status
Simulation time 7735864683 ps
CPU time 76.33 seconds
Started Aug 07 06:50:10 PM PDT 24
Finished Aug 07 06:51:26 PM PDT 24
Peak memory 249596 kb
Host smart-2d4135b9-8e95-4f93-8338-95d1e0a76f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323176949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2323176949
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3617507058
Short name T748
Test name
Test status
Simulation time 501157607 ps
CPU time 8.48 seconds
Started Aug 07 06:50:13 PM PDT 24
Finished Aug 07 06:50:22 PM PDT 24
Peak memory 233140 kb
Host smart-2a30c27e-32e1-45a4-b5d8-5aa048c01a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617507058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3617507058
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2076417571
Short name T315
Test name
Test status
Simulation time 32146769 ps
CPU time 2.52 seconds
Started Aug 07 06:50:09 PM PDT 24
Finished Aug 07 06:50:12 PM PDT 24
Peak memory 232844 kb
Host smart-87e4105a-cbf3-476b-8710-a1c1568eca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076417571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2076417571
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.267592446
Short name T247
Test name
Test status
Simulation time 1662005509 ps
CPU time 5.07 seconds
Started Aug 07 06:50:09 PM PDT 24
Finished Aug 07 06:50:14 PM PDT 24
Peak memory 224856 kb
Host smart-5514d750-939f-4e4e-8e3f-e85d0193cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267592446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.267592446
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2610951719
Short name T395
Test name
Test status
Simulation time 554183421 ps
CPU time 5.74 seconds
Started Aug 07 06:50:03 PM PDT 24
Finished Aug 07 06:50:09 PM PDT 24
Peak memory 233132 kb
Host smart-49d87a3c-8735-4874-9e06-147eeb1c523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610951719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2610951719
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.365424885
Short name T581
Test name
Test status
Simulation time 166810935 ps
CPU time 3.9 seconds
Started Aug 07 06:50:10 PM PDT 24
Finished Aug 07 06:50:14 PM PDT 24
Peak memory 223984 kb
Host smart-6c4dec0f-c2d6-4c67-82b7-7b897028878e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=365424885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.365424885
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.75732410
Short name T864
Test name
Test status
Simulation time 570812523 ps
CPU time 0.94 seconds
Started Aug 07 06:50:09 PM PDT 24
Finished Aug 07 06:50:10 PM PDT 24
Peak memory 207172 kb
Host smart-9ca09675-3fdb-4e5c-91b9-252a801f8471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75732410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress
_all.75732410
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1137042538
Short name T466
Test name
Test status
Simulation time 8891374704 ps
CPU time 15.6 seconds
Started Aug 07 06:50:03 PM PDT 24
Finished Aug 07 06:50:19 PM PDT 24
Peak memory 216904 kb
Host smart-5335f68e-481e-40f4-b0b3-c5b5af013b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137042538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1137042538
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3701915691
Short name T924
Test name
Test status
Simulation time 1957407399 ps
CPU time 8.2 seconds
Started Aug 07 06:50:06 PM PDT 24
Finished Aug 07 06:50:14 PM PDT 24
Peak memory 216724 kb
Host smart-346a0043-3a74-481a-a5ab-9f715c5e6af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701915691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3701915691
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1349016905
Short name T478
Test name
Test status
Simulation time 154623061 ps
CPU time 1.96 seconds
Started Aug 07 06:50:05 PM PDT 24
Finished Aug 07 06:50:07 PM PDT 24
Peak memory 216720 kb
Host smart-37b0d56a-5714-439a-a4fe-62d391f279eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349016905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1349016905
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2963910382
Short name T77
Test name
Test status
Simulation time 86322987 ps
CPU time 0.76 seconds
Started Aug 07 06:50:04 PM PDT 24
Finished Aug 07 06:50:05 PM PDT 24
Peak memory 206336 kb
Host smart-b45e5bb6-7aad-4495-bcd4-2f52b2677c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963910382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2963910382
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3107344342
Short name T588
Test name
Test status
Simulation time 7645671270 ps
CPU time 22.9 seconds
Started Aug 07 06:50:12 PM PDT 24
Finished Aug 07 06:50:35 PM PDT 24
Peak memory 224972 kb
Host smart-8681c6c0-a760-46d2-b1d0-0527dba2d48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107344342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3107344342
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2420817108
Short name T578
Test name
Test status
Simulation time 38400750 ps
CPU time 0.72 seconds
Started Aug 07 06:50:19 PM PDT 24
Finished Aug 07 06:50:20 PM PDT 24
Peak memory 205768 kb
Host smart-1b3f0acb-9315-4f19-bd3a-35b946c4d8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420817108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2420817108
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.615311301
Short name T410
Test name
Test status
Simulation time 3126911696 ps
CPU time 4.78 seconds
Started Aug 07 06:50:16 PM PDT 24
Finished Aug 07 06:50:21 PM PDT 24
Peak memory 225032 kb
Host smart-38a7e0fb-23a9-4a0d-ac49-00a3433e6c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615311301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.615311301
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2975791661
Short name T648
Test name
Test status
Simulation time 184250385 ps
CPU time 0.8 seconds
Started Aug 07 06:50:09 PM PDT 24
Finished Aug 07 06:50:10 PM PDT 24
Peak memory 207296 kb
Host smart-8ed8a57e-c197-46be-8c9c-888f49895fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975791661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2975791661
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1310620246
Short name T653
Test name
Test status
Simulation time 45295047 ps
CPU time 0.75 seconds
Started Aug 07 06:50:20 PM PDT 24
Finished Aug 07 06:50:21 PM PDT 24
Peak memory 216156 kb
Host smart-416750b5-aabe-4fd4-925c-1eb6199c8291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310620246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1310620246
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1155076977
Short name T191
Test name
Test status
Simulation time 93828815307 ps
CPU time 236.12 seconds
Started Aug 07 06:50:19 PM PDT 24
Finished Aug 07 06:54:15 PM PDT 24
Peak memory 257816 kb
Host smart-1d84984d-5691-414c-9fb8-8d8e05f86007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155076977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1155076977
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2351102016
Short name T759
Test name
Test status
Simulation time 4235187421 ps
CPU time 109.29 seconds
Started Aug 07 06:50:20 PM PDT 24
Finished Aug 07 06:52:09 PM PDT 24
Peak memory 253704 kb
Host smart-2b3eb221-566d-4e01-af20-0e1d44832a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351102016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2351102016
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.341034102
Short name T443
Test name
Test status
Simulation time 693879098 ps
CPU time 5.74 seconds
Started Aug 07 06:50:19 PM PDT 24
Finished Aug 07 06:50:25 PM PDT 24
Peak memory 224944 kb
Host smart-6c710b58-5743-4c01-8d6c-75d316f399e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341034102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.341034102
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1659186880
Short name T577
Test name
Test status
Simulation time 108087934 ps
CPU time 4.36 seconds
Started Aug 07 06:50:14 PM PDT 24
Finished Aug 07 06:50:19 PM PDT 24
Peak memory 233132 kb
Host smart-150efacb-1ae0-4758-9e11-46d13c3aedca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659186880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1659186880
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.825822630
Short name T13
Test name
Test status
Simulation time 60501684563 ps
CPU time 95.39 seconds
Started Aug 07 06:50:15 PM PDT 24
Finished Aug 07 06:51:50 PM PDT 24
Peak memory 240112 kb
Host smart-66e890b4-f975-4ba1-9933-342c603b45af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825822630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.825822630
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.201771660
Short name T281
Test name
Test status
Simulation time 4479716054 ps
CPU time 11.54 seconds
Started Aug 07 06:50:17 PM PDT 24
Finished Aug 07 06:50:29 PM PDT 24
Peak memory 233144 kb
Host smart-2ad6c200-370c-4608-8fab-46353a1c4feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201771660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.201771660
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.64582162
Short name T318
Test name
Test status
Simulation time 1351654055 ps
CPU time 2.5 seconds
Started Aug 07 06:50:14 PM PDT 24
Finished Aug 07 06:50:17 PM PDT 24
Peak memory 224892 kb
Host smart-1dc71095-2081-4d4f-90c2-1c9961114a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64582162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.64582162
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1874054980
Short name T429
Test name
Test status
Simulation time 1293121473 ps
CPU time 15.05 seconds
Started Aug 07 06:50:18 PM PDT 24
Finished Aug 07 06:50:34 PM PDT 24
Peak memory 223596 kb
Host smart-524b2fe1-4f58-4f55-ad9a-ccb727619f6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1874054980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1874054980
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.626645887
Short name T275
Test name
Test status
Simulation time 241679855418 ps
CPU time 483.5 seconds
Started Aug 07 06:50:19 PM PDT 24
Finished Aug 07 06:58:23 PM PDT 24
Peak memory 265416 kb
Host smart-56e81d9c-e4f3-4425-ab1c-a1046c36879e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626645887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.626645887
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.893461805
Short name T961
Test name
Test status
Simulation time 1256981173 ps
CPU time 16.9 seconds
Started Aug 07 06:50:12 PM PDT 24
Finished Aug 07 06:50:29 PM PDT 24
Peak memory 216916 kb
Host smart-8322320a-9d1d-4b51-a65e-fbbbd890e905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893461805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.893461805
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1222123022
Short name T862
Test name
Test status
Simulation time 834387556 ps
CPU time 6.01 seconds
Started Aug 07 06:50:12 PM PDT 24
Finished Aug 07 06:50:18 PM PDT 24
Peak memory 216700 kb
Host smart-1b7724ce-2d11-48e3-a301-99664c1595b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222123022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1222123022
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1932367890
Short name T682
Test name
Test status
Simulation time 87960245 ps
CPU time 1.36 seconds
Started Aug 07 06:50:16 PM PDT 24
Finished Aug 07 06:50:17 PM PDT 24
Peak memory 216632 kb
Host smart-ab71cef5-f2f0-4bd1-bd7c-c556c4599f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932367890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1932367890
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.25315483
Short name T358
Test name
Test status
Simulation time 39943105 ps
CPU time 0.81 seconds
Started Aug 07 06:50:10 PM PDT 24
Finished Aug 07 06:50:11 PM PDT 24
Peak memory 206280 kb
Host smart-9030e50d-34cd-473e-904c-c34a940ff327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25315483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.25315483
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1857517372
Short name T661
Test name
Test status
Simulation time 677476916 ps
CPU time 7.2 seconds
Started Aug 07 06:50:14 PM PDT 24
Finished Aug 07 06:50:21 PM PDT 24
Peak memory 233180 kb
Host smart-377ead44-961b-4166-8557-21aeab34ddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857517372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1857517372
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3443139429
Short name T952
Test name
Test status
Simulation time 44887816 ps
CPU time 0.74 seconds
Started Aug 07 06:46:00 PM PDT 24
Finished Aug 07 06:46:01 PM PDT 24
Peak memory 205840 kb
Host smart-401b3870-06f4-404b-91e3-4e5f95671e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443139429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
443139429
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1991881547
Short name T751
Test name
Test status
Simulation time 1047222321 ps
CPU time 4.53 seconds
Started Aug 07 06:46:00 PM PDT 24
Finished Aug 07 06:46:05 PM PDT 24
Peak memory 224832 kb
Host smart-3e3184f4-b91a-42ac-b71e-08dcac3c1466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991881547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1991881547
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2522205134
Short name T558
Test name
Test status
Simulation time 16687690 ps
CPU time 0.75 seconds
Started Aug 07 06:45:57 PM PDT 24
Finished Aug 07 06:45:57 PM PDT 24
Peak memory 206268 kb
Host smart-efa72195-ade3-43af-a91c-801524f3925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522205134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2522205134
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3751355910
Short name T197
Test name
Test status
Simulation time 3957576890 ps
CPU time 59.58 seconds
Started Aug 07 06:45:59 PM PDT 24
Finished Aug 07 06:46:59 PM PDT 24
Peak memory 249580 kb
Host smart-495beb39-c354-4457-91c3-d5eab029e486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751355910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3751355910
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4152553286
Short name T201
Test name
Test status
Simulation time 5330685525 ps
CPU time 65.67 seconds
Started Aug 07 06:46:00 PM PDT 24
Finished Aug 07 06:47:06 PM PDT 24
Peak memory 233180 kb
Host smart-8d4db212-8ff9-4282-9702-0cca76cdab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152553286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4152553286
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.989954062
Short name T301
Test name
Test status
Simulation time 52298529883 ps
CPU time 126.83 seconds
Started Aug 07 06:46:00 PM PDT 24
Finished Aug 07 06:48:07 PM PDT 24
Peak memory 249764 kb
Host smart-7a3aed17-71cd-457f-85ed-f5e372a8c5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989954062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
989954062
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3994652803
Short name T1
Test name
Test status
Simulation time 346334558 ps
CPU time 5.46 seconds
Started Aug 07 06:46:02 PM PDT 24
Finished Aug 07 06:46:07 PM PDT 24
Peak memory 233188 kb
Host smart-4b8dea61-6119-4856-bfec-a0c0ce043360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994652803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3994652803
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4148408453
Short name T207
Test name
Test status
Simulation time 3578956933 ps
CPU time 18.21 seconds
Started Aug 07 06:46:00 PM PDT 24
Finished Aug 07 06:46:18 PM PDT 24
Peak memory 233180 kb
Host smart-d48df787-93e7-48c6-88ec-8ef58f56c1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148408453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4148408453
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1332802519
Short name T981
Test name
Test status
Simulation time 220839276 ps
CPU time 2.94 seconds
Started Aug 07 06:45:59 PM PDT 24
Finished Aug 07 06:46:02 PM PDT 24
Peak memory 224820 kb
Host smart-05f3bc4c-e961-48eb-8e46-5a1fc358b0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332802519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1332802519
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2770473071
Short name T917
Test name
Test status
Simulation time 8140868777 ps
CPU time 9.76 seconds
Started Aug 07 06:45:59 PM PDT 24
Finished Aug 07 06:46:09 PM PDT 24
Peak memory 233196 kb
Host smart-bd5272a4-77e2-4f92-a2cf-e8ed4786662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770473071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2770473071
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3797137305
Short name T130
Test name
Test status
Simulation time 235023331 ps
CPU time 4.74 seconds
Started Aug 07 06:46:00 PM PDT 24
Finished Aug 07 06:46:05 PM PDT 24
Peak memory 223508 kb
Host smart-181222d2-3c7b-4625-9dde-fa46ff0b1b7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3797137305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3797137305
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.152100777
Short name T57
Test name
Test status
Simulation time 980854774 ps
CPU time 1.28 seconds
Started Aug 07 06:46:02 PM PDT 24
Finished Aug 07 06:46:03 PM PDT 24
Peak memory 237956 kb
Host smart-0bad67ac-292f-4acf-af4b-d2bcbdf3528f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152100777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.152100777
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2362851674
Short name T271
Test name
Test status
Simulation time 101475740560 ps
CPU time 916.98 seconds
Started Aug 07 06:46:06 PM PDT 24
Finished Aug 07 07:01:23 PM PDT 24
Peak memory 290420 kb
Host smart-86f01f27-e976-4d41-874e-bc007239e9bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362851674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2362851674
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2576055220
Short name T576
Test name
Test status
Simulation time 3392220387 ps
CPU time 16.94 seconds
Started Aug 07 06:45:56 PM PDT 24
Finished Aug 07 06:46:13 PM PDT 24
Peak memory 216828 kb
Host smart-64edf902-3ef2-447b-b166-4a209ae8dabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576055220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2576055220
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2984243402
Short name T439
Test name
Test status
Simulation time 3760073464 ps
CPU time 6.08 seconds
Started Aug 07 06:45:57 PM PDT 24
Finished Aug 07 06:46:03 PM PDT 24
Peak memory 216684 kb
Host smart-3fb6f40b-77af-4f1d-abff-2ac5ce9f3ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984243402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2984243402
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1193057077
Short name T386
Test name
Test status
Simulation time 742166610 ps
CPU time 4.45 seconds
Started Aug 07 06:45:54 PM PDT 24
Finished Aug 07 06:45:59 PM PDT 24
Peak memory 216688 kb
Host smart-51d8c39d-e212-4b80-b76a-cdbfd19ffb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193057077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1193057077
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1914579376
Short name T923
Test name
Test status
Simulation time 47055144 ps
CPU time 0.83 seconds
Started Aug 07 06:45:56 PM PDT 24
Finished Aug 07 06:45:57 PM PDT 24
Peak memory 206344 kb
Host smart-a2c7c57e-c5e2-4608-ab7e-6a5e8ce06660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914579376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1914579376
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3474900448
Short name T768
Test name
Test status
Simulation time 2871479917 ps
CPU time 9.77 seconds
Started Aug 07 06:46:01 PM PDT 24
Finished Aug 07 06:46:10 PM PDT 24
Peak memory 224944 kb
Host smart-93976477-4608-4eb5-91fb-9084037f69e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474900448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3474900448
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2699197214
Short name T553
Test name
Test status
Simulation time 44756507 ps
CPU time 0.68 seconds
Started Aug 07 06:50:28 PM PDT 24
Finished Aug 07 06:50:29 PM PDT 24
Peak memory 205176 kb
Host smart-aca013a4-c046-40d6-bee5-71c3c2165b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699197214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2699197214
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2509953798
Short name T220
Test name
Test status
Simulation time 430425673 ps
CPU time 2.25 seconds
Started Aug 07 06:50:25 PM PDT 24
Finished Aug 07 06:50:27 PM PDT 24
Peak memory 224888 kb
Host smart-8790073d-a501-49a2-97fa-44c520680527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509953798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2509953798
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.746703662
Short name T817
Test name
Test status
Simulation time 19544485 ps
CPU time 0.8 seconds
Started Aug 07 06:50:29 PM PDT 24
Finished Aug 07 06:50:30 PM PDT 24
Peak memory 207268 kb
Host smart-9dadf147-2c2b-4302-9bbf-16d6e3453915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746703662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.746703662
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1633783459
Short name T973
Test name
Test status
Simulation time 15068285520 ps
CPU time 56.19 seconds
Started Aug 07 06:50:31 PM PDT 24
Finished Aug 07 06:51:27 PM PDT 24
Peak memory 249580 kb
Host smart-57ff2a37-613e-4af8-8a0c-2bd629c60f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633783459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1633783459
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.951642468
Short name T251
Test name
Test status
Simulation time 2205560698 ps
CPU time 31.97 seconds
Started Aug 07 06:50:30 PM PDT 24
Finished Aug 07 06:51:02 PM PDT 24
Peak memory 250604 kb
Host smart-527e3bee-2b86-4c81-a6c3-d1b87c18ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951642468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.951642468
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1232354471
Short name T350
Test name
Test status
Simulation time 96572394501 ps
CPU time 220.02 seconds
Started Aug 07 06:50:31 PM PDT 24
Finished Aug 07 06:54:11 PM PDT 24
Peak memory 253136 kb
Host smart-46f8eac9-55f5-4280-b5b8-8f216c1b5faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232354471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1232354471
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1836530584
Short name T579
Test name
Test status
Simulation time 240289973 ps
CPU time 3.21 seconds
Started Aug 07 06:50:30 PM PDT 24
Finished Aug 07 06:50:33 PM PDT 24
Peak memory 224964 kb
Host smart-a9b5d0d7-c71b-4e1c-a42f-a3f89bb31c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836530584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1836530584
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1422581588
Short name T312
Test name
Test status
Simulation time 29865663 ps
CPU time 2.15 seconds
Started Aug 07 06:50:25 PM PDT 24
Finished Aug 07 06:50:27 PM PDT 24
Peak memory 232856 kb
Host smart-6dd86719-9920-46c6-b512-877fb732e383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422581588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1422581588
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3656529590
Short name T865
Test name
Test status
Simulation time 2322243198 ps
CPU time 33.71 seconds
Started Aug 07 06:50:24 PM PDT 24
Finished Aug 07 06:50:58 PM PDT 24
Peak memory 250912 kb
Host smart-afb7c858-ad75-4586-bd6b-694eedd1d84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656529590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3656529590
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.386057946
Short name T883
Test name
Test status
Simulation time 1599903107 ps
CPU time 5.98 seconds
Started Aug 07 06:50:25 PM PDT 24
Finished Aug 07 06:50:31 PM PDT 24
Peak memory 233140 kb
Host smart-7c9d6c26-8680-4788-8000-9df4005b860b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386057946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.386057946
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4281950105
Short name T371
Test name
Test status
Simulation time 2841741222 ps
CPU time 7.73 seconds
Started Aug 07 06:50:28 PM PDT 24
Finished Aug 07 06:50:36 PM PDT 24
Peak memory 224984 kb
Host smart-29e57173-c8a7-4922-96f6-c313d68781e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281950105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4281950105
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4247577740
Short name T613
Test name
Test status
Simulation time 1235553214 ps
CPU time 7.27 seconds
Started Aug 07 06:50:32 PM PDT 24
Finished Aug 07 06:50:39 PM PDT 24
Peak memory 219244 kb
Host smart-d0a5f776-0900-47fa-a076-e7d1ea2f1b02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4247577740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4247577740
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2102865240
Short name T268
Test name
Test status
Simulation time 27328207367 ps
CPU time 100.84 seconds
Started Aug 07 06:50:29 PM PDT 24
Finished Aug 07 06:52:10 PM PDT 24
Peak memory 249648 kb
Host smart-fcd1c6a1-eb19-4932-832f-4f7b41725e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102865240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2102865240
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.79468474
Short name T687
Test name
Test status
Simulation time 3177396661 ps
CPU time 22.69 seconds
Started Aug 07 06:50:29 PM PDT 24
Finished Aug 07 06:50:52 PM PDT 24
Peak memory 216724 kb
Host smart-0b01ed7e-b752-4622-803a-761c44c94be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79468474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.79468474
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.177292440
Short name T554
Test name
Test status
Simulation time 38070848718 ps
CPU time 21.65 seconds
Started Aug 07 06:50:28 PM PDT 24
Finished Aug 07 06:50:50 PM PDT 24
Peak memory 216812 kb
Host smart-8247b570-0b0e-42a3-8c06-d228c3f20f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177292440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.177292440
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2870590292
Short name T452
Test name
Test status
Simulation time 76135030 ps
CPU time 0.72 seconds
Started Aug 07 06:50:25 PM PDT 24
Finished Aug 07 06:50:26 PM PDT 24
Peak memory 206408 kb
Host smart-f0eaf684-9d9f-43f0-a11a-441cf60ae5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870590292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2870590292
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1707884167
Short name T674
Test name
Test status
Simulation time 30605626 ps
CPU time 0.83 seconds
Started Aug 07 06:50:26 PM PDT 24
Finished Aug 07 06:50:27 PM PDT 24
Peak memory 206340 kb
Host smart-8007dbd3-acfd-4cee-83df-cfdcfc2e9880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707884167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1707884167
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.138277109
Short name T631
Test name
Test status
Simulation time 13015508897 ps
CPU time 11.99 seconds
Started Aug 07 06:50:25 PM PDT 24
Finished Aug 07 06:50:38 PM PDT 24
Peak memory 233148 kb
Host smart-87e7cbb9-4707-4868-955c-5c6abbd2fd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138277109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.138277109
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.442146172
Short name T615
Test name
Test status
Simulation time 16335735 ps
CPU time 0.74 seconds
Started Aug 07 06:50:40 PM PDT 24
Finished Aug 07 06:50:41 PM PDT 24
Peak memory 205904 kb
Host smart-b2cfbf01-d702-44ff-8506-4a33f34a1264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442146172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.442146172
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2176788743
Short name T832
Test name
Test status
Simulation time 138515984 ps
CPU time 2.6 seconds
Started Aug 07 06:50:37 PM PDT 24
Finished Aug 07 06:50:40 PM PDT 24
Peak memory 233088 kb
Host smart-aa3b3051-3676-438e-94fa-daff1d63461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176788743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2176788743
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2745084207
Short name T633
Test name
Test status
Simulation time 20608003 ps
CPU time 0.78 seconds
Started Aug 07 06:50:32 PM PDT 24
Finished Aug 07 06:50:32 PM PDT 24
Peak memory 206940 kb
Host smart-15a2e9e3-efbd-480e-9545-2d087152a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745084207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2745084207
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1237802816
Short name T611
Test name
Test status
Simulation time 59965155633 ps
CPU time 55.65 seconds
Started Aug 07 06:50:39 PM PDT 24
Finished Aug 07 06:51:35 PM PDT 24
Peak memory 233196 kb
Host smart-22f1f03f-e2b3-43ce-a9fb-74e176ba4f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237802816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1237802816
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3673386353
Short name T891
Test name
Test status
Simulation time 671543836 ps
CPU time 16.83 seconds
Started Aug 07 06:50:40 PM PDT 24
Finished Aug 07 06:50:57 PM PDT 24
Peak memory 236616 kb
Host smart-0c43be46-5751-4860-9f7d-b75d23c3afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673386353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3673386353
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2254306901
Short name T601
Test name
Test status
Simulation time 4456986985 ps
CPU time 28.24 seconds
Started Aug 07 06:50:40 PM PDT 24
Finished Aug 07 06:51:09 PM PDT 24
Peak memory 224996 kb
Host smart-e8a34f97-d48b-4a28-bd82-20b85ad85818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254306901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2254306901
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2042683667
Short name T291
Test name
Test status
Simulation time 558558147 ps
CPU time 14.96 seconds
Started Aug 07 06:50:36 PM PDT 24
Finished Aug 07 06:50:51 PM PDT 24
Peak memory 235044 kb
Host smart-f7f2b0b8-8ff2-430d-915c-440ceb25e09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042683667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2042683667
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1728663162
Short name T165
Test name
Test status
Simulation time 62528517647 ps
CPU time 103.42 seconds
Started Aug 07 06:50:35 PM PDT 24
Finished Aug 07 06:52:18 PM PDT 24
Peak memory 250008 kb
Host smart-89049ddd-370a-40c6-b635-bf4b1ce7948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728663162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1728663162
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1382033993
Short name T731
Test name
Test status
Simulation time 5836290293 ps
CPU time 19.44 seconds
Started Aug 07 06:50:35 PM PDT 24
Finished Aug 07 06:50:54 PM PDT 24
Peak memory 224912 kb
Host smart-a75af92b-43a5-441f-8688-2d6729699fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382033993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1382033993
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3994531827
Short name T723
Test name
Test status
Simulation time 153698228 ps
CPU time 5.19 seconds
Started Aug 07 06:50:35 PM PDT 24
Finished Aug 07 06:50:40 PM PDT 24
Peak memory 233120 kb
Host smart-c625decb-c6e2-421e-b394-843f364550c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994531827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3994531827
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.812945289
Short name T902
Test name
Test status
Simulation time 300637722 ps
CPU time 3.4 seconds
Started Aug 07 06:50:36 PM PDT 24
Finished Aug 07 06:50:39 PM PDT 24
Peak memory 224872 kb
Host smart-dd771974-104f-4ae5-9838-7a01c2977239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812945289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.812945289
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1968091900
Short name T638
Test name
Test status
Simulation time 2513995868 ps
CPU time 3.56 seconds
Started Aug 07 06:50:29 PM PDT 24
Finished Aug 07 06:50:33 PM PDT 24
Peak memory 224968 kb
Host smart-a18ec427-e5cd-4841-a4d8-b8ede005950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968091900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1968091900
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.131917962
Short name T363
Test name
Test status
Simulation time 3226829787 ps
CPU time 5 seconds
Started Aug 07 06:50:43 PM PDT 24
Finished Aug 07 06:50:48 PM PDT 24
Peak memory 223652 kb
Host smart-0a265aa2-cee2-49ec-a001-77c55fd007b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=131917962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.131917962
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4000555532
Short name T863
Test name
Test status
Simulation time 37180016499 ps
CPU time 440.32 seconds
Started Aug 07 06:50:42 PM PDT 24
Finished Aug 07 06:58:02 PM PDT 24
Peak memory 273764 kb
Host smart-1f546229-6127-46e0-835c-c49e5a39c2a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000555532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4000555532
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3860813388
Short name T302
Test name
Test status
Simulation time 5157277009 ps
CPU time 30.21 seconds
Started Aug 07 06:50:33 PM PDT 24
Finished Aug 07 06:51:03 PM PDT 24
Peak memory 216676 kb
Host smart-8b5e43d0-6582-4ad2-8006-3ba28d7d8dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860813388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3860813388
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3637602869
Short name T784
Test name
Test status
Simulation time 3901301371 ps
CPU time 7.86 seconds
Started Aug 07 06:50:29 PM PDT 24
Finished Aug 07 06:50:37 PM PDT 24
Peak memory 216644 kb
Host smart-1998cb29-8f94-4f85-8f88-b2989c7bead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637602869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3637602869
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3086546389
Short name T629
Test name
Test status
Simulation time 113531855 ps
CPU time 1.28 seconds
Started Aug 07 06:50:34 PM PDT 24
Finished Aug 07 06:50:35 PM PDT 24
Peak memory 216496 kb
Host smart-edd0db65-57e2-4103-b41b-9a1c07593c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086546389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3086546389
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1463917412
Short name T339
Test name
Test status
Simulation time 45976761 ps
CPU time 0.8 seconds
Started Aug 07 06:50:30 PM PDT 24
Finished Aug 07 06:50:31 PM PDT 24
Peak memory 206348 kb
Host smart-45de50e5-4371-4766-8d9c-b534b8e8ae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463917412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1463917412
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3932549129
Short name T253
Test name
Test status
Simulation time 11898682889 ps
CPU time 13.01 seconds
Started Aug 07 06:50:37 PM PDT 24
Finished Aug 07 06:50:50 PM PDT 24
Peak memory 251636 kb
Host smart-9c69c2da-8104-46b7-8bb2-c8b1d7d34928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932549129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3932549129
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3103743859
Short name T978
Test name
Test status
Simulation time 13710012 ps
CPU time 0.71 seconds
Started Aug 07 06:50:45 PM PDT 24
Finished Aug 07 06:50:46 PM PDT 24
Peak memory 205216 kb
Host smart-5731ffc4-8c44-47ab-9485-e330e812c3a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103743859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3103743859
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4032682372
Short name T776
Test name
Test status
Simulation time 1566702042 ps
CPU time 8.19 seconds
Started Aug 07 06:50:44 PM PDT 24
Finished Aug 07 06:50:53 PM PDT 24
Peak memory 233124 kb
Host smart-d3d09708-b293-48cf-9fe9-b78ad11daeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032682372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4032682372
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1700508088
Short name T908
Test name
Test status
Simulation time 17515113 ps
CPU time 0.83 seconds
Started Aug 07 06:50:42 PM PDT 24
Finished Aug 07 06:50:43 PM PDT 24
Peak memory 206952 kb
Host smart-61b8e2ca-1cff-4d05-a564-c6f8833ee363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700508088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1700508088
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2824693589
Short name T990
Test name
Test status
Simulation time 8571252954 ps
CPU time 27.13 seconds
Started Aug 07 06:50:45 PM PDT 24
Finished Aug 07 06:51:13 PM PDT 24
Peak memory 225004 kb
Host smart-8af2cfef-62f2-4d4b-8650-8dbad7e59df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824693589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2824693589
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2314924688
Short name T310
Test name
Test status
Simulation time 62393774354 ps
CPU time 270.86 seconds
Started Aug 07 06:50:45 PM PDT 24
Finished Aug 07 06:55:16 PM PDT 24
Peak memory 255544 kb
Host smart-ad876e5b-47dd-4da4-b385-2baaa4f4f253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314924688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2314924688
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3431070330
Short name T185
Test name
Test status
Simulation time 12614959225 ps
CPU time 82.28 seconds
Started Aug 07 06:50:47 PM PDT 24
Finished Aug 07 06:52:09 PM PDT 24
Peak memory 263376 kb
Host smart-32c1e8fb-a99c-4486-b51a-aa32dce7bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431070330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3431070330
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1127229848
Short name T658
Test name
Test status
Simulation time 3883844304 ps
CPU time 7.38 seconds
Started Aug 07 06:50:45 PM PDT 24
Finished Aug 07 06:50:53 PM PDT 24
Peak memory 224908 kb
Host smart-67c6d95e-7fa8-4555-b7d3-b2e762513643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127229848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1127229848
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.4078255282
Short name T509
Test name
Test status
Simulation time 93947711145 ps
CPU time 183.7 seconds
Started Aug 07 06:50:45 PM PDT 24
Finished Aug 07 06:53:49 PM PDT 24
Peak memory 257772 kb
Host smart-45a3b9c5-6bc8-4f82-8dea-8834182b356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078255282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.4078255282
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1519755768
Short name T721
Test name
Test status
Simulation time 2422296469 ps
CPU time 19.26 seconds
Started Aug 07 06:50:46 PM PDT 24
Finished Aug 07 06:51:05 PM PDT 24
Peak memory 233244 kb
Host smart-0245f9e6-0d97-4d28-8e38-8438a5f564f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519755768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1519755768
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3762212857
Short name T819
Test name
Test status
Simulation time 16952601215 ps
CPU time 67.94 seconds
Started Aug 07 06:50:45 PM PDT 24
Finished Aug 07 06:51:53 PM PDT 24
Peak memory 252496 kb
Host smart-a27a4494-cfb1-49a6-bcd1-39376493bb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762212857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3762212857
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.892055385
Short name T447
Test name
Test status
Simulation time 2971176065 ps
CPU time 14.54 seconds
Started Aug 07 06:50:47 PM PDT 24
Finished Aug 07 06:51:02 PM PDT 24
Peak memory 240568 kb
Host smart-7322ee6d-fbcb-4576-82f4-2df9c78c3f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892055385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.892055385
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.713228077
Short name T788
Test name
Test status
Simulation time 13210397589 ps
CPU time 18.25 seconds
Started Aug 07 06:50:43 PM PDT 24
Finished Aug 07 06:51:01 PM PDT 24
Peak memory 233196 kb
Host smart-d8662121-1e84-4125-afcd-f43cfe557dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713228077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.713228077
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4006816849
Short name T33
Test name
Test status
Simulation time 380558534 ps
CPU time 4.33 seconds
Started Aug 07 06:50:46 PM PDT 24
Finished Aug 07 06:50:50 PM PDT 24
Peak memory 219320 kb
Host smart-de200006-14d5-4251-8a61-bdb65cf714e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4006816849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4006816849
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1011359888
Short name T878
Test name
Test status
Simulation time 29070033348 ps
CPU time 140.48 seconds
Started Aug 07 06:50:47 PM PDT 24
Finished Aug 07 06:53:08 PM PDT 24
Peak memory 264232 kb
Host smart-b1f619dc-aff9-4db6-86b3-439c39c42d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011359888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1011359888
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.649806135
Short name T483
Test name
Test status
Simulation time 9273565568 ps
CPU time 36.13 seconds
Started Aug 07 06:50:40 PM PDT 24
Finished Aug 07 06:51:17 PM PDT 24
Peak memory 216844 kb
Host smart-aadb6db8-01b6-4b4a-b925-a36e269b7f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649806135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.649806135
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2138392516
Short name T353
Test name
Test status
Simulation time 9542995408 ps
CPU time 12.03 seconds
Started Aug 07 06:50:42 PM PDT 24
Finished Aug 07 06:50:54 PM PDT 24
Peak memory 216688 kb
Host smart-f04f552a-658b-44fd-b856-b7c8653a831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138392516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2138392516
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1108432622
Short name T501
Test name
Test status
Simulation time 29612742 ps
CPU time 1.03 seconds
Started Aug 07 06:50:40 PM PDT 24
Finished Aug 07 06:50:41 PM PDT 24
Peak memory 207512 kb
Host smart-d81f9026-c21c-4d70-98af-a41cf9a5144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108432622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1108432622
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3546697230
Short name T769
Test name
Test status
Simulation time 69146659 ps
CPU time 0.9 seconds
Started Aug 07 06:50:40 PM PDT 24
Finished Aug 07 06:50:41 PM PDT 24
Peak memory 206364 kb
Host smart-b81193bd-4e45-4256-a495-ec411c440fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546697230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3546697230
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.280615670
Short name T793
Test name
Test status
Simulation time 1372581274 ps
CPU time 4.24 seconds
Started Aug 07 06:50:46 PM PDT 24
Finished Aug 07 06:50:50 PM PDT 24
Peak memory 219772 kb
Host smart-c9d85012-e5c8-4e84-af11-4dc839aeb718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280615670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.280615670
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2825026729
Short name T946
Test name
Test status
Simulation time 31671504 ps
CPU time 0.7 seconds
Started Aug 07 06:50:57 PM PDT 24
Finished Aug 07 06:50:57 PM PDT 24
Peak memory 205196 kb
Host smart-302e79c8-5bed-4f94-8650-bca89928ba82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825026729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2825026729
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4049492469
Short name T763
Test name
Test status
Simulation time 155337238 ps
CPU time 2.57 seconds
Started Aug 07 06:50:54 PM PDT 24
Finished Aug 07 06:50:57 PM PDT 24
Peak memory 233024 kb
Host smart-67ad1d93-fb29-43fb-bd31-cf5305d86236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049492469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4049492469
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.279204298
Short name T551
Test name
Test status
Simulation time 29931245 ps
CPU time 0.81 seconds
Started Aug 07 06:50:46 PM PDT 24
Finished Aug 07 06:50:47 PM PDT 24
Peak memory 207040 kb
Host smart-6bfa8a88-0652-44d5-9498-1a09593dc038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279204298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.279204298
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2714468558
Short name T856
Test name
Test status
Simulation time 1542965411 ps
CPU time 30.72 seconds
Started Aug 07 06:50:57 PM PDT 24
Finished Aug 07 06:51:28 PM PDT 24
Peak memory 249752 kb
Host smart-dfc56ad5-e066-4d0a-b085-18b905374de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714468558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2714468558
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3853681641
Short name T617
Test name
Test status
Simulation time 3645719598 ps
CPU time 80.39 seconds
Started Aug 07 06:50:56 PM PDT 24
Finished Aug 07 06:52:16 PM PDT 24
Peak memory 266012 kb
Host smart-2b80ed40-addb-4b97-83fb-636dcad1940c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853681641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3853681641
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2103068594
Short name T293
Test name
Test status
Simulation time 898482603 ps
CPU time 9.82 seconds
Started Aug 07 06:50:52 PM PDT 24
Finished Aug 07 06:51:02 PM PDT 24
Peak memory 237440 kb
Host smart-d5b3acaf-ee3f-4531-8cde-6249c7c8cbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103068594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2103068594
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.813555565
Short name T2
Test name
Test status
Simulation time 5789186390 ps
CPU time 72.46 seconds
Started Aug 07 06:50:52 PM PDT 24
Finished Aug 07 06:52:04 PM PDT 24
Peak memory 254620 kb
Host smart-17528f12-57ef-4d55-9d0e-4669ee33cc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813555565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.813555565
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1260964684
Short name T630
Test name
Test status
Simulation time 430214766 ps
CPU time 3.72 seconds
Started Aug 07 06:50:53 PM PDT 24
Finished Aug 07 06:50:57 PM PDT 24
Peak memory 233080 kb
Host smart-a81d8d6f-7970-45f9-94d8-d16d8636b9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260964684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1260964684
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2496217790
Short name T440
Test name
Test status
Simulation time 19667988184 ps
CPU time 30.3 seconds
Started Aug 07 06:50:52 PM PDT 24
Finished Aug 07 06:51:23 PM PDT 24
Peak memory 233188 kb
Host smart-97aa6ea1-5d3e-47bc-872c-2ef2c8b05292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496217790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2496217790
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2095951216
Short name T37
Test name
Test status
Simulation time 24091670360 ps
CPU time 15.72 seconds
Started Aug 07 06:50:51 PM PDT 24
Finished Aug 07 06:51:07 PM PDT 24
Peak memory 233252 kb
Host smart-362e6920-96d0-4d86-b13a-05c469f34ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095951216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2095951216
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2016256121
Short name T375
Test name
Test status
Simulation time 14834588777 ps
CPU time 43.83 seconds
Started Aug 07 06:50:51 PM PDT 24
Finished Aug 07 06:51:35 PM PDT 24
Peak memory 253968 kb
Host smart-505b148f-5168-4728-a641-c01d7b17f57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016256121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2016256121
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1724652293
Short name T360
Test name
Test status
Simulation time 652673596 ps
CPU time 4.76 seconds
Started Aug 07 06:50:55 PM PDT 24
Finished Aug 07 06:51:00 PM PDT 24
Peak memory 223572 kb
Host smart-8ccf3823-8c83-4892-9405-c1b22d8760e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1724652293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1724652293
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.847607926
Short name T145
Test name
Test status
Simulation time 90966940870 ps
CPU time 388.14 seconds
Started Aug 07 06:50:57 PM PDT 24
Finished Aug 07 06:57:25 PM PDT 24
Peak memory 254756 kb
Host smart-0780d863-3671-4a3d-a64d-6c939a5b6f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847607926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.847607926
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.571138433
Short name T331
Test name
Test status
Simulation time 2544389799 ps
CPU time 17.24 seconds
Started Aug 07 06:50:51 PM PDT 24
Finished Aug 07 06:51:08 PM PDT 24
Peak memory 217068 kb
Host smart-f4a2ed9a-412b-4dc7-b726-4286dabbc4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571138433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.571138433
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2424342124
Short name T727
Test name
Test status
Simulation time 3159290815 ps
CPU time 8.92 seconds
Started Aug 07 06:50:51 PM PDT 24
Finished Aug 07 06:51:00 PM PDT 24
Peak memory 216712 kb
Host smart-e46ee8c0-1b40-4e39-bf8b-7da02f932688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424342124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2424342124
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.455177998
Short name T696
Test name
Test status
Simulation time 54413817 ps
CPU time 2.15 seconds
Started Aug 07 06:50:53 PM PDT 24
Finished Aug 07 06:50:56 PM PDT 24
Peak memory 216664 kb
Host smart-2de2b1e4-d189-4fc6-b25f-bd3403c65779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455177998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.455177998
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.529769787
Short name T307
Test name
Test status
Simulation time 148142041 ps
CPU time 0.96 seconds
Started Aug 07 06:50:53 PM PDT 24
Finished Aug 07 06:50:54 PM PDT 24
Peak memory 206396 kb
Host smart-0666fa7d-501a-4668-92cb-ab814759cd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529769787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.529769787
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1688416186
Short name T505
Test name
Test status
Simulation time 375436698 ps
CPU time 2.93 seconds
Started Aug 07 06:50:52 PM PDT 24
Finished Aug 07 06:50:55 PM PDT 24
Peak memory 224976 kb
Host smart-056b5331-f2ed-4266-96e1-e5ecd68a4a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688416186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1688416186
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.976085077
Short name T417
Test name
Test status
Simulation time 11972979 ps
CPU time 0.71 seconds
Started Aug 07 06:51:07 PM PDT 24
Finished Aug 07 06:51:07 PM PDT 24
Peak memory 205188 kb
Host smart-7a96cfa0-0e4d-4a74-95c4-76e4d0c86359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976085077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.976085077
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1731799134
Short name T238
Test name
Test status
Simulation time 102764718 ps
CPU time 4.38 seconds
Started Aug 07 06:51:03 PM PDT 24
Finished Aug 07 06:51:07 PM PDT 24
Peak memory 233052 kb
Host smart-d6544d82-64f5-4f4c-89f5-d72c71c164a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731799134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1731799134
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1251066524
Short name T313
Test name
Test status
Simulation time 15782942 ps
CPU time 0.77 seconds
Started Aug 07 06:50:56 PM PDT 24
Finished Aug 07 06:50:57 PM PDT 24
Peak memory 206956 kb
Host smart-34d0be5a-9f2f-4bee-a7f3-5bc34c6c669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251066524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1251066524
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3319162870
Short name T874
Test name
Test status
Simulation time 2179749286 ps
CPU time 21.31 seconds
Started Aug 07 06:51:05 PM PDT 24
Finished Aug 07 06:51:27 PM PDT 24
Peak memory 240960 kb
Host smart-9d73754f-58f4-4c96-b5fa-57e74d12f659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319162870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3319162870
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2756941019
Short name T667
Test name
Test status
Simulation time 23558253979 ps
CPU time 157.53 seconds
Started Aug 07 06:51:09 PM PDT 24
Finished Aug 07 06:53:46 PM PDT 24
Peak memory 249668 kb
Host smart-f74b2daa-5c2c-4b94-803e-d2ac1cce7041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756941019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2756941019
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1634338345
Short name T304
Test name
Test status
Simulation time 5882240828 ps
CPU time 9.92 seconds
Started Aug 07 06:51:07 PM PDT 24
Finished Aug 07 06:51:17 PM PDT 24
Peak memory 217948 kb
Host smart-8a1bf960-866c-4d32-a360-4e02fbefcda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634338345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1634338345
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.447507757
Short name T393
Test name
Test status
Simulation time 1614610919 ps
CPU time 7.28 seconds
Started Aug 07 06:51:00 PM PDT 24
Finished Aug 07 06:51:08 PM PDT 24
Peak memory 224908 kb
Host smart-f35db132-862c-4714-b8c8-eaec43b44314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447507757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.447507757
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.158070758
Short name T436
Test name
Test status
Simulation time 4052935152 ps
CPU time 38.28 seconds
Started Aug 07 06:51:00 PM PDT 24
Finished Aug 07 06:51:38 PM PDT 24
Peak memory 237392 kb
Host smart-86e7626b-1ede-41bf-97b6-32b261f6a968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158070758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.158070758
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2937629397
Short name T179
Test name
Test status
Simulation time 3628165327 ps
CPU time 11.16 seconds
Started Aug 07 06:51:02 PM PDT 24
Finished Aug 07 06:51:13 PM PDT 24
Peak memory 233216 kb
Host smart-8ef5b4f7-f789-420d-9d55-3e2b2388ca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937629397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2937629397
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.463317480
Short name T200
Test name
Test status
Simulation time 8886327311 ps
CPU time 70.15 seconds
Started Aug 07 06:51:02 PM PDT 24
Finished Aug 07 06:52:12 PM PDT 24
Peak memory 233220 kb
Host smart-f2f61cd4-31ab-4397-bfc0-186a00583fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463317480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.463317480
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4058623755
Short name T334
Test name
Test status
Simulation time 57790057 ps
CPU time 2.26 seconds
Started Aug 07 06:51:00 PM PDT 24
Finished Aug 07 06:51:03 PM PDT 24
Peak memory 232872 kb
Host smart-b11f632e-5442-4a1e-8516-029789ae476d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058623755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4058623755
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4215865547
Short name T854
Test name
Test status
Simulation time 62874351 ps
CPU time 1.99 seconds
Started Aug 07 06:51:00 PM PDT 24
Finished Aug 07 06:51:02 PM PDT 24
Peak memory 224496 kb
Host smart-c4d6b7f3-43c8-4015-8508-c670a0abe119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215865547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4215865547
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3718833593
Short name T780
Test name
Test status
Simulation time 243267886 ps
CPU time 3.73 seconds
Started Aug 07 06:51:00 PM PDT 24
Finished Aug 07 06:51:04 PM PDT 24
Peak memory 223508 kb
Host smart-c32c497f-ed07-4d19-b5b6-ecce2d93035b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3718833593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3718833593
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1690653653
Short name T16
Test name
Test status
Simulation time 860501139459 ps
CPU time 393.85 seconds
Started Aug 07 06:51:07 PM PDT 24
Finished Aug 07 06:57:41 PM PDT 24
Peak memory 266952 kb
Host smart-fbd067a7-2d99-4e05-ba6a-fe3aef474b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690653653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1690653653
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2986679388
Short name T702
Test name
Test status
Simulation time 4349937509 ps
CPU time 20.91 seconds
Started Aug 07 06:50:55 PM PDT 24
Finished Aug 07 06:51:16 PM PDT 24
Peak memory 216992 kb
Host smart-e171257d-d5ae-4254-8d1e-9240aca40740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986679388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2986679388
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1929085411
Short name T512
Test name
Test status
Simulation time 5732381253 ps
CPU time 16.19 seconds
Started Aug 07 06:50:56 PM PDT 24
Finished Aug 07 06:51:13 PM PDT 24
Peak memory 216940 kb
Host smart-f9f7f6f5-9c29-4878-8d76-5476d7b5acfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929085411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1929085411
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3387803508
Short name T305
Test name
Test status
Simulation time 282895565 ps
CPU time 9.55 seconds
Started Aug 07 06:51:00 PM PDT 24
Finished Aug 07 06:51:10 PM PDT 24
Peak memory 216688 kb
Host smart-b1c7c36d-3e81-4e88-ae48-c1919f6589d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387803508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3387803508
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4172343185
Short name T760
Test name
Test status
Simulation time 99791971 ps
CPU time 0.87 seconds
Started Aug 07 06:50:56 PM PDT 24
Finished Aug 07 06:50:57 PM PDT 24
Peak memory 206316 kb
Host smart-f8c1976e-e6d8-40c0-82c4-fc79a6bffc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172343185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4172343185
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3306453979
Short name T610
Test name
Test status
Simulation time 1782332243 ps
CPU time 3.84 seconds
Started Aug 07 06:51:01 PM PDT 24
Finished Aug 07 06:51:05 PM PDT 24
Peak memory 233180 kb
Host smart-03d1035e-a1d8-460b-820e-2537fa72b833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306453979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3306453979
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3074741337
Short name T326
Test name
Test status
Simulation time 12554238 ps
CPU time 0.71 seconds
Started Aug 07 06:51:22 PM PDT 24
Finished Aug 07 06:51:23 PM PDT 24
Peak memory 205844 kb
Host smart-47e03b97-9921-46e3-a0d9-bfb7af2959da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074741337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3074741337
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.652738613
Short name T433
Test name
Test status
Simulation time 274279025 ps
CPU time 2.87 seconds
Started Aug 07 06:51:14 PM PDT 24
Finished Aug 07 06:51:17 PM PDT 24
Peak memory 233076 kb
Host smart-5aef6573-91a5-471c-9d26-6cb2841c87c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652738613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.652738613
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.761414920
Short name T1001
Test name
Test status
Simulation time 15770813 ps
CPU time 0.78 seconds
Started Aug 07 06:51:07 PM PDT 24
Finished Aug 07 06:51:08 PM PDT 24
Peak memory 207328 kb
Host smart-3fd5e7f0-8782-4383-b60b-1a09d2e69c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761414920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.761414920
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2400695454
Short name T884
Test name
Test status
Simulation time 75324521740 ps
CPU time 556.61 seconds
Started Aug 07 06:51:12 PM PDT 24
Finished Aug 07 07:00:29 PM PDT 24
Peak memory 264092 kb
Host smart-82bfd977-0029-4645-a8f6-f027d8a25aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400695454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2400695454
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1153711199
Short name T181
Test name
Test status
Simulation time 15619355559 ps
CPU time 124.85 seconds
Started Aug 07 06:51:12 PM PDT 24
Finished Aug 07 06:53:17 PM PDT 24
Peak memory 257804 kb
Host smart-45b6e2d4-21a9-4415-954d-be0aa53385c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153711199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1153711199
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2876157957
Short name T480
Test name
Test status
Simulation time 3178807765 ps
CPU time 35.28 seconds
Started Aug 07 06:51:12 PM PDT 24
Finished Aug 07 06:51:48 PM PDT 24
Peak memory 233284 kb
Host smart-0bcb7a3d-f9d5-45eb-b096-3edd2707c6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876157957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2876157957
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4011540502
Short name T747
Test name
Test status
Simulation time 991960271 ps
CPU time 2.92 seconds
Started Aug 07 06:51:13 PM PDT 24
Finished Aug 07 06:51:16 PM PDT 24
Peak memory 233140 kb
Host smart-aba1c064-bc0d-4039-a7f8-34fb1feb47ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011540502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4011540502
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1690260407
Short name T539
Test name
Test status
Simulation time 41128025 ps
CPU time 0.73 seconds
Started Aug 07 06:51:13 PM PDT 24
Finished Aug 07 06:51:13 PM PDT 24
Peak memory 216136 kb
Host smart-584c4025-f27f-465f-9309-88bc59bb7362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690260407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1690260407
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2681832575
Short name T228
Test name
Test status
Simulation time 801993987 ps
CPU time 6.64 seconds
Started Aug 07 06:51:13 PM PDT 24
Finished Aug 07 06:51:20 PM PDT 24
Peak memory 224960 kb
Host smart-30676268-7634-4482-95dd-8b9dd8d437d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681832575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2681832575
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.374443511
Short name T673
Test name
Test status
Simulation time 11282597433 ps
CPU time 26.55 seconds
Started Aug 07 06:51:16 PM PDT 24
Finished Aug 07 06:51:42 PM PDT 24
Peak memory 233088 kb
Host smart-a9b0f5c5-6c88-4325-bff5-57bfd235b1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374443511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.374443511
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2994309699
Short name T839
Test name
Test status
Simulation time 338304935 ps
CPU time 5.58 seconds
Started Aug 07 06:51:12 PM PDT 24
Finished Aug 07 06:51:18 PM PDT 24
Peak memory 233164 kb
Host smart-0aba16ad-159c-4b84-82f9-ed9ea52a902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994309699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2994309699
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1902427762
Short name T710
Test name
Test status
Simulation time 7003344329 ps
CPU time 7.33 seconds
Started Aug 07 06:51:12 PM PDT 24
Finished Aug 07 06:51:20 PM PDT 24
Peak memory 233176 kb
Host smart-303850ca-d9da-4d3e-9af7-f2f7e6be0f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902427762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1902427762
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4283051505
Short name T949
Test name
Test status
Simulation time 1696339725 ps
CPU time 4.45 seconds
Started Aug 07 06:51:14 PM PDT 24
Finished Aug 07 06:51:18 PM PDT 24
Peak memory 222968 kb
Host smart-c65de3b0-c191-488a-8ee2-eeb610f5f4b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4283051505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4283051505
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2721233470
Short name T351
Test name
Test status
Simulation time 1357624128 ps
CPU time 8.53 seconds
Started Aug 07 06:51:09 PM PDT 24
Finished Aug 07 06:51:17 PM PDT 24
Peak memory 216744 kb
Host smart-e44acfe9-c888-4274-805d-6a7e3f5e49a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721233470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2721233470
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3343438792
Short name T1006
Test name
Test status
Simulation time 524984825 ps
CPU time 4.42 seconds
Started Aug 07 06:51:06 PM PDT 24
Finished Aug 07 06:51:11 PM PDT 24
Peak memory 216644 kb
Host smart-1fd0dc97-315a-42d8-86d7-58e4b6579d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343438792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3343438792
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1710742362
Short name T10
Test name
Test status
Simulation time 153833931 ps
CPU time 1.12 seconds
Started Aug 07 06:51:05 PM PDT 24
Finished Aug 07 06:51:06 PM PDT 24
Peak memory 208220 kb
Host smart-cee46235-a0fc-46d9-b53b-ccf8c7543807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710742362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1710742362
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2947171634
Short name T372
Test name
Test status
Simulation time 169591869 ps
CPU time 0.96 seconds
Started Aug 07 06:51:06 PM PDT 24
Finished Aug 07 06:51:07 PM PDT 24
Peak memory 206352 kb
Host smart-287ffec4-12fe-4f95-8cea-52cecfb40f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947171634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2947171634
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3608992401
Short name T22
Test name
Test status
Simulation time 139475738 ps
CPU time 2.35 seconds
Started Aug 07 06:51:12 PM PDT 24
Finished Aug 07 06:51:15 PM PDT 24
Peak memory 232756 kb
Host smart-8314642d-9c28-4f42-ae64-72ef930d1de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608992401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3608992401
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4242548702
Short name T412
Test name
Test status
Simulation time 32965586 ps
CPU time 0.71 seconds
Started Aug 07 06:51:27 PM PDT 24
Finished Aug 07 06:51:28 PM PDT 24
Peak memory 205828 kb
Host smart-41d9d38e-bd08-42fe-b11b-462e7adb0ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242548702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4242548702
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2548449867
Short name T792
Test name
Test status
Simulation time 141623856 ps
CPU time 2.33 seconds
Started Aug 07 06:51:24 PM PDT 24
Finished Aug 07 06:51:27 PM PDT 24
Peak memory 224912 kb
Host smart-481dffe3-3ac7-4b8e-b09c-cbd653f08aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548449867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2548449867
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2233016461
Short name T914
Test name
Test status
Simulation time 23632239 ps
CPU time 0.83 seconds
Started Aug 07 06:51:22 PM PDT 24
Finished Aug 07 06:51:23 PM PDT 24
Peak memory 207300 kb
Host smart-837d8190-c2c3-4edf-84a0-8cef26a489f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233016461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2233016461
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4025024387
Short name T823
Test name
Test status
Simulation time 2673249629 ps
CPU time 67.31 seconds
Started Aug 07 06:51:25 PM PDT 24
Finished Aug 07 06:52:33 PM PDT 24
Peak memory 249700 kb
Host smart-f7802b1f-f9f5-4ac5-8076-e7d64994d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025024387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4025024387
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.787101695
Short name T153
Test name
Test status
Simulation time 1930510256 ps
CPU time 55.04 seconds
Started Aug 07 06:51:26 PM PDT 24
Finished Aug 07 06:52:21 PM PDT 24
Peak memory 249616 kb
Host smart-4947ebda-4ba0-4291-b310-679b8bef5401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787101695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.787101695
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2440108984
Short name T267
Test name
Test status
Simulation time 302702457034 ps
CPU time 505.39 seconds
Started Aug 07 06:51:23 PM PDT 24
Finished Aug 07 06:59:49 PM PDT 24
Peak memory 257304 kb
Host smart-5851fb77-779f-46b8-8c1d-e3ce9daa9393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440108984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2440108984
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2522427539
Short name T357
Test name
Test status
Simulation time 423740778 ps
CPU time 2.92 seconds
Started Aug 07 06:51:25 PM PDT 24
Finished Aug 07 06:51:28 PM PDT 24
Peak memory 224948 kb
Host smart-194767c2-8f2c-4036-bc03-85fab5603236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522427539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2522427539
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.946432331
Short name T166
Test name
Test status
Simulation time 3337195955 ps
CPU time 22.37 seconds
Started Aug 07 06:51:24 PM PDT 24
Finished Aug 07 06:51:47 PM PDT 24
Peak memory 234996 kb
Host smart-55d345a0-7284-40a2-bba7-8aaf16ed9a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946432331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.946432331
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2834631895
Short name T540
Test name
Test status
Simulation time 7353392701 ps
CPU time 17.54 seconds
Started Aug 07 06:51:21 PM PDT 24
Finished Aug 07 06:51:38 PM PDT 24
Peak memory 225040 kb
Host smart-9ab7c7db-505b-4382-b9c1-7f538102ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834631895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2834631895
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2672077128
Short name T756
Test name
Test status
Simulation time 2322901559 ps
CPU time 13.55 seconds
Started Aug 07 06:51:23 PM PDT 24
Finished Aug 07 06:51:37 PM PDT 24
Peak memory 240460 kb
Host smart-52149566-4865-4b3f-b8b5-e573446d9609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672077128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2672077128
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.979482508
Short name T245
Test name
Test status
Simulation time 5904333611 ps
CPU time 15.77 seconds
Started Aug 07 06:51:23 PM PDT 24
Finished Aug 07 06:51:39 PM PDT 24
Peak memory 233196 kb
Host smart-f9ca497e-26a8-44df-bd33-fa4973ca90f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979482508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.979482508
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1123424942
Short name T485
Test name
Test status
Simulation time 251230910 ps
CPU time 5 seconds
Started Aug 07 06:51:21 PM PDT 24
Finished Aug 07 06:51:27 PM PDT 24
Peak memory 241084 kb
Host smart-5857627c-9b48-4a5e-939e-615a62e34568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123424942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1123424942
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3789256409
Short name T956
Test name
Test status
Simulation time 251252753 ps
CPU time 3.58 seconds
Started Aug 07 06:51:26 PM PDT 24
Finished Aug 07 06:51:30 PM PDT 24
Peak memory 223020 kb
Host smart-b4b3ae8b-e6b9-4cf6-a684-2053340ecba8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3789256409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3789256409
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2974895447
Short name T146
Test name
Test status
Simulation time 7017041258 ps
CPU time 38.5 seconds
Started Aug 07 06:51:26 PM PDT 24
Finished Aug 07 06:52:05 PM PDT 24
Peak memory 237072 kb
Host smart-5c4018d6-52c4-459d-97a1-d1adca0bfe56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974895447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2974895447
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2974103553
Short name T742
Test name
Test status
Simulation time 8755354128 ps
CPU time 36.84 seconds
Started Aug 07 06:51:24 PM PDT 24
Finished Aug 07 06:52:01 PM PDT 24
Peak memory 216664 kb
Host smart-bf4efd6b-5f13-414d-a1c1-105e51be99e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974103553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2974103553
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2378714137
Short name T765
Test name
Test status
Simulation time 127729303 ps
CPU time 1.2 seconds
Started Aug 07 06:51:21 PM PDT 24
Finished Aug 07 06:51:23 PM PDT 24
Peak memory 208300 kb
Host smart-41cb8269-75bf-45e6-8bbb-0a3a15f334e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378714137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2378714137
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1574172879
Short name T325
Test name
Test status
Simulation time 537753346 ps
CPU time 1.25 seconds
Started Aug 07 06:51:24 PM PDT 24
Finished Aug 07 06:51:25 PM PDT 24
Peak memory 208260 kb
Host smart-b1fe94de-4b58-4d80-8b0c-e32097f5296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574172879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1574172879
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3483106695
Short name T752
Test name
Test status
Simulation time 49236598 ps
CPU time 0.89 seconds
Started Aug 07 06:51:20 PM PDT 24
Finished Aug 07 06:51:21 PM PDT 24
Peak memory 207368 kb
Host smart-de6880e6-576e-460f-bbfd-a6b8a9acc270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483106695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3483106695
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3742849557
Short name T896
Test name
Test status
Simulation time 262572558 ps
CPU time 4.62 seconds
Started Aug 07 06:51:22 PM PDT 24
Finished Aug 07 06:51:27 PM PDT 24
Peak memory 233084 kb
Host smart-ebe77c49-419f-477b-aa1f-8d1c5917d7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742849557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3742849557
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2642024243
Short name T622
Test name
Test status
Simulation time 30487755 ps
CPU time 0.72 seconds
Started Aug 07 06:51:34 PM PDT 24
Finished Aug 07 06:51:35 PM PDT 24
Peak memory 205820 kb
Host smart-380855d1-cce4-419d-8d42-041532ab6c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642024243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2642024243
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2411514817
Short name T858
Test name
Test status
Simulation time 1444373086 ps
CPU time 6.32 seconds
Started Aug 07 06:51:35 PM PDT 24
Finished Aug 07 06:51:41 PM PDT 24
Peak memory 233060 kb
Host smart-58020c90-6bf2-4bce-bc0c-c045461dedf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411514817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2411514817
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3310709023
Short name T640
Test name
Test status
Simulation time 27540852 ps
CPU time 0.75 seconds
Started Aug 07 06:51:27 PM PDT 24
Finished Aug 07 06:51:28 PM PDT 24
Peak memory 206240 kb
Host smart-de3f8373-5f14-4833-8fbb-ad85068806fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310709023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3310709023
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1445752986
Short name T968
Test name
Test status
Simulation time 105819525212 ps
CPU time 44.91 seconds
Started Aug 07 06:51:35 PM PDT 24
Finished Aug 07 06:52:20 PM PDT 24
Peak memory 218080 kb
Host smart-06a413cd-6b8e-4df8-9945-8259a707f117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445752986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1445752986
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1938744909
Short name T587
Test name
Test status
Simulation time 44352187221 ps
CPU time 246.02 seconds
Started Aug 07 06:51:35 PM PDT 24
Finished Aug 07 06:55:41 PM PDT 24
Peak memory 271192 kb
Host smart-b15954ad-971e-48fc-b7d4-f84599488929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938744909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1938744909
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2661923918
Short name T431
Test name
Test status
Simulation time 1410239840 ps
CPU time 7.51 seconds
Started Aug 07 06:51:33 PM PDT 24
Finished Aug 07 06:51:41 PM PDT 24
Peak memory 233120 kb
Host smart-3a7d6bb0-f158-4143-ac05-a1352ba598c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661923918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2661923918
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1555743950
Short name T168
Test name
Test status
Simulation time 9260698679 ps
CPU time 32.18 seconds
Started Aug 07 06:51:34 PM PDT 24
Finished Aug 07 06:52:07 PM PDT 24
Peak memory 237648 kb
Host smart-03c603b9-ca55-4407-91bf-7778c4d70ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555743950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1555743950
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2100048505
Short name T66
Test name
Test status
Simulation time 1169102663 ps
CPU time 4.58 seconds
Started Aug 07 06:51:31 PM PDT 24
Finished Aug 07 06:51:36 PM PDT 24
Peak memory 219248 kb
Host smart-504cbe93-95ee-4dd9-a688-77b1bcad24fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100048505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2100048505
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2961188357
Short name T724
Test name
Test status
Simulation time 455567302 ps
CPU time 6.01 seconds
Started Aug 07 06:51:28 PM PDT 24
Finished Aug 07 06:51:34 PM PDT 24
Peak memory 233160 kb
Host smart-1689824d-0610-4b74-8a69-d67c73fbb62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961188357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2961188357
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2288276875
Short name T284
Test name
Test status
Simulation time 12215193701 ps
CPU time 6.11 seconds
Started Aug 07 06:51:29 PM PDT 24
Finished Aug 07 06:51:35 PM PDT 24
Peak memory 224908 kb
Host smart-dd80400b-f1af-4dae-abca-1cde9f00b6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288276875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2288276875
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1573108392
Short name T546
Test name
Test status
Simulation time 232714332 ps
CPU time 4.51 seconds
Started Aug 07 06:51:30 PM PDT 24
Finished Aug 07 06:51:34 PM PDT 24
Peak memory 224988 kb
Host smart-ce4aebe4-8c8c-4b87-9fda-5c7b1e504cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573108392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1573108392
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2139615190
Short name T964
Test name
Test status
Simulation time 4347337153 ps
CPU time 6.92 seconds
Started Aug 07 06:51:36 PM PDT 24
Finished Aug 07 06:51:43 PM PDT 24
Peak memory 220980 kb
Host smart-55a12f92-6182-4c4b-ae94-a477452c303f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2139615190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2139615190
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3586606718
Short name T650
Test name
Test status
Simulation time 2455461816 ps
CPU time 19.98 seconds
Started Aug 07 06:51:31 PM PDT 24
Finished Aug 07 06:51:51 PM PDT 24
Peak memory 225008 kb
Host smart-18047434-e860-4970-91de-fbbf17e34f53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586606718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3586606718
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.202778183
Short name T948
Test name
Test status
Simulation time 3194607658 ps
CPU time 17.02 seconds
Started Aug 07 06:51:32 PM PDT 24
Finished Aug 07 06:51:49 PM PDT 24
Peak memory 220300 kb
Host smart-e398c2db-c01d-4364-b43a-0f16f8271bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202778183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.202778183
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.684688003
Short name T691
Test name
Test status
Simulation time 27039576013 ps
CPU time 16.92 seconds
Started Aug 07 06:51:31 PM PDT 24
Finished Aug 07 06:51:48 PM PDT 24
Peak memory 216840 kb
Host smart-e512b4dd-8199-4cff-bdb9-6011ff59636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684688003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.684688003
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2086690285
Short name T397
Test name
Test status
Simulation time 701905174 ps
CPU time 1.5 seconds
Started Aug 07 06:51:29 PM PDT 24
Finished Aug 07 06:51:30 PM PDT 24
Peak memory 216684 kb
Host smart-cf73a6ca-f5e0-489e-9ed1-674e2dd32b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086690285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2086690285
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1751718892
Short name T919
Test name
Test status
Simulation time 203289753 ps
CPU time 0.94 seconds
Started Aug 07 06:51:29 PM PDT 24
Finished Aug 07 06:51:30 PM PDT 24
Peak memory 206888 kb
Host smart-a88aad53-60f5-4041-87ca-40b966531740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751718892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1751718892
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2706957927
Short name T233
Test name
Test status
Simulation time 2318793486 ps
CPU time 12.22 seconds
Started Aug 07 06:51:28 PM PDT 24
Finished Aug 07 06:51:41 PM PDT 24
Peak memory 233208 kb
Host smart-d7e99fd3-4dd9-4811-8056-3921d04445ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706957927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2706957927
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3923803640
Short name T771
Test name
Test status
Simulation time 29058080 ps
CPU time 0.74 seconds
Started Aug 07 06:51:47 PM PDT 24
Finished Aug 07 06:51:47 PM PDT 24
Peak memory 206164 kb
Host smart-df4746d8-c006-4b3f-a6ce-8fcaaa232b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923803640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3923803640
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2695592963
Short name T790
Test name
Test status
Simulation time 34940360 ps
CPU time 2.6 seconds
Started Aug 07 06:51:46 PM PDT 24
Finished Aug 07 06:51:49 PM PDT 24
Peak memory 232708 kb
Host smart-8e34f4e0-dcb2-4807-9f8c-9b355f60698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695592963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2695592963
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3543425737
Short name T535
Test name
Test status
Simulation time 14013633 ps
CPU time 0.78 seconds
Started Aug 07 06:51:34 PM PDT 24
Finished Aug 07 06:51:35 PM PDT 24
Peak memory 206920 kb
Host smart-331bb390-d7c9-42b1-9b53-2313b99857f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543425737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3543425737
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2016192922
Short name T392
Test name
Test status
Simulation time 5884831925 ps
CPU time 63.5 seconds
Started Aug 07 06:51:38 PM PDT 24
Finished Aug 07 06:52:42 PM PDT 24
Peak memory 250168 kb
Host smart-39d17f95-a880-44ba-9009-da70ae1583e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016192922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2016192922
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2296353459
Short name T637
Test name
Test status
Simulation time 1281580884 ps
CPU time 21.12 seconds
Started Aug 07 06:51:48 PM PDT 24
Finished Aug 07 06:52:09 PM PDT 24
Peak memory 234268 kb
Host smart-b3d191d7-9b01-4bb6-84d2-81a0a09902d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296353459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2296353459
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3486241577
Short name T468
Test name
Test status
Simulation time 269886491 ps
CPU time 7.32 seconds
Started Aug 07 06:51:39 PM PDT 24
Finished Aug 07 06:51:47 PM PDT 24
Peak memory 236728 kb
Host smart-7ce182ce-8ad6-4ea6-94eb-8f7c3b3a64a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486241577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3486241577
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2645016072
Short name T269
Test name
Test status
Simulation time 128518853106 ps
CPU time 284.6 seconds
Started Aug 07 06:51:38 PM PDT 24
Finished Aug 07 06:56:23 PM PDT 24
Peak memory 263516 kb
Host smart-60c070c4-57f6-42b5-b9b3-9ee003eb6f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645016072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2645016072
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2797224253
Short name T824
Test name
Test status
Simulation time 1430560788 ps
CPU time 8.32 seconds
Started Aug 07 06:51:45 PM PDT 24
Finished Aug 07 06:51:53 PM PDT 24
Peak memory 233156 kb
Host smart-c1db2b09-b9fc-40ec-ae8e-f554d4659b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797224253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2797224253
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2859208047
Short name T173
Test name
Test status
Simulation time 7539726447 ps
CPU time 14.49 seconds
Started Aug 07 06:51:39 PM PDT 24
Finished Aug 07 06:51:54 PM PDT 24
Peak memory 224964 kb
Host smart-292f163c-07e4-4ae8-8745-625577aeea5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859208047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2859208047
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1573547400
Short name T571
Test name
Test status
Simulation time 59138561 ps
CPU time 2.59 seconds
Started Aug 07 06:51:45 PM PDT 24
Finished Aug 07 06:51:48 PM PDT 24
Peak memory 233116 kb
Host smart-40c003a8-54b5-4520-81cf-e5d51fd73cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573547400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1573547400
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2171456228
Short name T853
Test name
Test status
Simulation time 60600149 ps
CPU time 2.55 seconds
Started Aug 07 06:51:45 PM PDT 24
Finished Aug 07 06:51:48 PM PDT 24
Peak memory 224944 kb
Host smart-c6699b7d-2d01-45c5-acd8-ae6e29b61ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171456228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2171456228
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2738479540
Short name T421
Test name
Test status
Simulation time 792461655 ps
CPU time 6.01 seconds
Started Aug 07 06:51:39 PM PDT 24
Finished Aug 07 06:51:45 PM PDT 24
Peak memory 220068 kb
Host smart-14527dbc-fedd-42c7-9bab-b7dd1307e549
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2738479540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2738479540
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.104054559
Short name T120
Test name
Test status
Simulation time 3686196084 ps
CPU time 66.55 seconds
Started Aug 07 06:51:46 PM PDT 24
Finished Aug 07 06:52:53 PM PDT 24
Peak memory 257500 kb
Host smart-165a1456-ee15-4386-aad7-10ae0fe2f0ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104054559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.104054559
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1733310879
Short name T377
Test name
Test status
Simulation time 3824053600 ps
CPU time 10.79 seconds
Started Aug 07 06:51:33 PM PDT 24
Finished Aug 07 06:51:44 PM PDT 24
Peak memory 216696 kb
Host smart-276f6e7a-503d-4544-af33-8c1b905d3950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733310879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1733310879
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2559126668
Short name T725
Test name
Test status
Simulation time 7479941021 ps
CPU time 20.59 seconds
Started Aug 07 06:51:37 PM PDT 24
Finished Aug 07 06:51:57 PM PDT 24
Peak memory 216744 kb
Host smart-0dcdcb8e-4d2a-4d79-9ce9-90b63f8b27fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559126668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2559126668
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3265058146
Short name T737
Test name
Test status
Simulation time 589710900 ps
CPU time 2.39 seconds
Started Aug 07 06:51:40 PM PDT 24
Finished Aug 07 06:51:43 PM PDT 24
Peak memory 216644 kb
Host smart-279be92e-67c9-4b7e-b8bf-034e427e9d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265058146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3265058146
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3154076900
Short name T834
Test name
Test status
Simulation time 100278626 ps
CPU time 0.74 seconds
Started Aug 07 06:51:39 PM PDT 24
Finished Aug 07 06:51:40 PM PDT 24
Peak memory 206360 kb
Host smart-dc8918ca-c396-4ca8-94c0-5d1b75e58da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154076900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3154076900
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1111799646
Short name T704
Test name
Test status
Simulation time 17859088476 ps
CPU time 13.86 seconds
Started Aug 07 06:51:38 PM PDT 24
Finished Aug 07 06:51:52 PM PDT 24
Peak memory 239008 kb
Host smart-ee15437e-db0e-4ce5-87b9-11921de9f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111799646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1111799646
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3489125767
Short name T458
Test name
Test status
Simulation time 13031648 ps
CPU time 0.71 seconds
Started Aug 07 06:51:52 PM PDT 24
Finished Aug 07 06:51:53 PM PDT 24
Peak memory 205268 kb
Host smart-f0641d9d-a6b8-4f97-a4bf-4f365ae6f788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489125767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3489125767
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.890518699
Short name T962
Test name
Test status
Simulation time 77726028 ps
CPU time 2.87 seconds
Started Aug 07 06:51:48 PM PDT 24
Finished Aug 07 06:51:51 PM PDT 24
Peak memory 233136 kb
Host smart-69f21e79-e719-46a3-a3ce-657945c25302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890518699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.890518699
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1905105170
Short name T635
Test name
Test status
Simulation time 53929608 ps
CPU time 0.81 seconds
Started Aug 07 06:51:47 PM PDT 24
Finished Aug 07 06:51:48 PM PDT 24
Peak memory 206984 kb
Host smart-37e71db6-ecce-4e76-bbb9-e7ea09826e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905105170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1905105170
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.50617016
Short name T359
Test name
Test status
Simulation time 18265638 ps
CPU time 0.74 seconds
Started Aug 07 06:51:49 PM PDT 24
Finished Aug 07 06:51:50 PM PDT 24
Peak memory 216144 kb
Host smart-ff59277c-ce01-4b8d-81ae-4fd6cef3de7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50617016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.50617016
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3888085780
Short name T243
Test name
Test status
Simulation time 28942608113 ps
CPU time 163.83 seconds
Started Aug 07 06:51:50 PM PDT 24
Finished Aug 07 06:54:34 PM PDT 24
Peak memory 256020 kb
Host smart-6385f7eb-ab5e-48d2-986c-cb4b66f617f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888085780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3888085780
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4044151082
Short name T893
Test name
Test status
Simulation time 12880994254 ps
CPU time 48.92 seconds
Started Aug 07 06:51:53 PM PDT 24
Finished Aug 07 06:52:42 PM PDT 24
Peak memory 250196 kb
Host smart-5b7cc2d2-a225-4c38-b525-a6a269a49bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044151082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4044151082
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3489595108
Short name T327
Test name
Test status
Simulation time 14770262670 ps
CPU time 59.06 seconds
Started Aug 07 06:51:48 PM PDT 24
Finished Aug 07 06:52:47 PM PDT 24
Peak memory 233192 kb
Host smart-f7ea8cdd-4491-4d95-a715-6a98514ea448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489595108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3489595108
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3096324291
Short name T746
Test name
Test status
Simulation time 40591333020 ps
CPU time 30.86 seconds
Started Aug 07 06:51:48 PM PDT 24
Finished Aug 07 06:52:19 PM PDT 24
Peak memory 233152 kb
Host smart-012dd4aa-f3ba-4259-9b95-42a6f40aeb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096324291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3096324291
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3846859252
Short name T508
Test name
Test status
Simulation time 26813506723 ps
CPU time 186.96 seconds
Started Aug 07 06:51:49 PM PDT 24
Finished Aug 07 06:54:56 PM PDT 24
Peak memory 252956 kb
Host smart-c9644f01-a30b-4fd0-89af-af95ec3d94cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846859252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3846859252
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1517438686
Short name T754
Test name
Test status
Simulation time 8009652368 ps
CPU time 17.42 seconds
Started Aug 07 06:51:44 PM PDT 24
Finished Aug 07 06:52:01 PM PDT 24
Peak memory 233216 kb
Host smart-18f23f75-436f-44d0-9a9d-bdf690542a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517438686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1517438686
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3687297045
Short name T677
Test name
Test status
Simulation time 32085738 ps
CPU time 2.45 seconds
Started Aug 07 06:51:45 PM PDT 24
Finished Aug 07 06:51:47 PM PDT 24
Peak memory 232696 kb
Host smart-ce37d5c7-6462-4ba3-a5dd-66dd7a8bd217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687297045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3687297045
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2948345835
Short name T381
Test name
Test status
Simulation time 322675217 ps
CPU time 6.9 seconds
Started Aug 07 06:51:48 PM PDT 24
Finished Aug 07 06:51:55 PM PDT 24
Peak memory 223432 kb
Host smart-1b0171b6-510e-43e7-9d27-1401fc56780e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2948345835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2948345835
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1282431510
Short name T454
Test name
Test status
Simulation time 33421780425 ps
CPU time 139.3 seconds
Started Aug 07 06:51:52 PM PDT 24
Finished Aug 07 06:54:11 PM PDT 24
Peak memory 264264 kb
Host smart-a3bc3b6f-2042-4ff3-99ab-872ced0f6fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282431510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1282431510
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3128431804
Short name T419
Test name
Test status
Simulation time 60523562 ps
CPU time 0.71 seconds
Started Aug 07 06:51:47 PM PDT 24
Finished Aug 07 06:51:48 PM PDT 24
Peak memory 206060 kb
Host smart-e3d91b72-e086-41ea-bfce-13a6c5490348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128431804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3128431804
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1476023807
Short name T669
Test name
Test status
Simulation time 1080862949 ps
CPU time 6.9 seconds
Started Aug 07 06:51:45 PM PDT 24
Finished Aug 07 06:51:52 PM PDT 24
Peak memory 216656 kb
Host smart-58566bd2-9f34-42e5-a6a2-66a5bf643940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476023807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1476023807
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2043936118
Short name T840
Test name
Test status
Simulation time 51762418 ps
CPU time 1.01 seconds
Started Aug 07 06:51:46 PM PDT 24
Finished Aug 07 06:51:48 PM PDT 24
Peak memory 208228 kb
Host smart-ee33ea7e-1ac4-461b-a740-1f6405e73187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043936118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2043936118
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2527743183
Short name T25
Test name
Test status
Simulation time 557290724 ps
CPU time 0.78 seconds
Started Aug 07 06:51:43 PM PDT 24
Finished Aug 07 06:51:44 PM PDT 24
Peak memory 206340 kb
Host smart-ad4d357f-a5d5-42b2-9f54-c9e2d114b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527743183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2527743183
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1110503067
Short name T814
Test name
Test status
Simulation time 13488843315 ps
CPU time 13.79 seconds
Started Aug 07 06:51:51 PM PDT 24
Finished Aug 07 06:52:04 PM PDT 24
Peak memory 224944 kb
Host smart-89fe7612-4834-46f3-bf7e-273c3a9766c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110503067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1110503067
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3417712989
Short name T591
Test name
Test status
Simulation time 17397855 ps
CPU time 0.73 seconds
Started Aug 07 06:46:10 PM PDT 24
Finished Aug 07 06:46:11 PM PDT 24
Peak memory 205876 kb
Host smart-b41bc27c-4a15-4eeb-bda2-6e143d4428b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417712989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
417712989
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4125110096
Short name T750
Test name
Test status
Simulation time 1510431071 ps
CPU time 15.05 seconds
Started Aug 07 06:46:04 PM PDT 24
Finished Aug 07 06:46:19 PM PDT 24
Peak memory 233100 kb
Host smart-968cdfe7-616e-4184-9225-e37884959978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125110096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4125110096
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2010993442
Short name T656
Test name
Test status
Simulation time 15109049 ps
CPU time 0.78 seconds
Started Aug 07 06:46:00 PM PDT 24
Finished Aug 07 06:46:01 PM PDT 24
Peak memory 206948 kb
Host smart-a786aa50-b28f-4898-a575-819e627c42fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010993442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2010993442
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3164860711
Short name T373
Test name
Test status
Simulation time 7613911469 ps
CPU time 84.2 seconds
Started Aug 07 06:46:10 PM PDT 24
Finished Aug 07 06:47:34 PM PDT 24
Peak memory 249592 kb
Host smart-97b8e80a-21fd-439d-88b7-e873e6d9255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164860711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3164860711
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3626823333
Short name T920
Test name
Test status
Simulation time 5042905974 ps
CPU time 52.13 seconds
Started Aug 07 06:46:10 PM PDT 24
Finished Aug 07 06:47:02 PM PDT 24
Peak memory 241428 kb
Host smart-f76aa4ec-ebab-4249-b2b2-af0559cb2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626823333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3626823333
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1957904182
Short name T486
Test name
Test status
Simulation time 38762634209 ps
CPU time 105.6 seconds
Started Aug 07 06:46:10 PM PDT 24
Finished Aug 07 06:47:56 PM PDT 24
Peak memory 249620 kb
Host smart-26942761-5384-41b4-9216-c21d2a68554f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957904182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1957904182
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1652342517
Short name T437
Test name
Test status
Simulation time 677386942 ps
CPU time 14.62 seconds
Started Aug 07 06:46:14 PM PDT 24
Finished Aug 07 06:46:29 PM PDT 24
Peak memory 224912 kb
Host smart-680e697b-d670-46e5-ae3d-9783a9df1eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652342517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1652342517
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3446066704
Short name T795
Test name
Test status
Simulation time 8141220447 ps
CPU time 13.09 seconds
Started Aug 07 06:46:04 PM PDT 24
Finished Aug 07 06:46:17 PM PDT 24
Peak memory 235964 kb
Host smart-8437b082-dda7-40da-b240-6bba9811755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446066704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3446066704
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2040943966
Short name T177
Test name
Test status
Simulation time 8114411623 ps
CPU time 21.72 seconds
Started Aug 07 06:46:04 PM PDT 24
Finished Aug 07 06:46:26 PM PDT 24
Peak memory 233220 kb
Host smart-91e4d594-d380-4ac8-9354-4c4b56018c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040943966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2040943966
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.784499744
Short name T937
Test name
Test status
Simulation time 111107451 ps
CPU time 2.2 seconds
Started Aug 07 06:46:05 PM PDT 24
Finished Aug 07 06:46:07 PM PDT 24
Peak memory 227264 kb
Host smart-c6efdb76-93e2-4553-8804-05f1055e0f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784499744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.784499744
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2003612560
Short name T242
Test name
Test status
Simulation time 4264417050 ps
CPU time 8.99 seconds
Started Aug 07 06:46:05 PM PDT 24
Finished Aug 07 06:46:14 PM PDT 24
Peak memory 233228 kb
Host smart-1d1d8219-7115-4249-8968-d5775c2f7258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003612560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2003612560
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1149543506
Short name T612
Test name
Test status
Simulation time 1242307562 ps
CPU time 5.06 seconds
Started Aug 07 06:46:05 PM PDT 24
Finished Aug 07 06:46:11 PM PDT 24
Peak memory 224880 kb
Host smart-63bae223-82f8-4224-a3f5-de6abfe1c569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149543506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1149543506
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.743843084
Short name T378
Test name
Test status
Simulation time 331178274 ps
CPU time 4 seconds
Started Aug 07 06:46:06 PM PDT 24
Finished Aug 07 06:46:10 PM PDT 24
Peak memory 219560 kb
Host smart-45afeb3b-fd2a-4eaa-bfa5-f3cd6a6e2fcc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=743843084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.743843084
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3390890684
Short name T58
Test name
Test status
Simulation time 155562915 ps
CPU time 1.2 seconds
Started Aug 07 06:46:11 PM PDT 24
Finished Aug 07 06:46:12 PM PDT 24
Peak memory 236444 kb
Host smart-9731b6b3-953d-401d-91be-d2e36502e751
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390890684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3390890684
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2908842063
Short name T877
Test name
Test status
Simulation time 29704539247 ps
CPU time 170.6 seconds
Started Aug 07 06:46:10 PM PDT 24
Finished Aug 07 06:49:00 PM PDT 24
Peak memory 255596 kb
Host smart-0922fd3f-5e54-473a-aace-66247e078f39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908842063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2908842063
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.256757927
Short name T745
Test name
Test status
Simulation time 3602870624 ps
CPU time 9.25 seconds
Started Aug 07 06:46:05 PM PDT 24
Finished Aug 07 06:46:15 PM PDT 24
Peak memory 216696 kb
Host smart-50e22589-e874-48e8-923d-c9661505377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256757927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.256757927
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.542748414
Short name T329
Test name
Test status
Simulation time 3807163063 ps
CPU time 4.86 seconds
Started Aug 07 06:46:04 PM PDT 24
Finished Aug 07 06:46:09 PM PDT 24
Peak memory 216676 kb
Host smart-d3ebea9a-1939-453d-a583-d4824d963eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542748414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.542748414
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2113430418
Short name T815
Test name
Test status
Simulation time 132346931 ps
CPU time 2.09 seconds
Started Aug 07 06:46:04 PM PDT 24
Finished Aug 07 06:46:06 PM PDT 24
Peak memory 216700 kb
Host smart-4bcf6102-da83-41d2-96bb-829dc53b46d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113430418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2113430418
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1006868723
Short name T643
Test name
Test status
Simulation time 65610238 ps
CPU time 0.92 seconds
Started Aug 07 06:46:04 PM PDT 24
Finished Aug 07 06:46:05 PM PDT 24
Peak memory 206300 kb
Host smart-342c96df-16b4-4b69-8909-a6d76d228369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006868723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1006868723
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3901988496
Short name T655
Test name
Test status
Simulation time 279385357 ps
CPU time 2.26 seconds
Started Aug 07 06:46:04 PM PDT 24
Finished Aug 07 06:46:06 PM PDT 24
Peak memory 224476 kb
Host smart-0dd9cb97-7acc-427a-9d95-b9c78914f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901988496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3901988496
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.407171246
Short name T996
Test name
Test status
Simulation time 25337003 ps
CPU time 0.74 seconds
Started Aug 07 06:52:00 PM PDT 24
Finished Aug 07 06:52:00 PM PDT 24
Peak memory 205280 kb
Host smart-0a4f95fa-19ba-4c66-af25-57c94848c1f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407171246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.407171246
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.717682517
Short name T686
Test name
Test status
Simulation time 633046687 ps
CPU time 10.17 seconds
Started Aug 07 06:51:59 PM PDT 24
Finished Aug 07 06:52:10 PM PDT 24
Peak memory 224972 kb
Host smart-b702b9b6-6a0a-4eee-8fa1-2409fd716223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717682517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.717682517
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3524941057
Short name T388
Test name
Test status
Simulation time 13871989 ps
CPU time 0.81 seconds
Started Aug 07 06:51:54 PM PDT 24
Finished Aug 07 06:51:55 PM PDT 24
Peak memory 206984 kb
Host smart-d96c6d88-4b13-4500-a35e-9ebc13434861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524941057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3524941057
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1651475288
Short name T266
Test name
Test status
Simulation time 5579673958 ps
CPU time 102.08 seconds
Started Aug 07 06:52:00 PM PDT 24
Finished Aug 07 06:53:42 PM PDT 24
Peak memory 274172 kb
Host smart-dc8fe2bf-8572-402b-b693-4fed01004d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651475288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1651475288
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2111114685
Short name T642
Test name
Test status
Simulation time 1086883826 ps
CPU time 19.41 seconds
Started Aug 07 06:52:01 PM PDT 24
Finished Aug 07 06:52:20 PM PDT 24
Peak memory 225004 kb
Host smart-8d164a15-2bcb-4f0f-91d1-383f9c651ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111114685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2111114685
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1450768619
Short name T807
Test name
Test status
Simulation time 16983144240 ps
CPU time 41.97 seconds
Started Aug 07 06:52:00 PM PDT 24
Finished Aug 07 06:52:42 PM PDT 24
Peak memory 235840 kb
Host smart-01ade00d-64ca-4e20-96a5-6c724c9455cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450768619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1450768619
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2850211824
Short name T688
Test name
Test status
Simulation time 1465023752 ps
CPU time 5.75 seconds
Started Aug 07 06:52:00 PM PDT 24
Finished Aug 07 06:52:06 PM PDT 24
Peak memory 224948 kb
Host smart-ab44a1e3-8126-44af-8e09-193e5a107837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850211824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2850211824
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2047124705
Short name T922
Test name
Test status
Simulation time 125019344959 ps
CPU time 264.08 seconds
Started Aug 07 06:51:59 PM PDT 24
Finished Aug 07 06:56:23 PM PDT 24
Peak memory 266008 kb
Host smart-436664cf-a133-4217-b50c-8b5a3c542e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047124705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2047124705
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.889020881
Short name T861
Test name
Test status
Simulation time 161942685 ps
CPU time 4.42 seconds
Started Aug 07 06:51:53 PM PDT 24
Finished Aug 07 06:51:58 PM PDT 24
Peak memory 233160 kb
Host smart-3d6025cd-0a0c-4529-99b9-5d9d8c8b953c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889020881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.889020881
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1766706955
Short name T254
Test name
Test status
Simulation time 1147252130 ps
CPU time 12.22 seconds
Started Aug 07 06:51:52 PM PDT 24
Finished Aug 07 06:52:05 PM PDT 24
Peak memory 233096 kb
Host smart-dba2e71e-2b2e-4355-b480-4b47d4bbbb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766706955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1766706955
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1399030860
Short name T641
Test name
Test status
Simulation time 25384550919 ps
CPU time 18.08 seconds
Started Aug 07 06:51:55 PM PDT 24
Finished Aug 07 06:52:13 PM PDT 24
Peak memory 224964 kb
Host smart-3b8bb2bf-5aae-448d-bc5b-4b5e3f078a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399030860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1399030860
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.220199835
Short name T441
Test name
Test status
Simulation time 836663103 ps
CPU time 6.58 seconds
Started Aug 07 06:51:55 PM PDT 24
Finished Aug 07 06:52:02 PM PDT 24
Peak memory 224888 kb
Host smart-fb5345b3-d4b3-4a23-bc1e-3ce002377f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220199835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.220199835
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.596797277
Short name T671
Test name
Test status
Simulation time 2302610619 ps
CPU time 11.43 seconds
Started Aug 07 06:51:59 PM PDT 24
Finished Aug 07 06:52:10 PM PDT 24
Peak memory 223652 kb
Host smart-bac53f66-3ec3-493d-8cb1-84f6d163c0c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=596797277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.596797277
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.453290400
Short name T333
Test name
Test status
Simulation time 5905732595 ps
CPU time 11.68 seconds
Started Aug 07 06:51:53 PM PDT 24
Finished Aug 07 06:52:05 PM PDT 24
Peak memory 216772 kb
Host smart-3a71041a-8e48-4311-a5cd-69f0940ff90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453290400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.453290400
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.354653290
Short name T797
Test name
Test status
Simulation time 2492681571 ps
CPU time 5.92 seconds
Started Aug 07 06:51:53 PM PDT 24
Finished Aug 07 06:51:59 PM PDT 24
Peak memory 216696 kb
Host smart-d8ecd6ea-d90f-44f8-955c-dbf22f58da12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354653290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.354653290
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4109274131
Short name T559
Test name
Test status
Simulation time 238998850 ps
CPU time 1.55 seconds
Started Aug 07 06:51:56 PM PDT 24
Finished Aug 07 06:51:58 PM PDT 24
Peak memory 216636 kb
Host smart-098bce84-1606-4852-83cb-499e4e83e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109274131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4109274131
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3087920840
Short name T356
Test name
Test status
Simulation time 1311798165 ps
CPU time 0.99 seconds
Started Aug 07 06:51:54 PM PDT 24
Finished Aug 07 06:51:55 PM PDT 24
Peak memory 207356 kb
Host smart-68a5b034-e7db-438e-b6f2-e5704d78102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087920840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3087920840
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3433649818
Short name T806
Test name
Test status
Simulation time 17821625432 ps
CPU time 24.22 seconds
Started Aug 07 06:52:00 PM PDT 24
Finished Aug 07 06:52:25 PM PDT 24
Peak memory 241308 kb
Host smart-4f7077bd-295c-4e63-a510-4634fa94c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433649818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3433649818
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2113795105
Short name T542
Test name
Test status
Simulation time 13588132 ps
CPU time 0.7 seconds
Started Aug 07 06:52:10 PM PDT 24
Finished Aug 07 06:52:11 PM PDT 24
Peak memory 205892 kb
Host smart-f5398dc3-3a14-4675-a0ed-2c0c650feb9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113795105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2113795105
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1285496887
Short name T235
Test name
Test status
Simulation time 272925324 ps
CPU time 4.13 seconds
Started Aug 07 06:52:04 PM PDT 24
Finished Aug 07 06:52:08 PM PDT 24
Peak memory 233176 kb
Host smart-cf0fb965-ed89-4f97-aad9-f09b550ec21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285496887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1285496887
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2108426759
Short name T503
Test name
Test status
Simulation time 19849781 ps
CPU time 0.78 seconds
Started Aug 07 06:51:59 PM PDT 24
Finished Aug 07 06:52:00 PM PDT 24
Peak memory 206948 kb
Host smart-fc1b4abf-079e-446c-8df6-af8b50d98258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108426759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2108426759
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.769689317
Short name T265
Test name
Test status
Simulation time 3183313490 ps
CPU time 68.37 seconds
Started Aug 07 06:52:05 PM PDT 24
Finished Aug 07 06:53:14 PM PDT 24
Peak memory 256176 kb
Host smart-9c93ec45-c4f8-4839-9420-3a91c9263b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769689317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.769689317
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.681614170
Short name T71
Test name
Test status
Simulation time 95714366454 ps
CPU time 422.91 seconds
Started Aug 07 06:52:07 PM PDT 24
Finished Aug 07 06:59:10 PM PDT 24
Peak memory 256076 kb
Host smart-aa8c7c9a-469f-4329-b9e6-4532984ce4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681614170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.681614170
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3043335464
Short name T211
Test name
Test status
Simulation time 34820144406 ps
CPU time 101.89 seconds
Started Aug 07 06:52:11 PM PDT 24
Finished Aug 07 06:53:53 PM PDT 24
Peak memory 255000 kb
Host smart-c7cdf371-e47b-4a59-a000-332bbef924ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043335464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3043335464
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3494742948
Short name T4
Test name
Test status
Simulation time 6030800853 ps
CPU time 16.54 seconds
Started Aug 07 06:52:05 PM PDT 24
Finished Aug 07 06:52:22 PM PDT 24
Peak memory 225028 kb
Host smart-e0dedd53-6f3e-40f3-bdda-b5fc051bb513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494742948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3494742948
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.4265239350
Short name T328
Test name
Test status
Simulation time 31125273 ps
CPU time 0.78 seconds
Started Aug 07 06:52:06 PM PDT 24
Finished Aug 07 06:52:07 PM PDT 24
Peak memory 216212 kb
Host smart-5363b920-994b-4395-bd60-6b9caac87ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265239350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.4265239350
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3508155860
Short name T709
Test name
Test status
Simulation time 681939169 ps
CPU time 8.04 seconds
Started Aug 07 06:52:06 PM PDT 24
Finished Aug 07 06:52:14 PM PDT 24
Peak memory 233208 kb
Host smart-6c6118e3-c03d-4999-b035-230c79b1441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508155860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3508155860
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2513005227
Short name T652
Test name
Test status
Simulation time 1327398362 ps
CPU time 12.9 seconds
Started Aug 07 06:52:05 PM PDT 24
Finished Aug 07 06:52:18 PM PDT 24
Peak memory 233100 kb
Host smart-1fd86da0-f8a1-4368-b4bb-70718d295c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513005227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2513005227
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3050969892
Short name T101
Test name
Test status
Simulation time 682828096 ps
CPU time 4.29 seconds
Started Aug 07 06:52:04 PM PDT 24
Finished Aug 07 06:52:09 PM PDT 24
Peak memory 233128 kb
Host smart-c2d7f5b0-31c6-497f-b3a7-89cfab30996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050969892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3050969892
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3089917846
Short name T519
Test name
Test status
Simulation time 319954084 ps
CPU time 3.23 seconds
Started Aug 07 06:52:04 PM PDT 24
Finished Aug 07 06:52:07 PM PDT 24
Peak memory 233092 kb
Host smart-28b9b243-6c84-446d-94d7-7a25dd6795ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089917846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3089917846
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3898573231
Short name T681
Test name
Test status
Simulation time 159176227 ps
CPU time 3.83 seconds
Started Aug 07 06:52:06 PM PDT 24
Finished Aug 07 06:52:10 PM PDT 24
Peak memory 219956 kb
Host smart-63f9cd9a-98e7-4a16-9ea5-4707b64fd09e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3898573231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3898573231
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3951949089
Short name T740
Test name
Test status
Simulation time 13425267558 ps
CPU time 20.27 seconds
Started Aug 07 06:52:05 PM PDT 24
Finished Aug 07 06:52:25 PM PDT 24
Peak memory 216804 kb
Host smart-dc7faa98-ac32-414b-86c3-f7b8443d1273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951949089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3951949089
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4234267278
Short name T645
Test name
Test status
Simulation time 15247273015 ps
CPU time 10.7 seconds
Started Aug 07 06:52:05 PM PDT 24
Finished Aug 07 06:52:15 PM PDT 24
Peak memory 216620 kb
Host smart-bbf3df14-5e69-4716-ad34-68b870cc38dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234267278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4234267278
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2083391938
Short name T636
Test name
Test status
Simulation time 94189028 ps
CPU time 1.46 seconds
Started Aug 07 06:52:05 PM PDT 24
Finished Aug 07 06:52:06 PM PDT 24
Peak memory 216728 kb
Host smart-c3efd8ae-da7b-4c40-9f18-be04e83339c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083391938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2083391938
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2826165161
Short name T826
Test name
Test status
Simulation time 12911836 ps
CPU time 0.7 seconds
Started Aug 07 06:52:05 PM PDT 24
Finished Aug 07 06:52:06 PM PDT 24
Peak memory 205992 kb
Host smart-6be0c642-5eec-45c3-a549-11240ff98f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826165161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2826165161
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3151503756
Short name T986
Test name
Test status
Simulation time 1869179582 ps
CPU time 6.13 seconds
Started Aug 07 06:52:05 PM PDT 24
Finished Aug 07 06:52:11 PM PDT 24
Peak memory 224816 kb
Host smart-cdfab145-db50-49d4-85c4-84b996d6ba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151503756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3151503756
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4070863671
Short name T317
Test name
Test status
Simulation time 47165935 ps
CPU time 0.73 seconds
Started Aug 07 06:52:20 PM PDT 24
Finished Aug 07 06:52:21 PM PDT 24
Peak memory 205820 kb
Host smart-5e950ca0-9ad7-4462-ab79-b8da65d3a9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070863671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4070863671
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.273066890
Short name T668
Test name
Test status
Simulation time 390707017 ps
CPU time 3.78 seconds
Started Aug 07 06:52:14 PM PDT 24
Finished Aug 07 06:52:18 PM PDT 24
Peak memory 224908 kb
Host smart-c56804a6-3a0f-4743-9923-4991cbc5835f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273066890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.273066890
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2066023548
Short name T115
Test name
Test status
Simulation time 28250912 ps
CPU time 0.77 seconds
Started Aug 07 06:52:10 PM PDT 24
Finished Aug 07 06:52:11 PM PDT 24
Peak memory 206316 kb
Host smart-67247741-2e1e-4f9e-9a4e-02d65f9404f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066023548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2066023548
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1984849207
Short name T418
Test name
Test status
Simulation time 15588898167 ps
CPU time 105.96 seconds
Started Aug 07 06:52:13 PM PDT 24
Finished Aug 07 06:53:59 PM PDT 24
Peak memory 241360 kb
Host smart-61d9d348-132a-4f69-9af5-dbc37355273b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984849207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1984849207
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3198392408
Short name T202
Test name
Test status
Simulation time 17514916562 ps
CPU time 104.87 seconds
Started Aug 07 06:52:21 PM PDT 24
Finished Aug 07 06:54:06 PM PDT 24
Peak memory 253768 kb
Host smart-cba2d23e-681e-445c-a4bd-a409d89e2a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198392408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3198392408
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.12293537
Short name T383
Test name
Test status
Simulation time 6003377276 ps
CPU time 77.18 seconds
Started Aug 07 06:52:20 PM PDT 24
Finished Aug 07 06:53:37 PM PDT 24
Peak memory 250700 kb
Host smart-80713f54-e79b-4d98-bc5b-dc57c69b72cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12293537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.12293537
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4216247433
Short name T979
Test name
Test status
Simulation time 904094814 ps
CPU time 13.6 seconds
Started Aug 07 06:52:15 PM PDT 24
Finished Aug 07 06:52:29 PM PDT 24
Peak memory 233096 kb
Host smart-a592d0f7-c9ea-4500-ba91-951cb045d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216247433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4216247433
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3502741344
Short name T534
Test name
Test status
Simulation time 425266725 ps
CPU time 8.51 seconds
Started Aug 07 06:52:15 PM PDT 24
Finished Aug 07 06:52:24 PM PDT 24
Peak memory 224968 kb
Host smart-59ffa142-78d8-44f6-adc8-b024443a0b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502741344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3502741344
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3487250760
Short name T400
Test name
Test status
Simulation time 239508209 ps
CPU time 4.62 seconds
Started Aug 07 06:52:15 PM PDT 24
Finished Aug 07 06:52:19 PM PDT 24
Peak memory 220192 kb
Host smart-c075112d-57e3-4a23-a63b-514dbee6593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487250760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3487250760
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3238927262
Short name T818
Test name
Test status
Simulation time 1597531042 ps
CPU time 3.75 seconds
Started Aug 07 06:52:15 PM PDT 24
Finished Aug 07 06:52:19 PM PDT 24
Peak memory 224844 kb
Host smart-b4ba66a9-fa8e-4af4-89cb-d4596b1ad6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238927262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3238927262
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2182927007
Short name T423
Test name
Test status
Simulation time 4059459460 ps
CPU time 13.42 seconds
Started Aug 07 06:52:13 PM PDT 24
Finished Aug 07 06:52:26 PM PDT 24
Peak memory 240956 kb
Host smart-0e0ef772-9fc6-48fa-b749-7330e02a015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182927007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2182927007
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.20175937
Short name T829
Test name
Test status
Simulation time 5200825894 ps
CPU time 10.11 seconds
Started Aug 07 06:52:11 PM PDT 24
Finished Aug 07 06:52:21 PM PDT 24
Peak memory 233096 kb
Host smart-391f00e8-46e2-476c-b5fb-6973003aca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20175937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.20175937
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.431095511
Short name T62
Test name
Test status
Simulation time 23546251991 ps
CPU time 14.56 seconds
Started Aug 07 06:52:15 PM PDT 24
Finished Aug 07 06:52:30 PM PDT 24
Peak memory 222776 kb
Host smart-012d3aaa-a6c8-447f-9a20-5230af7a1dee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=431095511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.431095511
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1600040702
Short name T607
Test name
Test status
Simulation time 91582393141 ps
CPU time 155.7 seconds
Started Aug 07 06:52:21 PM PDT 24
Finished Aug 07 06:54:57 PM PDT 24
Peak memory 250428 kb
Host smart-6fb886cc-6842-4097-b87c-776ad8444ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600040702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1600040702
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3819424838
Short name T971
Test name
Test status
Simulation time 6981654026 ps
CPU time 22.87 seconds
Started Aug 07 06:52:10 PM PDT 24
Finished Aug 07 06:52:33 PM PDT 24
Peak memory 220344 kb
Host smart-501cc39f-10fc-426d-b091-574673129328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819424838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3819424838
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1216845433
Short name T70
Test name
Test status
Simulation time 1414840687 ps
CPU time 4.82 seconds
Started Aug 07 06:52:09 PM PDT 24
Finished Aug 07 06:52:14 PM PDT 24
Peak memory 216676 kb
Host smart-cc0e872c-38bc-4069-b63b-913fc686dcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216845433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1216845433
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4061770949
Short name T343
Test name
Test status
Simulation time 438918927 ps
CPU time 5.18 seconds
Started Aug 07 06:52:11 PM PDT 24
Finished Aug 07 06:52:16 PM PDT 24
Peak memory 216628 kb
Host smart-b76dc15a-c46b-41c6-8e4e-e7413f6594f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061770949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4061770949
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1601483190
Short name T477
Test name
Test status
Simulation time 26681896 ps
CPU time 0.78 seconds
Started Aug 07 06:52:10 PM PDT 24
Finished Aug 07 06:52:11 PM PDT 24
Peak memory 206348 kb
Host smart-2bcb15f1-07be-42a8-994f-bd1356fd6c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601483190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1601483190
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3223328551
Short name T403
Test name
Test status
Simulation time 895660565 ps
CPU time 2.79 seconds
Started Aug 07 06:52:15 PM PDT 24
Finished Aug 07 06:52:18 PM PDT 24
Peak memory 233128 kb
Host smart-71282043-81a9-43ce-8450-3c093fd64c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223328551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3223328551
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3562400487
Short name T716
Test name
Test status
Simulation time 46494795 ps
CPU time 0.72 seconds
Started Aug 07 06:52:24 PM PDT 24
Finished Aug 07 06:52:25 PM PDT 24
Peak memory 205280 kb
Host smart-1e008012-1745-43a2-ad95-2dbbd49b36d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562400487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3562400487
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3576091542
Short name T599
Test name
Test status
Simulation time 75612974 ps
CPU time 2.57 seconds
Started Aug 07 06:52:27 PM PDT 24
Finished Aug 07 06:52:30 PM PDT 24
Peak memory 233080 kb
Host smart-4878bfe7-9071-424a-8e88-c059b2128f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576091542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3576091542
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.900458423
Short name T983
Test name
Test status
Simulation time 67453233 ps
CPU time 0.78 seconds
Started Aug 07 06:52:19 PM PDT 24
Finished Aug 07 06:52:20 PM PDT 24
Peak memory 207008 kb
Host smart-af4b3541-4b8d-4fcc-bd90-22eb7ee37674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900458423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.900458423
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1456503018
Short name T187
Test name
Test status
Simulation time 5976776600 ps
CPU time 78.1 seconds
Started Aug 07 06:52:25 PM PDT 24
Finished Aug 07 06:53:43 PM PDT 24
Peak memory 265968 kb
Host smart-02715362-baef-41b2-95d9-936b6fcb3047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456503018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1456503018
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2189571539
Short name T420
Test name
Test status
Simulation time 12026775898 ps
CPU time 152.64 seconds
Started Aug 07 06:52:25 PM PDT 24
Finished Aug 07 06:54:58 PM PDT 24
Peak memory 257780 kb
Host smart-6e0c9ad3-1fe0-4e49-a702-050b01113357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189571539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2189571539
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2590637648
Short name T24
Test name
Test status
Simulation time 39857317365 ps
CPU time 77.68 seconds
Started Aug 07 06:52:24 PM PDT 24
Finished Aug 07 06:53:42 PM PDT 24
Peak memory 255344 kb
Host smart-124d1780-4768-498d-bea5-f4bc7f8323be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590637648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2590637648
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2281336688
Short name T609
Test name
Test status
Simulation time 98503766 ps
CPU time 2.75 seconds
Started Aug 07 06:52:27 PM PDT 24
Finished Aug 07 06:52:30 PM PDT 24
Peak memory 233120 kb
Host smart-c37bfeec-4bd4-4e5c-8920-676437b1b225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281336688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2281336688
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.999204838
Short name T167
Test name
Test status
Simulation time 71465516951 ps
CPU time 133.12 seconds
Started Aug 07 06:52:25 PM PDT 24
Finished Aug 07 06:54:38 PM PDT 24
Peak memory 255200 kb
Host smart-e3b06fc1-ac0c-4301-965f-c94c8035946f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999204838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.999204838
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1993626195
Short name T899
Test name
Test status
Simulation time 811383230 ps
CPU time 4.16 seconds
Started Aug 07 06:52:25 PM PDT 24
Finished Aug 07 06:52:29 PM PDT 24
Peak memory 233116 kb
Host smart-2bd76890-35bb-416a-a2f1-29e98f821898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993626195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1993626195
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2637602307
Short name T117
Test name
Test status
Simulation time 102943109 ps
CPU time 2.38 seconds
Started Aug 07 06:52:26 PM PDT 24
Finished Aug 07 06:52:28 PM PDT 24
Peak memory 224192 kb
Host smart-c094a58e-605c-4ea5-a978-7ae7604a5636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637602307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2637602307
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1606753050
Short name T332
Test name
Test status
Simulation time 186598678 ps
CPU time 2.17 seconds
Started Aug 07 06:52:25 PM PDT 24
Finished Aug 07 06:52:27 PM PDT 24
Peak memory 223424 kb
Host smart-32376373-efa0-4375-a79c-5d36840dab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606753050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1606753050
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3810208635
Short name T250
Test name
Test status
Simulation time 6870524750 ps
CPU time 9.4 seconds
Started Aug 07 06:52:24 PM PDT 24
Finished Aug 07 06:52:34 PM PDT 24
Peak memory 241192 kb
Host smart-14d9f653-0dac-447c-a727-109b8384c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810208635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3810208635
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3171265764
Short name T785
Test name
Test status
Simulation time 1603715165 ps
CPU time 3.74 seconds
Started Aug 07 06:52:24 PM PDT 24
Finished Aug 07 06:52:28 PM PDT 24
Peak memory 219536 kb
Host smart-f311f1fb-6aa5-4eb2-ae94-8884476d9e51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3171265764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3171265764
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3154171469
Short name T349
Test name
Test status
Simulation time 12035578 ps
CPU time 0.7 seconds
Started Aug 07 06:52:20 PM PDT 24
Finished Aug 07 06:52:21 PM PDT 24
Peak memory 206132 kb
Host smart-70ec1c89-c5b5-4416-888b-76ddf1541022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154171469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3154171469
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3023585641
Short name T975
Test name
Test status
Simulation time 23414257 ps
CPU time 0.71 seconds
Started Aug 07 06:52:20 PM PDT 24
Finished Aug 07 06:52:21 PM PDT 24
Peak memory 206056 kb
Host smart-8700793e-0fe5-4bc8-8c7c-2e3b62468e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023585641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3023585641
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.9586039
Short name T27
Test name
Test status
Simulation time 39013063 ps
CPU time 0.75 seconds
Started Aug 07 06:52:26 PM PDT 24
Finished Aug 07 06:52:27 PM PDT 24
Peak memory 206352 kb
Host smart-5e907184-1ec3-4148-a7a9-fa5a75b39bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9586039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.9586039
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3091084046
Short name T414
Test name
Test status
Simulation time 67165918 ps
CPU time 0.92 seconds
Started Aug 07 06:52:26 PM PDT 24
Finished Aug 07 06:52:27 PM PDT 24
Peak memory 206360 kb
Host smart-37a520ea-af16-4266-9d7f-c30b8eedafed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091084046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3091084046
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.152203701
Short name T886
Test name
Test status
Simulation time 10741717663 ps
CPU time 22.02 seconds
Started Aug 07 06:52:25 PM PDT 24
Finished Aug 07 06:52:47 PM PDT 24
Peak memory 241136 kb
Host smart-a79265b7-445b-4137-8f56-b87ae6f25f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152203701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.152203701
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2467669559
Short name T720
Test name
Test status
Simulation time 13184430 ps
CPU time 0.7 seconds
Started Aug 07 06:52:35 PM PDT 24
Finished Aug 07 06:52:36 PM PDT 24
Peak memory 205272 kb
Host smart-f6717391-827b-4eeb-9ac8-af1243048f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467669559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2467669559
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2799951353
Short name T172
Test name
Test status
Simulation time 529977685 ps
CPU time 8.16 seconds
Started Aug 07 06:52:32 PM PDT 24
Finished Aug 07 06:52:40 PM PDT 24
Peak memory 233068 kb
Host smart-d6ca7896-87f7-419e-8602-bc0680d9aa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799951353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2799951353
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3602148836
Short name T442
Test name
Test status
Simulation time 35976372 ps
CPU time 0.74 seconds
Started Aug 07 06:52:27 PM PDT 24
Finished Aug 07 06:52:27 PM PDT 24
Peak memory 205940 kb
Host smart-76a4a5ef-60d3-416c-a4a1-f7cf17ed18b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602148836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3602148836
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1487093329
Short name T272
Test name
Test status
Simulation time 339291158940 ps
CPU time 262.91 seconds
Started Aug 07 06:52:30 PM PDT 24
Finished Aug 07 06:56:53 PM PDT 24
Peak memory 271136 kb
Host smart-c746c956-4e75-4dd6-9843-724838921b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487093329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1487093329
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1370298186
Short name T938
Test name
Test status
Simulation time 6513545336 ps
CPU time 100.01 seconds
Started Aug 07 06:52:35 PM PDT 24
Finished Aug 07 06:54:15 PM PDT 24
Peak memory 249792 kb
Host smart-8cf11d4d-4f75-4794-b903-a56024928a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370298186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1370298186
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2582980597
Short name T225
Test name
Test status
Simulation time 14605865871 ps
CPU time 167.98 seconds
Started Aug 07 06:52:35 PM PDT 24
Finished Aug 07 06:55:23 PM PDT 24
Peak memory 256580 kb
Host smart-fc910d79-8cdf-4d7c-8737-a769f9aba7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582980597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2582980597
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1834907701
Short name T575
Test name
Test status
Simulation time 483119530 ps
CPU time 10.64 seconds
Started Aug 07 06:52:32 PM PDT 24
Finished Aug 07 06:52:43 PM PDT 24
Peak memory 233196 kb
Host smart-3fcae683-da11-401a-8930-b8413485c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834907701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1834907701
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3238253081
Short name T31
Test name
Test status
Simulation time 11629450686 ps
CPU time 63.81 seconds
Started Aug 07 06:52:32 PM PDT 24
Finished Aug 07 06:53:36 PM PDT 24
Peak memory 253628 kb
Host smart-7d17ac5b-7c0b-482f-a675-b172af9c9627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238253081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3238253081
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.445600141
Short name T654
Test name
Test status
Simulation time 2727163775 ps
CPU time 15.52 seconds
Started Aug 07 06:52:30 PM PDT 24
Finished Aug 07 06:52:46 PM PDT 24
Peak memory 225012 kb
Host smart-9e16be5e-582d-463c-ad3d-a4675d0f4735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445600141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.445600141
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.527735778
Short name T741
Test name
Test status
Simulation time 2145838815 ps
CPU time 6.45 seconds
Started Aug 07 06:52:30 PM PDT 24
Finished Aug 07 06:52:36 PM PDT 24
Peak memory 238856 kb
Host smart-4da54a6e-81e7-4f42-8444-0f4fe58933e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527735778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.527735778
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1346145605
Short name T257
Test name
Test status
Simulation time 3185459568 ps
CPU time 6.46 seconds
Started Aug 07 06:52:30 PM PDT 24
Finished Aug 07 06:52:37 PM PDT 24
Peak memory 233196 kb
Host smart-e0341839-16b1-4c9c-9a8f-55becc89ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346145605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1346145605
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4030234784
Short name T619
Test name
Test status
Simulation time 17394682698 ps
CPU time 13.55 seconds
Started Aug 07 06:52:30 PM PDT 24
Finished Aug 07 06:52:43 PM PDT 24
Peak memory 233216 kb
Host smart-1aa842ca-23be-474b-9225-9a8f7dfae87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030234784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4030234784
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2709948603
Short name T942
Test name
Test status
Simulation time 8961692103 ps
CPU time 8.62 seconds
Started Aug 07 06:52:32 PM PDT 24
Finished Aug 07 06:52:41 PM PDT 24
Peak memory 221136 kb
Host smart-afe99756-e86d-4775-b977-1de13d4807b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2709948603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2709948603
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.195652086
Short name T142
Test name
Test status
Simulation time 63758357262 ps
CPU time 131.72 seconds
Started Aug 07 06:52:35 PM PDT 24
Finished Aug 07 06:54:47 PM PDT 24
Peak memory 266012 kb
Host smart-92dd60c5-586a-4c04-88ec-96e096afdadf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195652086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.195652086
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2290163304
Short name T488
Test name
Test status
Simulation time 5715706853 ps
CPU time 29.01 seconds
Started Aug 07 06:52:27 PM PDT 24
Finished Aug 07 06:52:56 PM PDT 24
Peak memory 216676 kb
Host smart-c94579a7-2726-4bfb-adfa-46ae20a1e0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290163304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2290163304
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1406629458
Short name T698
Test name
Test status
Simulation time 3836372094 ps
CPU time 11.87 seconds
Started Aug 07 06:52:28 PM PDT 24
Finished Aug 07 06:52:40 PM PDT 24
Peak memory 216764 kb
Host smart-ac4915d1-124e-4af7-b8da-43edda22dfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406629458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1406629458
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3692830624
Short name T538
Test name
Test status
Simulation time 904970562 ps
CPU time 3.4 seconds
Started Aug 07 06:52:27 PM PDT 24
Finished Aug 07 06:52:30 PM PDT 24
Peak memory 216696 kb
Host smart-a4cdb8e7-ab4d-49f9-80d5-d8ddc6e3b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692830624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3692830624
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1365548541
Short name T811
Test name
Test status
Simulation time 21584944 ps
CPU time 0.73 seconds
Started Aug 07 06:52:25 PM PDT 24
Finished Aug 07 06:52:26 PM PDT 24
Peak memory 206304 kb
Host smart-84c31d59-2ee3-42e1-8bb1-fcc7de8e7182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365548541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1365548541
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1394519974
Short name T259
Test name
Test status
Simulation time 2799727569 ps
CPU time 4.44 seconds
Started Aug 07 06:52:31 PM PDT 24
Finished Aug 07 06:52:36 PM PDT 24
Peak memory 233132 kb
Host smart-5ba6c48c-b5f1-40e9-9f23-05ecac3a0527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394519974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1394519974
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3043750109
Short name T489
Test name
Test status
Simulation time 11658013 ps
CPU time 0.72 seconds
Started Aug 07 06:52:49 PM PDT 24
Finished Aug 07 06:52:50 PM PDT 24
Peak memory 205260 kb
Host smart-5363f7ec-583c-4e4d-8ec6-8793c3506f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043750109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3043750109
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2483375088
Short name T561
Test name
Test status
Simulation time 1312885790 ps
CPU time 14.62 seconds
Started Aug 07 06:52:42 PM PDT 24
Finished Aug 07 06:52:57 PM PDT 24
Peak memory 233092 kb
Host smart-064a4058-8f27-416f-9f8b-3ec8f4effb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483375088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2483375088
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3314275794
Short name T516
Test name
Test status
Simulation time 35832298 ps
CPU time 0.81 seconds
Started Aug 07 06:52:36 PM PDT 24
Finished Aug 07 06:52:37 PM PDT 24
Peak memory 207288 kb
Host smart-b1427bd6-2bd8-4297-8e62-203c68467f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314275794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3314275794
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2172917666
Short name T500
Test name
Test status
Simulation time 87771623449 ps
CPU time 163.26 seconds
Started Aug 07 06:52:39 PM PDT 24
Finished Aug 07 06:55:23 PM PDT 24
Peak memory 250804 kb
Host smart-99b619e5-80a5-41cf-8938-c32890c739ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172917666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2172917666
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.387423489
Short name T297
Test name
Test status
Simulation time 2812922629 ps
CPU time 27.26 seconds
Started Aug 07 06:52:41 PM PDT 24
Finished Aug 07 06:53:08 PM PDT 24
Peak memory 218016 kb
Host smart-30a7f034-3979-47e9-bd25-63f9b31ab61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387423489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.387423489
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1025780993
Short name T42
Test name
Test status
Simulation time 57707084281 ps
CPU time 120.18 seconds
Started Aug 07 06:52:42 PM PDT 24
Finished Aug 07 06:54:43 PM PDT 24
Peak memory 252944 kb
Host smart-2887571c-62d9-4ff1-9f52-09b732d1ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025780993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1025780993
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1073802068
Short name T287
Test name
Test status
Simulation time 473303351 ps
CPU time 7.11 seconds
Started Aug 07 06:52:43 PM PDT 24
Finished Aug 07 06:52:51 PM PDT 24
Peak memory 223912 kb
Host smart-7d19322b-99b5-4d4d-a67d-1f79f25f3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073802068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1073802068
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2581567278
Short name T566
Test name
Test status
Simulation time 4722781727 ps
CPU time 54.63 seconds
Started Aug 07 06:52:41 PM PDT 24
Finished Aug 07 06:53:36 PM PDT 24
Peak memory 265928 kb
Host smart-d05d9314-f8db-43a5-9ca6-65f4b562acfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581567278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2581567278
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.343741159
Short name T448
Test name
Test status
Simulation time 4244660314 ps
CPU time 10.15 seconds
Started Aug 07 06:52:44 PM PDT 24
Finished Aug 07 06:52:54 PM PDT 24
Peak memory 232156 kb
Host smart-928619c2-20e7-49c3-816c-9181cb97670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343741159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.343741159
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3679677907
Short name T868
Test name
Test status
Simulation time 1159312102 ps
CPU time 2.45 seconds
Started Aug 07 06:52:41 PM PDT 24
Finished Aug 07 06:52:43 PM PDT 24
Peak memory 224828 kb
Host smart-138a0976-f6b1-4ca9-a1c0-f3d638329041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679677907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3679677907
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.534001309
Short name T209
Test name
Test status
Simulation time 2126305707 ps
CPU time 9.87 seconds
Started Aug 07 06:52:42 PM PDT 24
Finished Aug 07 06:52:52 PM PDT 24
Peak memory 224892 kb
Host smart-a77234c5-a07c-4e72-b978-cacc97b7962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534001309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.534001309
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1884712982
Short name T781
Test name
Test status
Simulation time 310158220 ps
CPU time 4.22 seconds
Started Aug 07 06:52:36 PM PDT 24
Finished Aug 07 06:52:40 PM PDT 24
Peak memory 233080 kb
Host smart-c73dd2c7-0dd8-4c1a-a8ad-26d4d66e25d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884712982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1884712982
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1093840811
Short name T777
Test name
Test status
Simulation time 216783615 ps
CPU time 3.94 seconds
Started Aug 07 06:52:41 PM PDT 24
Finished Aug 07 06:52:45 PM PDT 24
Peak memory 223552 kb
Host smart-79e7ee7e-88ad-4590-a615-79510f18ee10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093840811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1093840811
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.554101763
Short name T20
Test name
Test status
Simulation time 21502722213 ps
CPU time 228.09 seconds
Started Aug 07 06:52:45 PM PDT 24
Finished Aug 07 06:56:33 PM PDT 24
Peak memory 252380 kb
Host smart-7f286270-d8e5-43d4-a63d-c0bdf1f2936d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554101763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.554101763
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4107501316
Short name T499
Test name
Test status
Simulation time 24175867304 ps
CPU time 34.66 seconds
Started Aug 07 06:52:39 PM PDT 24
Finished Aug 07 06:53:13 PM PDT 24
Peak memory 216676 kb
Host smart-6d38c9de-0878-4f37-bf24-018426bbcd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107501316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4107501316
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.705905070
Short name T666
Test name
Test status
Simulation time 6960078494 ps
CPU time 7.94 seconds
Started Aug 07 06:52:39 PM PDT 24
Finished Aug 07 06:52:47 PM PDT 24
Peak memory 216732 kb
Host smart-46ca5a61-cd55-4d22-9ff5-95a286627e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705905070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.705905070
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2255758450
Short name T860
Test name
Test status
Simulation time 78991717 ps
CPU time 1.16 seconds
Started Aug 07 06:52:35 PM PDT 24
Finished Aug 07 06:52:36 PM PDT 24
Peak memory 207752 kb
Host smart-eaa73612-cca5-4743-a2ae-4fc677c67ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255758450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2255758450
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2553665410
Short name T564
Test name
Test status
Simulation time 38483359 ps
CPU time 0.79 seconds
Started Aug 07 06:52:35 PM PDT 24
Finished Aug 07 06:52:36 PM PDT 24
Peak memory 206364 kb
Host smart-8d4fa66b-e4c6-478e-89e1-29abc7789222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553665410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2553665410
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2026014019
Short name T450
Test name
Test status
Simulation time 3184161558 ps
CPU time 7.68 seconds
Started Aug 07 06:52:43 PM PDT 24
Finished Aug 07 06:52:51 PM PDT 24
Peak memory 232152 kb
Host smart-9d8f1262-245f-4ce6-9421-3c0012e4c17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026014019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2026014019
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3619956763
Short name T916
Test name
Test status
Simulation time 3029341232 ps
CPU time 10.65 seconds
Started Aug 07 06:52:49 PM PDT 24
Finished Aug 07 06:53:00 PM PDT 24
Peak memory 224960 kb
Host smart-63f2582c-6c1d-4e9d-9be5-36de34b2e9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619956763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3619956763
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1177000641
Short name T867
Test name
Test status
Simulation time 12530324 ps
CPU time 0.76 seconds
Started Aug 07 06:52:45 PM PDT 24
Finished Aug 07 06:52:46 PM PDT 24
Peak memory 207308 kb
Host smart-58b6dea2-d47d-491e-8339-3ee585787065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177000641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1177000641
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1300702237
Short name T683
Test name
Test status
Simulation time 125936273684 ps
CPU time 163.31 seconds
Started Aug 07 06:52:50 PM PDT 24
Finished Aug 07 06:55:34 PM PDT 24
Peak memory 249484 kb
Host smart-ae562746-822e-4ccb-86b6-88ae5a87be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300702237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1300702237
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1819824145
Short name T664
Test name
Test status
Simulation time 5638191139 ps
CPU time 18.29 seconds
Started Aug 07 06:52:52 PM PDT 24
Finished Aug 07 06:53:11 PM PDT 24
Peak memory 218200 kb
Host smart-46b1893f-08c3-4d24-8502-a183f6ae1314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819824145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1819824145
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2738444017
Short name T277
Test name
Test status
Simulation time 4701887471 ps
CPU time 126.97 seconds
Started Aug 07 06:52:51 PM PDT 24
Finished Aug 07 06:54:59 PM PDT 24
Peak memory 265956 kb
Host smart-7ccbf60b-0e2f-4b07-82ef-d4f0e9faaeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738444017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2738444017
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2276288971
Short name T288
Test name
Test status
Simulation time 2338426118 ps
CPU time 7.54 seconds
Started Aug 07 06:52:45 PM PDT 24
Finished Aug 07 06:52:53 PM PDT 24
Peak memory 233228 kb
Host smart-ba371004-1535-4986-9d41-0d9b711764da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276288971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2276288971
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3487306675
Short name T565
Test name
Test status
Simulation time 18607047 ps
CPU time 0.75 seconds
Started Aug 07 06:52:52 PM PDT 24
Finished Aug 07 06:52:53 PM PDT 24
Peak memory 216164 kb
Host smart-455bd66b-b321-43d3-b722-9eede164a9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487306675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3487306675
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1793603983
Short name T222
Test name
Test status
Simulation time 652066431 ps
CPU time 5.13 seconds
Started Aug 07 06:52:46 PM PDT 24
Finished Aug 07 06:52:52 PM PDT 24
Peak memory 233144 kb
Host smart-c7c30b59-8314-4915-bbfa-80d2c80883de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793603983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1793603983
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.621750519
Short name T65
Test name
Test status
Simulation time 14454712196 ps
CPU time 23.31 seconds
Started Aug 07 06:52:48 PM PDT 24
Finished Aug 07 06:53:11 PM PDT 24
Peak memory 223048 kb
Host smart-b583a1b6-bb0e-4823-a4a9-d6711ac92699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621750519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.621750519
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3444385718
Short name T596
Test name
Test status
Simulation time 285727776 ps
CPU time 5.23 seconds
Started Aug 07 06:52:46 PM PDT 24
Finished Aug 07 06:52:51 PM PDT 24
Peak memory 241216 kb
Host smart-0cf4590e-eafa-4b2a-b856-565562e0fbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444385718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3444385718
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.852749699
Short name T513
Test name
Test status
Simulation time 45677087372 ps
CPU time 18.62 seconds
Started Aug 07 06:52:46 PM PDT 24
Finished Aug 07 06:53:05 PM PDT 24
Peak memory 224992 kb
Host smart-6233aeda-817b-4e40-bc7a-132eee1107c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852749699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.852749699
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1457863233
Short name T685
Test name
Test status
Simulation time 395708309 ps
CPU time 4.22 seconds
Started Aug 07 06:52:52 PM PDT 24
Finished Aug 07 06:52:56 PM PDT 24
Peak memory 223648 kb
Host smart-f1c05b3b-505a-4eb0-8d54-294d54c0a720
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1457863233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1457863233
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1915001759
Short name T192
Test name
Test status
Simulation time 113782524631 ps
CPU time 324.37 seconds
Started Aug 07 06:52:51 PM PDT 24
Finished Aug 07 06:58:16 PM PDT 24
Peak memory 272640 kb
Host smart-33f6f0c6-f56f-46ca-9cfb-586eeefb1020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915001759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1915001759
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.636372814
Short name T603
Test name
Test status
Simulation time 1365852007 ps
CPU time 9.07 seconds
Started Aug 07 06:52:47 PM PDT 24
Finished Aug 07 06:52:57 PM PDT 24
Peak memory 216988 kb
Host smart-f3f17621-d9d0-4563-bffb-a30010c35916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636372814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.636372814
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2145325258
Short name T335
Test name
Test status
Simulation time 1926945964 ps
CPU time 4.97 seconds
Started Aug 07 06:52:46 PM PDT 24
Finished Aug 07 06:52:51 PM PDT 24
Peak memory 215620 kb
Host smart-f0e29ae3-c869-4e69-9259-68599bcf0c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145325258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2145325258
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2306288531
Short name T23
Test name
Test status
Simulation time 13268947 ps
CPU time 0.79 seconds
Started Aug 07 06:52:46 PM PDT 24
Finished Aug 07 06:52:47 PM PDT 24
Peak memory 206368 kb
Host smart-b5f07321-5462-44d4-9d6c-537915cd0d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306288531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2306288531
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.499029288
Short name T875
Test name
Test status
Simulation time 14686744 ps
CPU time 0.73 seconds
Started Aug 07 06:52:46 PM PDT 24
Finished Aug 07 06:52:47 PM PDT 24
Peak memory 206324 kb
Host smart-cf53e964-53d1-4abe-8f4f-acf7929caaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499029288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.499029288
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1251547886
Short name T369
Test name
Test status
Simulation time 27306965813 ps
CPU time 24.67 seconds
Started Aug 07 06:52:46 PM PDT 24
Finished Aug 07 06:53:11 PM PDT 24
Peak memory 239988 kb
Host smart-c9057518-c17b-425a-a5c3-6dfb4b274a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251547886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1251547886
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2228235259
Short name T465
Test name
Test status
Simulation time 12882574 ps
CPU time 0.7 seconds
Started Aug 07 06:52:56 PM PDT 24
Finished Aug 07 06:52:57 PM PDT 24
Peak memory 206216 kb
Host smart-162b0238-ddba-4924-b674-46a4a9894443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228235259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2228235259
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3262871818
Short name T171
Test name
Test status
Simulation time 119965822 ps
CPU time 3.8 seconds
Started Aug 07 06:53:00 PM PDT 24
Finished Aug 07 06:53:03 PM PDT 24
Peak memory 233112 kb
Host smart-6b179746-6675-4922-8f3a-8f5281c70cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262871818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3262871818
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1439986901
Short name T816
Test name
Test status
Simulation time 48744067 ps
CPU time 0.8 seconds
Started Aug 07 06:52:52 PM PDT 24
Finished Aug 07 06:52:53 PM PDT 24
Peak memory 207000 kb
Host smart-1d0f1d9c-f2d7-4fcb-94ec-8af72d8f4ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439986901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1439986901
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4131167425
Short name T999
Test name
Test status
Simulation time 16257866286 ps
CPU time 67.06 seconds
Started Aug 07 06:52:56 PM PDT 24
Finished Aug 07 06:54:03 PM PDT 24
Peak memory 264900 kb
Host smart-503f4a60-9972-47dd-b75d-da80387031e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131167425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4131167425
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1145091165
Short name T1004
Test name
Test status
Simulation time 13116333258 ps
CPU time 128.61 seconds
Started Aug 07 06:52:58 PM PDT 24
Finished Aug 07 06:55:07 PM PDT 24
Peak memory 249452 kb
Host smart-7ac876c8-1002-4173-a728-5f14ad4b30b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145091165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1145091165
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3781292911
Short name T278
Test name
Test status
Simulation time 26844381759 ps
CPU time 233.21 seconds
Started Aug 07 06:52:58 PM PDT 24
Finished Aug 07 06:56:51 PM PDT 24
Peak memory 250840 kb
Host smart-5e81928c-998b-49cd-b01a-73d56b1974df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781292911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3781292911
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2398887669
Short name T909
Test name
Test status
Simulation time 4236008589 ps
CPU time 21.36 seconds
Started Aug 07 06:52:57 PM PDT 24
Finished Aug 07 06:53:19 PM PDT 24
Peak memory 233568 kb
Host smart-c02e8217-842b-42c9-9108-0ae704c64209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398887669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2398887669
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2313769113
Short name T897
Test name
Test status
Simulation time 37389187856 ps
CPU time 284.48 seconds
Started Aug 07 06:52:57 PM PDT 24
Finished Aug 07 06:57:41 PM PDT 24
Peak memory 254296 kb
Host smart-88824975-b647-421b-af6c-f3ee38f6b694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313769113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2313769113
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3685714327
Short name T843
Test name
Test status
Simulation time 477766020 ps
CPU time 4.34 seconds
Started Aug 07 06:52:56 PM PDT 24
Finished Aug 07 06:53:00 PM PDT 24
Peak memory 224920 kb
Host smart-a2a101b4-6b18-4021-aabf-c9132fe44a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685714327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3685714327
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1943956572
Short name T955
Test name
Test status
Simulation time 3221183505 ps
CPU time 22.81 seconds
Started Aug 07 06:52:55 PM PDT 24
Finished Aug 07 06:53:18 PM PDT 24
Peak memory 241232 kb
Host smart-52ce20ff-aeff-40b6-9c48-6e4c458a3b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943956572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1943956572
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1128394230
Short name T808
Test name
Test status
Simulation time 105777323 ps
CPU time 2.11 seconds
Started Aug 07 06:52:57 PM PDT 24
Finished Aug 07 06:52:59 PM PDT 24
Peak memory 224268 kb
Host smart-c66ce837-db6b-42b7-aa81-aa7d9110ec6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128394230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1128394230
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3702036535
Short name T672
Test name
Test status
Simulation time 29795089017 ps
CPU time 14.07 seconds
Started Aug 07 06:52:58 PM PDT 24
Finished Aug 07 06:53:12 PM PDT 24
Peak memory 224808 kb
Host smart-55d33635-4763-4017-8f24-89c54f6872a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702036535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3702036535
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3216078005
Short name T925
Test name
Test status
Simulation time 1055192248 ps
CPU time 4.18 seconds
Started Aug 07 06:52:56 PM PDT 24
Finished Aug 07 06:53:01 PM PDT 24
Peak memory 219636 kb
Host smart-af99a8dc-58e5-4c5c-a8c3-14ea5e2be50f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3216078005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3216078005
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1598778511
Short name T700
Test name
Test status
Simulation time 7583705921 ps
CPU time 114.28 seconds
Started Aug 07 06:52:59 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 266104 kb
Host smart-f50033a2-d6f3-4541-aada-9bd2a027efb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598778511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1598778511
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.832458754
Short name T974
Test name
Test status
Simulation time 6426980261 ps
CPU time 27.65 seconds
Started Aug 07 06:52:52 PM PDT 24
Finished Aug 07 06:53:20 PM PDT 24
Peak memory 216788 kb
Host smart-872ef6be-d5d7-495c-b796-fd266fd580f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832458754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.832458754
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2991874552
Short name T726
Test name
Test status
Simulation time 4565716960 ps
CPU time 12.74 seconds
Started Aug 07 06:53:01 PM PDT 24
Finished Aug 07 06:53:14 PM PDT 24
Peak memory 216764 kb
Host smart-0845d0c2-e138-4442-a173-8667e3d94691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991874552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2991874552
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2152675623
Short name T504
Test name
Test status
Simulation time 44526478 ps
CPU time 1.48 seconds
Started Aug 07 06:52:52 PM PDT 24
Finished Aug 07 06:52:53 PM PDT 24
Peak memory 216580 kb
Host smart-681df307-51ab-4540-8c8c-19a4c150134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152675623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2152675623
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3495642065
Short name T602
Test name
Test status
Simulation time 141850075 ps
CPU time 0.94 seconds
Started Aug 07 06:52:51 PM PDT 24
Finished Aug 07 06:52:52 PM PDT 24
Peak memory 206348 kb
Host smart-9d56fceb-5704-4cf6-86de-6f9c0c7de958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495642065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3495642065
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3967954809
Short name T984
Test name
Test status
Simulation time 1070916833 ps
CPU time 6.03 seconds
Started Aug 07 06:52:56 PM PDT 24
Finished Aug 07 06:53:03 PM PDT 24
Peak memory 233072 kb
Host smart-76341b08-57e6-4d59-8cf7-f91716a504b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967954809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3967954809
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1972412651
Short name T428
Test name
Test status
Simulation time 11932624 ps
CPU time 0.73 seconds
Started Aug 07 06:53:09 PM PDT 24
Finished Aug 07 06:53:09 PM PDT 24
Peak memory 205268 kb
Host smart-2feaa0fa-686c-4a48-a1bd-b164f9c6e631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972412651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1972412651
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3258849408
Short name T405
Test name
Test status
Simulation time 6890871846 ps
CPU time 16.08 seconds
Started Aug 07 06:53:02 PM PDT 24
Finished Aug 07 06:53:18 PM PDT 24
Peak memory 233172 kb
Host smart-7d1cdfe3-9b47-4061-9ed1-14e475b84c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258849408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3258849408
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3054488313
Short name T514
Test name
Test status
Simulation time 16148167 ps
CPU time 0.76 seconds
Started Aug 07 06:52:58 PM PDT 24
Finished Aug 07 06:52:59 PM PDT 24
Peak memory 207328 kb
Host smart-a2a46fa7-548a-4bed-ac2e-7400d7990196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054488313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3054488313
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.562695101
Short name T958
Test name
Test status
Simulation time 48150774725 ps
CPU time 173.05 seconds
Started Aug 07 06:53:00 PM PDT 24
Finished Aug 07 06:55:54 PM PDT 24
Peak memory 250548 kb
Host smart-83fdf178-de48-4329-92dd-88a957fa02df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562695101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.562695101
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1204536006
Short name T38
Test name
Test status
Simulation time 732018942121 ps
CPU time 509.6 seconds
Started Aug 07 06:53:00 PM PDT 24
Finished Aug 07 07:01:30 PM PDT 24
Peak memory 257848 kb
Host smart-6f0d3e00-f65b-48ee-8d70-b170b486a93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204536006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1204536006
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2620949896
Short name T45
Test name
Test status
Simulation time 4944682394 ps
CPU time 107.95 seconds
Started Aug 07 06:53:02 PM PDT 24
Finished Aug 07 06:54:50 PM PDT 24
Peak memory 269844 kb
Host smart-cc3f8b63-e2a3-4474-8c7e-4dacc18bf942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620949896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2620949896
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1212657101
Short name T805
Test name
Test status
Simulation time 653132990 ps
CPU time 7.75 seconds
Started Aug 07 06:53:05 PM PDT 24
Finished Aug 07 06:53:13 PM PDT 24
Peak memory 233132 kb
Host smart-60dcf37c-016b-4832-9420-ee2d2c9cde73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212657101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1212657101
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3065340031
Short name T729
Test name
Test status
Simulation time 32709169402 ps
CPU time 57.54 seconds
Started Aug 07 06:53:05 PM PDT 24
Finished Aug 07 06:54:03 PM PDT 24
Peak memory 241372 kb
Host smart-f95299f1-e819-4fb6-b753-2fca3805bbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065340031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3065340031
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2063366843
Short name T394
Test name
Test status
Simulation time 5193586852 ps
CPU time 10.96 seconds
Started Aug 07 06:53:02 PM PDT 24
Finished Aug 07 06:53:13 PM PDT 24
Peak memory 233236 kb
Host smart-8bc574ef-b3a7-4924-8883-1d4545b03761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063366843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2063366843
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1013814024
Short name T399
Test name
Test status
Simulation time 9294122672 ps
CPU time 55.69 seconds
Started Aug 07 06:53:05 PM PDT 24
Finished Aug 07 06:54:01 PM PDT 24
Peak memory 238144 kb
Host smart-3adcf108-d36a-464a-bdfd-568d36be6eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013814024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1013814024
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.689631302
Short name T593
Test name
Test status
Simulation time 553376299 ps
CPU time 6.22 seconds
Started Aug 07 06:53:02 PM PDT 24
Finished Aug 07 06:53:09 PM PDT 24
Peak memory 233160 kb
Host smart-184de4ff-45e3-4879-9c65-c6f4bb09a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689631302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.689631302
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3934440369
Short name T594
Test name
Test status
Simulation time 4003942472 ps
CPU time 13.61 seconds
Started Aug 07 06:53:02 PM PDT 24
Finished Aug 07 06:53:16 PM PDT 24
Peak memory 224900 kb
Host smart-c48b812e-aceb-4204-afd4-4e18a8d16c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934440369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3934440369
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1952471993
Short name T402
Test name
Test status
Simulation time 4769453479 ps
CPU time 15.43 seconds
Started Aug 07 06:53:03 PM PDT 24
Finished Aug 07 06:53:19 PM PDT 24
Peak memory 221264 kb
Host smart-02c039f6-1a2a-4d16-8d25-d3ec485c6d7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1952471993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1952471993
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.380646029
Short name T144
Test name
Test status
Simulation time 4520625416 ps
CPU time 32.42 seconds
Started Aug 07 06:53:06 PM PDT 24
Finished Aug 07 06:53:39 PM PDT 24
Peak memory 218336 kb
Host smart-9f3a044e-ed19-4825-bb67-2960236ea2f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380646029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.380646029
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2488732257
Short name T306
Test name
Test status
Simulation time 2524171774 ps
CPU time 16.84 seconds
Started Aug 07 06:53:01 PM PDT 24
Finished Aug 07 06:53:18 PM PDT 24
Peak memory 220500 kb
Host smart-1074e4d3-fba4-434c-b869-eb9230e57a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488732257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2488732257
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2581107305
Short name T340
Test name
Test status
Simulation time 1177315020 ps
CPU time 7.6 seconds
Started Aug 07 06:52:58 PM PDT 24
Finished Aug 07 06:53:06 PM PDT 24
Peak memory 216696 kb
Host smart-47010089-80e3-4ca6-8a4b-06826ddf7200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581107305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2581107305
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2050854117
Short name T977
Test name
Test status
Simulation time 121549581 ps
CPU time 4 seconds
Started Aug 07 06:53:00 PM PDT 24
Finished Aug 07 06:53:05 PM PDT 24
Peak memory 216720 kb
Host smart-147f331b-9756-488b-bc7c-4af050281003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050854117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2050854117
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3366884220
Short name T732
Test name
Test status
Simulation time 83121409 ps
CPU time 0.92 seconds
Started Aug 07 06:53:03 PM PDT 24
Finished Aug 07 06:53:04 PM PDT 24
Peak memory 206356 kb
Host smart-4cf38e64-50ff-470d-bafb-1424cebd5a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366884220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3366884220
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2210790704
Short name T646
Test name
Test status
Simulation time 12596177544 ps
CPU time 12.82 seconds
Started Aug 07 06:53:01 PM PDT 24
Finished Aug 07 06:53:14 PM PDT 24
Peak memory 224964 kb
Host smart-2ccd9786-adc4-400f-a42b-13119ca701ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210790704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2210790704
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.73565293
Short name T323
Test name
Test status
Simulation time 56562702 ps
CPU time 0.75 seconds
Started Aug 07 06:53:14 PM PDT 24
Finished Aug 07 06:53:15 PM PDT 24
Peak memory 205756 kb
Host smart-d39869f2-5bd8-40b2-8353-f129da340a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73565293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.73565293
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1384536274
Short name T976
Test name
Test status
Simulation time 112607471 ps
CPU time 2.39 seconds
Started Aug 07 06:53:11 PM PDT 24
Finished Aug 07 06:53:13 PM PDT 24
Peak memory 224864 kb
Host smart-36cf076a-22c9-4cfc-85f8-322438374e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384536274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1384536274
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3888947981
Short name T879
Test name
Test status
Simulation time 57042480 ps
CPU time 0.77 seconds
Started Aug 07 06:53:06 PM PDT 24
Finished Aug 07 06:53:07 PM PDT 24
Peak memory 206252 kb
Host smart-93e2520a-f1f7-425f-a711-f45e2da7d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888947981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3888947981
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.753111708
Short name T72
Test name
Test status
Simulation time 180395792624 ps
CPU time 261.07 seconds
Started Aug 07 06:53:13 PM PDT 24
Finished Aug 07 06:57:34 PM PDT 24
Peak memory 250596 kb
Host smart-9fe87fea-c98e-4ad3-8f91-cf0141c3f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753111708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.753111708
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2084853987
Short name T722
Test name
Test status
Simulation time 1495464140 ps
CPU time 21.79 seconds
Started Aug 07 06:53:13 PM PDT 24
Finished Aug 07 06:53:34 PM PDT 24
Peak memory 241348 kb
Host smart-08ee23f2-78cb-46a6-8e16-072d91731123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084853987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2084853987
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.614422313
Short name T398
Test name
Test status
Simulation time 25769495912 ps
CPU time 237.85 seconds
Started Aug 07 06:53:12 PM PDT 24
Finished Aug 07 06:57:10 PM PDT 24
Peak memory 257796 kb
Host smart-20401711-168f-44a1-910a-c92be5d08269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614422313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.614422313
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1728470906
Short name T289
Test name
Test status
Simulation time 1054682986 ps
CPU time 11.31 seconds
Started Aug 07 06:53:14 PM PDT 24
Finished Aug 07 06:53:25 PM PDT 24
Peak memory 233172 kb
Host smart-5fad2912-46ba-4a1c-a323-2db6867eb581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728470906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1728470906
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1895415726
Short name T193
Test name
Test status
Simulation time 145897652711 ps
CPU time 261.2 seconds
Started Aug 07 06:53:13 PM PDT 24
Finished Aug 07 06:57:34 PM PDT 24
Peak memory 268736 kb
Host smart-4daa41f4-3ef1-465a-b234-173b106cb58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895415726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1895415726
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2275517050
Short name T9
Test name
Test status
Simulation time 295152740 ps
CPU time 3.65 seconds
Started Aug 07 06:53:07 PM PDT 24
Finished Aug 07 06:53:11 PM PDT 24
Peak memory 233140 kb
Host smart-9a5ea7d2-3c27-4914-b01c-9f5a15e3092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275517050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2275517050
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1279422920
Short name T728
Test name
Test status
Simulation time 1843102899 ps
CPU time 12.48 seconds
Started Aug 07 06:53:14 PM PDT 24
Finished Aug 07 06:53:26 PM PDT 24
Peak memory 233008 kb
Host smart-f966f598-ea73-4460-bbfc-2ad9555f274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279422920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1279422920
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.656625052
Short name T930
Test name
Test status
Simulation time 4459379794 ps
CPU time 11.38 seconds
Started Aug 07 06:53:07 PM PDT 24
Finished Aug 07 06:53:19 PM PDT 24
Peak memory 241420 kb
Host smart-4f2e21e7-ce10-4ba9-beb1-937f93029afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656625052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.656625052
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3084623928
Short name T529
Test name
Test status
Simulation time 5779635934 ps
CPU time 11.42 seconds
Started Aug 07 06:53:07 PM PDT 24
Finished Aug 07 06:53:19 PM PDT 24
Peak memory 233228 kb
Host smart-b1f33191-07f1-488c-aa77-179e0e4be9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084623928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3084623928
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1444245390
Short name T126
Test name
Test status
Simulation time 92831824 ps
CPU time 3.86 seconds
Started Aug 07 06:53:13 PM PDT 24
Finished Aug 07 06:53:17 PM PDT 24
Peak memory 220256 kb
Host smart-f92241ef-9c52-4f7b-9d27-c5b62a69d68a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1444245390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1444245390
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3071970839
Short name T119
Test name
Test status
Simulation time 142877960218 ps
CPU time 67.13 seconds
Started Aug 07 06:53:14 PM PDT 24
Finished Aug 07 06:54:21 PM PDT 24
Peak memory 249644 kb
Host smart-1c2fde8d-516e-449e-940e-049526d50511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071970839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3071970839
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3266384679
Short name T299
Test name
Test status
Simulation time 8927126878 ps
CPU time 22.55 seconds
Started Aug 07 06:53:07 PM PDT 24
Finished Aug 07 06:53:29 PM PDT 24
Peak memory 221080 kb
Host smart-2872c1a8-5bc1-4fec-8823-2e1f6355d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266384679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3266384679
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1694863175
Short name T761
Test name
Test status
Simulation time 3677977211 ps
CPU time 12.27 seconds
Started Aug 07 06:53:07 PM PDT 24
Finished Aug 07 06:53:19 PM PDT 24
Peak memory 216620 kb
Host smart-11f364dd-d7b4-4a18-895e-b408e5422865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694863175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1694863175
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3480985481
Short name T40
Test name
Test status
Simulation time 1341678358 ps
CPU time 2.18 seconds
Started Aug 07 06:53:07 PM PDT 24
Finished Aug 07 06:53:09 PM PDT 24
Peak memory 216708 kb
Host smart-c0bdda82-88bc-4d1f-bdd7-7f9a8f3a7bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480985481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3480985481
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2095493252
Short name T626
Test name
Test status
Simulation time 199782543 ps
CPU time 0.75 seconds
Started Aug 07 06:53:05 PM PDT 24
Finished Aug 07 06:53:06 PM PDT 24
Peak memory 206312 kb
Host smart-5691efbc-c518-4553-824b-6e48fb095bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095493252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2095493252
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2601803222
Short name T99
Test name
Test status
Simulation time 6619677418 ps
CPU time 23.7 seconds
Started Aug 07 06:53:14 PM PDT 24
Finished Aug 07 06:53:37 PM PDT 24
Peak memory 250292 kb
Host smart-4b0bbd24-8f42-4392-b78a-ddb86cb6d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601803222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2601803222
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3800002007
Short name T533
Test name
Test status
Simulation time 12921435 ps
CPU time 0.75 seconds
Started Aug 07 06:46:23 PM PDT 24
Finished Aug 07 06:46:24 PM PDT 24
Peak memory 205296 kb
Host smart-23611423-c3f8-4160-8ec4-26045f43e5e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800002007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
800002007
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1257890635
Short name T322
Test name
Test status
Simulation time 108533518 ps
CPU time 2.81 seconds
Started Aug 07 06:46:20 PM PDT 24
Finished Aug 07 06:46:23 PM PDT 24
Peak memory 224888 kb
Host smart-04199ad8-7f5b-4b6d-a77d-fc637990540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257890635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1257890635
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4286079427
Short name T775
Test name
Test status
Simulation time 34713511 ps
CPU time 0.77 seconds
Started Aug 07 06:46:10 PM PDT 24
Finished Aug 07 06:46:10 PM PDT 24
Peak memory 206940 kb
Host smart-f88c2549-e3b8-4c2f-9501-1b474f016b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286079427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4286079427
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4215731012
Short name T693
Test name
Test status
Simulation time 42017330284 ps
CPU time 108.42 seconds
Started Aug 07 06:46:18 PM PDT 24
Finished Aug 07 06:48:07 PM PDT 24
Peak memory 256848 kb
Host smart-3355c69b-b725-461d-823f-b6f47dd200e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215731012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4215731012
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3616628193
Short name T29
Test name
Test status
Simulation time 62050699349 ps
CPU time 103.64 seconds
Started Aug 07 06:46:18 PM PDT 24
Finished Aug 07 06:48:01 PM PDT 24
Peak memory 249664 kb
Host smart-3d7d845d-f27d-41b5-99b9-dd4e521e7116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616628193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3616628193
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3536917420
Short name T772
Test name
Test status
Simulation time 11003903805 ps
CPU time 146.89 seconds
Started Aug 07 06:46:20 PM PDT 24
Finished Aug 07 06:48:47 PM PDT 24
Peak memory 265124 kb
Host smart-25d0c222-5303-44d7-8a2c-eaccb2640b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536917420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3536917420
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3521232522
Short name T295
Test name
Test status
Simulation time 274841978 ps
CPU time 4.63 seconds
Started Aug 07 06:46:15 PM PDT 24
Finished Aug 07 06:46:20 PM PDT 24
Peak memory 233136 kb
Host smart-fa453992-10d9-4866-85bf-83d657218aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521232522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3521232522
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3739224939
Short name T280
Test name
Test status
Simulation time 23018234598 ps
CPU time 65.02 seconds
Started Aug 07 06:46:16 PM PDT 24
Finished Aug 07 06:47:21 PM PDT 24
Peak memory 256980 kb
Host smart-a27da188-092b-4e72-8ee2-1fa84377b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739224939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3739224939
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1589668242
Short name T675
Test name
Test status
Simulation time 3808065773 ps
CPU time 17.92 seconds
Started Aug 07 06:46:18 PM PDT 24
Finished Aug 07 06:46:36 PM PDT 24
Peak memory 233196 kb
Host smart-16f10e9d-0a2a-4fd7-a2b7-cd6061efbb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589668242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1589668242
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.222098359
Short name T678
Test name
Test status
Simulation time 3349659430 ps
CPU time 12.83 seconds
Started Aug 07 06:46:18 PM PDT 24
Finished Aug 07 06:46:31 PM PDT 24
Peak memory 240824 kb
Host smart-7a24cc48-d787-4ac0-8b9c-268ea33b83a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222098359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.222098359
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.53019773
Short name T900
Test name
Test status
Simulation time 19575127416 ps
CPU time 7.09 seconds
Started Aug 07 06:46:15 PM PDT 24
Finished Aug 07 06:46:23 PM PDT 24
Peak memory 224824 kb
Host smart-bf832f6a-da89-4256-babb-11138316b43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53019773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.53019773
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.58048936
Short name T620
Test name
Test status
Simulation time 107351091 ps
CPU time 2.52 seconds
Started Aug 07 06:46:16 PM PDT 24
Finished Aug 07 06:46:19 PM PDT 24
Peak memory 232848 kb
Host smart-3c3c6cb6-6929-42fe-869d-68198e2a5184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58048936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.58048936
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1783519378
Short name T493
Test name
Test status
Simulation time 111887915 ps
CPU time 4.2 seconds
Started Aug 07 06:46:16 PM PDT 24
Finished Aug 07 06:46:21 PM PDT 24
Peak memory 223540 kb
Host smart-474f508d-3936-4833-beab-6cdc4e54d5df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1783519378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1783519378
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2945614
Short name T892
Test name
Test status
Simulation time 3416009072 ps
CPU time 17.23 seconds
Started Aug 07 06:46:10 PM PDT 24
Finished Aug 07 06:46:27 PM PDT 24
Peak memory 217088 kb
Host smart-cc206736-e1de-4a1c-bb12-cb081a55e7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2945614
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4113337630
Short name T903
Test name
Test status
Simulation time 1850615522 ps
CPU time 4.3 seconds
Started Aug 07 06:46:09 PM PDT 24
Finished Aug 07 06:46:14 PM PDT 24
Peak memory 216704 kb
Host smart-d87235d2-2d27-4b19-83a8-2c7775136a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113337630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4113337630
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2011943490
Short name T496
Test name
Test status
Simulation time 1356849916 ps
CPU time 2.93 seconds
Started Aug 07 06:46:15 PM PDT 24
Finished Aug 07 06:46:18 PM PDT 24
Peak memory 216808 kb
Host smart-ef4b8efb-1d98-4b6d-a152-4abe81b0bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011943490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2011943490
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2065816598
Short name T934
Test name
Test status
Simulation time 86948722 ps
CPU time 0.78 seconds
Started Aug 07 06:46:08 PM PDT 24
Finished Aug 07 06:46:09 PM PDT 24
Peak memory 206340 kb
Host smart-89998f2d-8c7b-4a98-8e43-75f378ce0047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065816598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2065816598
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1078843348
Short name T190
Test name
Test status
Simulation time 3636128346 ps
CPU time 14.96 seconds
Started Aug 07 06:46:15 PM PDT 24
Finished Aug 07 06:46:30 PM PDT 24
Peak memory 249472 kb
Host smart-bea87790-743d-4f1e-bdf8-a3de149757cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078843348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1078843348
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.892221724
Short name T476
Test name
Test status
Simulation time 44463407 ps
CPU time 0.73 seconds
Started Aug 07 06:46:33 PM PDT 24
Finished Aug 07 06:46:34 PM PDT 24
Peak memory 205796 kb
Host smart-fe6b8d60-b9d3-4e88-9ac2-350fdc4f245c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892221724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.892221724
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.920756735
Short name T64
Test name
Test status
Simulation time 296840129 ps
CPU time 3.37 seconds
Started Aug 07 06:46:20 PM PDT 24
Finished Aug 07 06:46:24 PM PDT 24
Peak memory 233116 kb
Host smart-ed6ba107-05ef-457d-80bc-d0dbfa6da26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920756735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.920756735
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1381127767
Short name T116
Test name
Test status
Simulation time 20679827 ps
CPU time 0.8 seconds
Started Aug 07 06:46:22 PM PDT 24
Finished Aug 07 06:46:23 PM PDT 24
Peak memory 207248 kb
Host smart-a5bce21a-7656-4a55-9926-2c4859a59d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381127767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1381127767
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3037353981
Short name T735
Test name
Test status
Simulation time 15475357846 ps
CPU time 69.66 seconds
Started Aug 07 06:46:26 PM PDT 24
Finished Aug 07 06:47:36 PM PDT 24
Peak memory 255556 kb
Host smart-0ae30e8d-12d1-4c70-bbfa-e8bbda772c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037353981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3037353981
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2112266109
Short name T206
Test name
Test status
Simulation time 293708292538 ps
CPU time 595.27 seconds
Started Aug 07 06:46:31 PM PDT 24
Finished Aug 07 06:56:27 PM PDT 24
Peak memory 249652 kb
Host smart-c4b2543a-b63f-4319-8f55-1be3f162f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112266109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2112266109
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4057678756
Short name T766
Test name
Test status
Simulation time 5078028122 ps
CPU time 52 seconds
Started Aug 07 06:46:31 PM PDT 24
Finished Aug 07 06:47:23 PM PDT 24
Peak memory 257812 kb
Host smart-1541ad11-3d52-4ee1-b2a0-375fcbfce958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057678756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4057678756
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2517677410
Short name T906
Test name
Test status
Simulation time 5880894490 ps
CPU time 42.73 seconds
Started Aug 07 06:46:25 PM PDT 24
Finished Aug 07 06:47:08 PM PDT 24
Peak memory 237420 kb
Host smart-62f54907-f485-495d-ac14-c4ca2e6ee462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517677410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2517677410
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.132382825
Short name T880
Test name
Test status
Simulation time 71306259381 ps
CPU time 171.05 seconds
Started Aug 07 06:46:26 PM PDT 24
Finished Aug 07 06:49:17 PM PDT 24
Peak memory 257412 kb
Host smart-11559dfc-3989-4a41-9654-207e089f28bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132382825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
132382825
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3180874811
Short name T605
Test name
Test status
Simulation time 788180334 ps
CPU time 5.24 seconds
Started Aug 07 06:46:21 PM PDT 24
Finished Aug 07 06:46:26 PM PDT 24
Peak memory 224896 kb
Host smart-04a19409-7f89-45c8-8c84-8ab82b7f12e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180874811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3180874811
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3569223430
Short name T175
Test name
Test status
Simulation time 1639438792 ps
CPU time 8.56 seconds
Started Aug 07 06:46:23 PM PDT 24
Finished Aug 07 06:46:32 PM PDT 24
Peak memory 238196 kb
Host smart-82755d52-7932-4c85-9376-930d65893eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569223430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3569223430
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3231566071
Short name T982
Test name
Test status
Simulation time 14434495978 ps
CPU time 5.18 seconds
Started Aug 07 06:46:21 PM PDT 24
Finished Aug 07 06:46:27 PM PDT 24
Peak memory 224928 kb
Host smart-3e4a8ec3-3b54-432e-9493-f8501a2bb818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231566071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3231566071
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2323188372
Short name T932
Test name
Test status
Simulation time 46959049077 ps
CPU time 25.92 seconds
Started Aug 07 06:46:22 PM PDT 24
Finished Aug 07 06:46:48 PM PDT 24
Peak memory 249408 kb
Host smart-8bc62d94-2eb5-4e82-afd5-32d958818a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323188372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2323188372
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1968682820
Short name T453
Test name
Test status
Simulation time 3281016218 ps
CPU time 10.94 seconds
Started Aug 07 06:46:28 PM PDT 24
Finished Aug 07 06:46:39 PM PDT 24
Peak memory 222896 kb
Host smart-c45f4207-a02c-4dfb-885f-674b85ae0440
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1968682820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1968682820
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1072855647
Short name T804
Test name
Test status
Simulation time 16529144900 ps
CPU time 34.99 seconds
Started Aug 07 06:46:23 PM PDT 24
Finished Aug 07 06:46:58 PM PDT 24
Peak memory 216756 kb
Host smart-7c1f2a4c-760f-49f9-aa55-3ad73ccbaad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072855647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1072855647
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3058145896
Short name T836
Test name
Test status
Simulation time 22064914759 ps
CPU time 10.9 seconds
Started Aug 07 06:46:20 PM PDT 24
Finished Aug 07 06:46:31 PM PDT 24
Peak memory 216808 kb
Host smart-8ffc4b9e-38e3-4669-8c62-2e3e6736756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058145896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3058145896
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1996923391
Short name T507
Test name
Test status
Simulation time 610516004 ps
CPU time 1.36 seconds
Started Aug 07 06:46:22 PM PDT 24
Finished Aug 07 06:46:23 PM PDT 24
Peak memory 216700 kb
Host smart-cc10716c-fd2d-4160-8754-ed4c76bd087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996923391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1996923391
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2472406284
Short name T346
Test name
Test status
Simulation time 95129779 ps
CPU time 0.78 seconds
Started Aug 07 06:46:22 PM PDT 24
Finished Aug 07 06:46:23 PM PDT 24
Peak memory 206328 kb
Host smart-c2eddd9f-a5ae-492d-953d-50fc0c5ef5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472406284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2472406284
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3104260490
Short name T258
Test name
Test status
Simulation time 265503609 ps
CPU time 2.66 seconds
Started Aug 07 06:46:21 PM PDT 24
Finished Aug 07 06:46:24 PM PDT 24
Peak memory 224912 kb
Host smart-498af804-c458-4858-bcdb-a0fb8efb8390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104260490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3104260490
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1541467094
Short name T560
Test name
Test status
Simulation time 39886233 ps
CPU time 0.72 seconds
Started Aug 07 06:46:37 PM PDT 24
Finished Aug 07 06:46:38 PM PDT 24
Peak memory 205836 kb
Host smart-ca2d3778-2765-4170-8457-25c0e2aecbad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541467094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
541467094
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2995328915
Short name T413
Test name
Test status
Simulation time 475650150 ps
CPU time 5.74 seconds
Started Aug 07 06:46:37 PM PDT 24
Finished Aug 07 06:46:43 PM PDT 24
Peak memory 233084 kb
Host smart-65baa212-46e1-4183-bc38-2a636a971019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995328915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2995328915
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4237311214
Short name T623
Test name
Test status
Simulation time 18542105 ps
CPU time 0.8 seconds
Started Aug 07 06:46:34 PM PDT 24
Finished Aug 07 06:46:35 PM PDT 24
Peak memory 207192 kb
Host smart-f405a696-4513-4117-a303-bb3167acebcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237311214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4237311214
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1800073714
Short name T479
Test name
Test status
Simulation time 59825028872 ps
CPU time 31.04 seconds
Started Aug 07 06:46:39 PM PDT 24
Finished Aug 07 06:47:10 PM PDT 24
Peak memory 218120 kb
Host smart-83041b0f-42ca-41c8-9de7-dfb33a40a9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800073714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1800073714
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.234611903
Short name T231
Test name
Test status
Simulation time 21607775465 ps
CPU time 98.08 seconds
Started Aug 07 06:46:37 PM PDT 24
Finished Aug 07 06:48:15 PM PDT 24
Peak memory 254696 kb
Host smart-eb086cd0-33b9-4de6-9b52-d1bb07b11f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234611903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
234611903
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1563987602
Short name T1008
Test name
Test status
Simulation time 370087654 ps
CPU time 7.26 seconds
Started Aug 07 06:46:40 PM PDT 24
Finished Aug 07 06:46:47 PM PDT 24
Peak memory 225172 kb
Host smart-7fb6ca47-2f39-4066-844f-ead188b9e637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563987602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1563987602
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2721196398
Short name T216
Test name
Test status
Simulation time 56447273471 ps
CPU time 378.89 seconds
Started Aug 07 06:46:41 PM PDT 24
Finished Aug 07 06:53:00 PM PDT 24
Peak memory 253408 kb
Host smart-ed85755c-ffe1-4f92-9805-6caca4994c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721196398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2721196398
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1564225554
Short name T48
Test name
Test status
Simulation time 2811880905 ps
CPU time 23.95 seconds
Started Aug 07 06:46:30 PM PDT 24
Finished Aug 07 06:46:54 PM PDT 24
Peak memory 224916 kb
Host smart-95552978-5770-4503-821d-894d782182f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564225554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1564225554
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.406023169
Short name T855
Test name
Test status
Simulation time 235652102 ps
CPU time 5.6 seconds
Started Aug 07 06:46:31 PM PDT 24
Finished Aug 07 06:46:37 PM PDT 24
Peak memory 224920 kb
Host smart-b24323df-2ebd-4c96-a74c-ba7ac65888e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406023169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.406023169
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2194503843
Short name T715
Test name
Test status
Simulation time 6049504363 ps
CPU time 7.45 seconds
Started Aug 07 06:46:33 PM PDT 24
Finished Aug 07 06:46:41 PM PDT 24
Peak memory 233160 kb
Host smart-5cfb6c6d-6b3b-40ea-912b-196f17b6dc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194503843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2194503843
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1445115198
Short name T194
Test name
Test status
Simulation time 43912245 ps
CPU time 2.16 seconds
Started Aug 07 06:46:32 PM PDT 24
Finished Aug 07 06:46:34 PM PDT 24
Peak memory 224848 kb
Host smart-923a54eb-5dd7-4f15-b390-b442d37de7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445115198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1445115198
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2315316140
Short name T132
Test name
Test status
Simulation time 102760831 ps
CPU time 3.35 seconds
Started Aug 07 06:46:37 PM PDT 24
Finished Aug 07 06:46:41 PM PDT 24
Peak memory 219308 kb
Host smart-6967696d-8b06-4d3a-b5ae-3d97fb3e5261
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2315316140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2315316140
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2138676012
Short name T859
Test name
Test status
Simulation time 10037458855 ps
CPU time 44.52 seconds
Started Aug 07 06:46:39 PM PDT 24
Finished Aug 07 06:47:24 PM PDT 24
Peak memory 224916 kb
Host smart-ccd9cc46-4aa3-43fa-b687-34183734994d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138676012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2138676012
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1605469640
Short name T782
Test name
Test status
Simulation time 3470381038 ps
CPU time 14.86 seconds
Started Aug 07 06:46:31 PM PDT 24
Finished Aug 07 06:46:46 PM PDT 24
Peak memory 216936 kb
Host smart-18957743-d6d6-4d4e-a2f1-c71eb2aaee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605469640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1605469640
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1268895925
Short name T462
Test name
Test status
Simulation time 2666534917 ps
CPU time 11.2 seconds
Started Aug 07 06:46:31 PM PDT 24
Finished Aug 07 06:46:42 PM PDT 24
Peak memory 216648 kb
Host smart-d0254364-27cd-40a4-9e57-62f614ccec06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268895925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1268895925
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2830396506
Short name T391
Test name
Test status
Simulation time 922586012 ps
CPU time 1.06 seconds
Started Aug 07 06:46:34 PM PDT 24
Finished Aug 07 06:46:35 PM PDT 24
Peak memory 207260 kb
Host smart-ab39d1d3-910c-4396-b680-7c245edfe1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830396506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2830396506
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.564362176
Short name T987
Test name
Test status
Simulation time 113474575 ps
CPU time 0.85 seconds
Started Aug 07 06:46:33 PM PDT 24
Finished Aug 07 06:46:34 PM PDT 24
Peak memory 206324 kb
Host smart-fc73adbc-6096-4c7b-8b78-0c1806e95674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564362176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.564362176
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3855636253
Short name T473
Test name
Test status
Simulation time 2887794315 ps
CPU time 11.59 seconds
Started Aug 07 06:46:37 PM PDT 24
Finished Aug 07 06:46:48 PM PDT 24
Peak memory 224912 kb
Host smart-344b4be7-f7c5-42f2-8b14-9608f023b490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855636253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3855636253
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.187255337
Short name T324
Test name
Test status
Simulation time 48418473 ps
CPU time 0.72 seconds
Started Aug 07 06:46:47 PM PDT 24
Finished Aug 07 06:46:47 PM PDT 24
Peak memory 205280 kb
Host smart-fae4bab2-3a60-411b-b12a-e48426e33d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187255337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.187255337
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2819612960
Short name T374
Test name
Test status
Simulation time 897907175 ps
CPU time 7.21 seconds
Started Aug 07 06:46:47 PM PDT 24
Finished Aug 07 06:46:54 PM PDT 24
Peak memory 224856 kb
Host smart-0b11a43c-e49c-4f14-8870-8d269dca4d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819612960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2819612960
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3580770983
Short name T849
Test name
Test status
Simulation time 13385657 ps
CPU time 0.76 seconds
Started Aug 07 06:46:38 PM PDT 24
Finished Aug 07 06:46:38 PM PDT 24
Peak memory 206936 kb
Host smart-fa7ccc26-1188-4e1d-bfa9-346757789b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580770983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3580770983
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3012233614
Short name T506
Test name
Test status
Simulation time 3682611928 ps
CPU time 59.94 seconds
Started Aug 07 06:46:46 PM PDT 24
Finished Aug 07 06:47:46 PM PDT 24
Peak memory 249968 kb
Host smart-a4169949-543c-4d08-8a97-984949e9183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012233614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3012233614
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3530853123
Short name T249
Test name
Test status
Simulation time 58151035975 ps
CPU time 134.96 seconds
Started Aug 07 06:46:47 PM PDT 24
Finished Aug 07 06:49:02 PM PDT 24
Peak memory 251740 kb
Host smart-ebc9fc20-8b65-4f63-9090-522a690bd8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530853123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3530853123
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3784810745
Short name T926
Test name
Test status
Simulation time 21982526971 ps
CPU time 34.24 seconds
Started Aug 07 06:46:46 PM PDT 24
Finished Aug 07 06:47:20 PM PDT 24
Peak memory 233144 kb
Host smart-540f11e7-927b-41e2-a27d-1fe0d356951b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784810745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3784810745
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1437941921
Short name T1000
Test name
Test status
Simulation time 11633795332 ps
CPU time 111.25 seconds
Started Aug 07 06:46:46 PM PDT 24
Finished Aug 07 06:48:38 PM PDT 24
Peak memory 253640 kb
Host smart-8168ecfa-a071-437c-ac81-606fb61d5dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437941921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1437941921
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3072543281
Short name T180
Test name
Test status
Simulation time 37089765 ps
CPU time 2.77 seconds
Started Aug 07 06:46:41 PM PDT 24
Finished Aug 07 06:46:44 PM PDT 24
Peak memory 228288 kb
Host smart-a0537387-501a-49a4-bd04-70f668f0a8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072543281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3072543281
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1842746408
Short name T471
Test name
Test status
Simulation time 695858289 ps
CPU time 11.89 seconds
Started Aug 07 06:46:41 PM PDT 24
Finished Aug 07 06:46:53 PM PDT 24
Peak memory 227768 kb
Host smart-ef65f416-83dd-40a2-945f-9162e981f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842746408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1842746408
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3163063554
Short name T208
Test name
Test status
Simulation time 9963521651 ps
CPU time 11.22 seconds
Started Aug 07 06:46:41 PM PDT 24
Finished Aug 07 06:46:52 PM PDT 24
Peak memory 233224 kb
Host smart-503b37ab-3de1-4b8b-bc95-a5408cbc2889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163063554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3163063554
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2153276930
Short name T472
Test name
Test status
Simulation time 954242717 ps
CPU time 4.74 seconds
Started Aug 07 06:46:42 PM PDT 24
Finished Aug 07 06:46:47 PM PDT 24
Peak memory 233084 kb
Host smart-525cff8b-9f83-40a2-b8c9-637401d0ae5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153276930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2153276930
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3256417
Short name T676
Test name
Test status
Simulation time 618305967 ps
CPU time 5.63 seconds
Started Aug 07 06:46:46 PM PDT 24
Finished Aug 07 06:46:52 PM PDT 24
Peak memory 219764 kb
Host smart-8bf734dd-88b5-4773-8468-afeb9268922e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3256417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.3256417
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1499833355
Short name T697
Test name
Test status
Simulation time 370085395 ps
CPU time 3.78 seconds
Started Aug 07 06:46:42 PM PDT 24
Finished Aug 07 06:46:46 PM PDT 24
Peak memory 219900 kb
Host smart-067a9a32-eb24-4048-bd7a-8107da030b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499833355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1499833355
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.385271890
Short name T308
Test name
Test status
Simulation time 434851567 ps
CPU time 2.44 seconds
Started Aug 07 06:46:41 PM PDT 24
Finished Aug 07 06:46:44 PM PDT 24
Peak memory 216660 kb
Host smart-3edcdced-40a3-4925-9df0-9b7a6e612942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385271890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.385271890
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4030739718
Short name T905
Test name
Test status
Simulation time 39731047 ps
CPU time 2.32 seconds
Started Aug 07 06:46:41 PM PDT 24
Finished Aug 07 06:46:44 PM PDT 24
Peak memory 216604 kb
Host smart-f6f0623c-7f46-4865-af53-16f4992b59f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030739718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4030739718
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1337883796
Short name T543
Test name
Test status
Simulation time 46605571 ps
CPU time 0.71 seconds
Started Aug 07 06:46:41 PM PDT 24
Finished Aug 07 06:46:42 PM PDT 24
Peak memory 206400 kb
Host smart-5e47e969-a876-42ae-ac23-06a97d72d7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337883796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1337883796
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.327916882
Short name T632
Test name
Test status
Simulation time 23749284411 ps
CPU time 19.36 seconds
Started Aug 07 06:46:47 PM PDT 24
Finished Aug 07 06:47:06 PM PDT 24
Peak memory 233176 kb
Host smart-4d234591-a00c-4389-a0c0-6ec6c85db945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327916882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.327916882
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3058293608
Short name T616
Test name
Test status
Simulation time 15388795 ps
CPU time 0.77 seconds
Started Aug 07 06:46:58 PM PDT 24
Finished Aug 07 06:46:59 PM PDT 24
Peak memory 205244 kb
Host smart-ce3a2abc-bbf6-403a-9668-aa2e5d8bc1d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058293608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
058293608
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2644630701
Short name T915
Test name
Test status
Simulation time 323472106 ps
CPU time 2.11 seconds
Started Aug 07 06:46:53 PM PDT 24
Finished Aug 07 06:46:55 PM PDT 24
Peak memory 224588 kb
Host smart-00c4cc0f-c7ca-4d84-a237-f0fb3c93d3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644630701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2644630701
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2146189926
Short name T510
Test name
Test status
Simulation time 70810642 ps
CPU time 0.75 seconds
Started Aug 07 06:46:50 PM PDT 24
Finished Aug 07 06:46:51 PM PDT 24
Peak memory 206964 kb
Host smart-bbde4f30-4d3c-41ed-ac62-36f75060b80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146189926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2146189926
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.436782942
Short name T227
Test name
Test status
Simulation time 151768597624 ps
CPU time 239.65 seconds
Started Aug 07 06:46:52 PM PDT 24
Finished Aug 07 06:50:52 PM PDT 24
Peak memory 249572 kb
Host smart-50a7b5a3-9029-4b24-b558-ae2883812a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436782942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.436782942
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2114071472
Short name T624
Test name
Test status
Simulation time 17699986204 ps
CPU time 76.12 seconds
Started Aug 07 06:46:59 PM PDT 24
Finished Aug 07 06:48:15 PM PDT 24
Peak memory 251312 kb
Host smart-2f64ada0-7e0d-49a5-a9bf-e09a875882c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114071472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2114071472
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3008570894
Short name T604
Test name
Test status
Simulation time 9906429972 ps
CPU time 65.26 seconds
Started Aug 07 06:46:58 PM PDT 24
Finished Aug 07 06:48:03 PM PDT 24
Peak memory 241456 kb
Host smart-53538ec6-fa11-4999-9ae6-b34e6b9c716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008570894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3008570894
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3293832419
Short name T464
Test name
Test status
Simulation time 107846419 ps
CPU time 4.97 seconds
Started Aug 07 06:46:51 PM PDT 24
Finished Aug 07 06:46:57 PM PDT 24
Peak memory 233196 kb
Host smart-3e7a1c73-38a0-4f6a-8201-c0fbaa22ee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293832419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3293832419
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2924291380
Short name T910
Test name
Test status
Simulation time 9597505115 ps
CPU time 98.96 seconds
Started Aug 07 06:46:52 PM PDT 24
Finished Aug 07 06:48:31 PM PDT 24
Peak memory 252608 kb
Host smart-942b34bb-210c-4bf8-ac95-605ae5b8658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924291380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2924291380
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2626507857
Short name T989
Test name
Test status
Simulation time 6946494469 ps
CPU time 33.43 seconds
Started Aug 07 06:46:51 PM PDT 24
Finished Aug 07 06:47:25 PM PDT 24
Peak memory 233224 kb
Host smart-bd3ce6da-52d9-4fc2-8682-4862e5c99e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626507857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2626507857
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2500525641
Short name T993
Test name
Test status
Simulation time 110943607 ps
CPU time 2.04 seconds
Started Aug 07 06:46:54 PM PDT 24
Finished Aug 07 06:46:56 PM PDT 24
Peak memory 223588 kb
Host smart-ee6a1d8c-0140-4d1c-ad76-d809be929feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500525641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2500525641
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4131574845
Short name T950
Test name
Test status
Simulation time 77858864 ps
CPU time 2.9 seconds
Started Aug 07 06:46:51 PM PDT 24
Finished Aug 07 06:46:54 PM PDT 24
Peak memory 233060 kb
Host smart-c7aea80d-d37b-4a37-ab43-a548783c3e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131574845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4131574845
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3172976278
Short name T550
Test name
Test status
Simulation time 6229447862 ps
CPU time 9.02 seconds
Started Aug 07 06:46:51 PM PDT 24
Finished Aug 07 06:47:00 PM PDT 24
Peak memory 233136 kb
Host smart-66c0bc40-4f86-49e3-9974-0c3a960cd26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172976278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3172976278
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2942199746
Short name T842
Test name
Test status
Simulation time 100740409 ps
CPU time 4.35 seconds
Started Aug 07 06:46:54 PM PDT 24
Finished Aug 07 06:46:59 PM PDT 24
Peak memory 223512 kb
Host smart-ffe72ddf-1fb7-4ca7-942d-b1a8dcf9a8a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2942199746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2942199746
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3081479020
Short name T12
Test name
Test status
Simulation time 53259607 ps
CPU time 1.22 seconds
Started Aug 07 06:46:59 PM PDT 24
Finished Aug 07 06:47:00 PM PDT 24
Peak memory 207540 kb
Host smart-6added18-74c2-4b40-a705-0efa51ea4dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081479020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3081479020
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3434723325
Short name T475
Test name
Test status
Simulation time 857721729 ps
CPU time 7.66 seconds
Started Aug 07 06:46:49 PM PDT 24
Finished Aug 07 06:46:57 PM PDT 24
Peak memory 217016 kb
Host smart-a6fdc308-bdff-4234-ac44-855dc72e73ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434723325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3434723325
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2470132220
Short name T545
Test name
Test status
Simulation time 2807501619 ps
CPU time 5.3 seconds
Started Aug 07 06:46:47 PM PDT 24
Finished Aug 07 06:46:53 PM PDT 24
Peak memory 216712 kb
Host smart-3ee0c856-dd33-45b0-8d65-ef862baa46ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470132220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2470132220
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1161559773
Short name T385
Test name
Test status
Simulation time 56202702 ps
CPU time 1.18 seconds
Started Aug 07 06:46:47 PM PDT 24
Finished Aug 07 06:46:49 PM PDT 24
Peak memory 207616 kb
Host smart-7e8a2bc4-0045-4e98-91fb-8a6181d79b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161559773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1161559773
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3160883322
Short name T481
Test name
Test status
Simulation time 10838536 ps
CPU time 0.68 seconds
Started Aug 07 06:46:47 PM PDT 24
Finished Aug 07 06:46:48 PM PDT 24
Peak memory 205972 kb
Host smart-0ce29f40-b74c-4e5c-b6cf-66bb43f06f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160883322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3160883322
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2564877553
Short name T657
Test name
Test status
Simulation time 65389575 ps
CPU time 2.29 seconds
Started Aug 07 06:46:54 PM PDT 24
Finished Aug 07 06:46:56 PM PDT 24
Peak memory 224560 kb
Host smart-5203ecec-1a8f-455d-bd49-ab3bc2e613e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564877553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2564877553
Directory /workspace/9.spi_device_upload/latest
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