Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2796537	1			T1	100483		T2	57498		T3	1
all_values[1]	2796537	1			T1	100483		T2	57498		T3	1
all_values[2]	2796537	1			T1	100483		T2	57498		T3	1
all_values[3]	2796537	1			T1	100483		T2	57498		T3	1
all_values[4]	2796537	1			T1	100483		T2	57498		T3	1
all_values[5]	2796537	1			T1	100483		T2	57498		T3	1
all_values[6]	2796537	1			T1	100483		T2	57498		T3	1
all_values[7]	2796537	1			T1	100483		T2	57498		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21492445

1

T1

803829

T2

459984

T3

8

auto[1]

879851

1

T1

35

T4

94

T9

130

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22345624

1

T1

803354

T2

459984

T3

8

auto[1]

26672

1

T1

510

T4

89

T9

358

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2679399	1			T1	100265		T2	57498		T3	1
all_values[0]	auto[0]	auto[1]	12457	1			T1	211		T4	14		T9	114
all_values[0]	auto[1]	auto[0]	104079	1			T1	5		T4	11		T9	16
all_values[0]	auto[1]	auto[1]	602	1			T1	2		T4	3		T9	6
all_values[1]	auto[0]	auto[0]	2665610	1			T1	100323		T2	57498		T3	1
all_values[1]	auto[0]	auto[1]	8281	1			T1	157		T4	14		T9	101
all_values[1]	auto[1]	auto[0]	122264	1			T1	2		T4	5		T9	3
all_values[1]	auto[1]	auto[1]	382	1			T1	1		T4	5		T9	7
all_values[2]	auto[0]	auto[0]	2682461	1			T1	100362		T2	57498		T3	1
all_values[2]	auto[0]	auto[1]	2762	1			T1	119		T4	6		T9	42
all_values[2]	auto[1]	auto[0]	111056	1			T4	6		T9	8		T17	1
all_values[2]	auto[1]	auto[1]	258	1			T1	2		T4	4		T9	10
all_values[3]	auto[0]	auto[0]	2774873	1			T1	100476		T2	57498		T3	1
all_values[3]	auto[0]	auto[1]	208	1			T1	2		T4	3		T9	11
all_values[3]	auto[1]	auto[0]	21286	1			T1	3		T4	10		T9	9
all_values[3]	auto[1]	auto[1]	170	1			T1	2		T4	5		T9	7
all_values[4]	auto[0]	auto[0]	2657146	1			T1	100478		T2	57498		T3	1
all_values[4]	auto[0]	auto[1]	190	1			T1	3		T4	3		T9	8
all_values[4]	auto[1]	auto[0]	139016	1			T4	8		T9	9		T17	1
all_values[4]	auto[1]	auto[1]	185	1			T1	2		T4	6		T9	8
all_values[5]	auto[0]	auto[0]	2640231	1			T1	100475		T2	57498		T3	1
all_values[5]	auto[0]	auto[1]	187	1			T1	1		T4	4		T9	3
all_values[5]	auto[1]	auto[0]	155935	1			T1	6		T4	5		T9	8
all_values[5]	auto[1]	auto[1]	184	1			T1	1		T4	5		T9	11
all_values[6]	auto[0]	auto[0]	2715590	1			T1	100476		T2	57498		T3	1
all_values[6]	auto[0]	auto[1]	219	1			T1	5		T4	4		T9	3
all_values[6]	auto[1]	auto[0]	80538	1			T1	1		T4	3		T9	9
all_values[6]	auto[1]	auto[1]	190	1			T1	1		T4	6		T9	6
all_values[7]	auto[0]	auto[0]	2652628	1			T1	100476		T2	57498		T3	1
all_values[7]	auto[0]	auto[1]	203	1			T4	1		T9	14		T17	3
all_values[7]	auto[1]	auto[0]	143512	1			T1	6		T4	6		T9	6
all_values[7]	auto[1]	auto[1]	194	1			T1	1		T4	6		T9	7