Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	38236	1			T1	156		T2	86		T3	2
auto[SpiFlashAddrCfg]	7952	1			T1	60		T2	25		T3	4
auto[SpiFlashAddr3b]	9602	1			T1	74		T2	31		T3	6
auto[SpiFlashAddr4b]	8024	1			T1	68		T2	37		T3	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35950

1

T1

201

T2

109

T3

14

auto[1]

27864

1

T1

157

T2

70

T4

37

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33808

1

T1

201

T2

124

T3

8

auto[1]

30006

1

T1

157

T2

55

T3

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	43139	1			T1	189		T2	100		T3	4
values[1]	1161	1			T1	7		T2	2		T4	2
values[2]	1586	1			T1	19		T2	10		T4	2
values[3]	1539	1			T1	11		T2	3		T4	4
values[4]	1530	1			T1	12		T2	8		T3	4
values[5]	1513	1			T1	21		T2	4		T4	3
values[6]	1604	1			T1	11		T2	9		T4	6
values[7]	1568	1			T1	13		T2	3		T4	1
values[8]	10174	1			T1	75		T2	40		T3	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31311

1

T1

338

T2

179

T3

14

auto[1]

32503

1

T1

20

T9

567

T14

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

60324

1

T1

328

T2

172

T3

12

write

3490

1

T1

30

T2

7

T3

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20237

1

T1

159

T2

80

T3

10

valids[0x1]

43577

1

T1

199

T2

99

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1639	1			T1	8		T2	7		T4	3
internal_process_ops[0x5a]	1665	1			T1	8		T2	3		T4	4
internal_process_ops[0x05]	23641	1			T1	44		T2	24		T4	8
internal_process_ops[0x35]	1623	1			T1	11		T2	6		T4	1
internal_process_ops[0x15]	1696	1			T1	11		T2	5		T4	3
internal_process_ops[0x03]	1047	1			T1	13		T2	8		T3	2
internal_process_ops[0x0b]	1023	1			T1	12		T2	3		T4	3
internal_process_ops[0x3b]	1119	1			T1	12		T2	7		T9	6
internal_process_ops[0x6b]	1055	1			T1	8		T2	5		T3	2
internal_process_ops[0xbb]	1136	1			T1	13		T2	5		T4	2
internal_process_ops[0xeb]	1153	1			T1	9		T2	2		T4	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62051

1

T1

343

T2

176

T3

14

auto[1]

1763

1

T1

15

T2

3

T4

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61364

1

T1

342

T2

176

T3

14

auto[1]

2450

1

T1

16

T2

3

T4

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10256

1

T1

85

T2

54

T4

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7003

1

T1

60

T2

30

T4

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2036

1

T1

25

T2

16

T3

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1813

1

T1

21

T2

9

T4

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2483

1

T1

28

T2

20

T3

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2181

1

T1

34

T2

8

T4

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2102

1

T1

33

T2

18

T3

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1857

1

T1

25

T2

17

T4

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

129

1

T1

3

T3

2

T29

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

100

1

T15

1

T17

1

T18

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T2

1

T15

3

T34

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

101

1

T1

3

T2

1

T15

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

106

1

T1

4

T29

2

T18

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

82

1

T4

2

T15

5

T17

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

104

1

T1

1

T15

1

T29

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

131

1

T1

5

T15

8

T28

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

96

1

T1

2

T2

1

T4

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

69

1

T1

2

T17

1

T148

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

94

1

T17

6

T18

1

T34

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

90

1

T1

1

T2

2

T15

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T1

1

T15

3

T34

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T1

2

T15

1

T17

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T1

1

T2

2

T28

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

102

1

T1

2

T4

1

T15

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11991

1

T1

4

T9

241

T16

5

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8137

1

T1

1

T9

151

T16

26

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1617

1

T1

4

T9

22

T14

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1539

1

T9

19

T16

1

T36

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2013

1

T1

1

T9

21

T14

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2066

1

T1

3

T9

44

T16

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1673

1

T1

4

T9

28

T14

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1557

1

T9

16

T36

2

T68

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T9

2

T68

3

T47

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

116

1

T16

2

T36

1

T68

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

110

1

T9

4

T36

1

T68

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T9

2

T36

2

T78

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

117

1

T9

2

T68

2

T47

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

153

1

T9

1

T36

1

T47

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

124

1

T9

2

T149

1

T150

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

130

1

T9

2

T36

1

T68

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

116

1

T1

3

T9

1

T68

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

132

1

T9

2

T16

1

T68

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

123

1

T18

1

T47

4

T149

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

139

1

T68

2

T18

4

T47

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T36

1

T68

2

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

138

1

T9

2

T16

2

T68

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T9

3

T68

2

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T9

2

T36

1

T47

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3816	1			T1	59		T2	35		T4	7
auto[0]	values[0]	valids[0x1]	16257	1			T1	118		T2	65		T3	4
auto[0]	values[1]	valids[0x1]	562	1			T1	5		T2	2		T4	2
auto[0]	values[2]	valids[0x0]	618	1			T1	7		T2	5		T4	1
auto[0]	values[2]	valids[0x1]	280	1			T1	12		T2	5		T4	1
auto[0]	values[3]	valids[0x0]	528	1			T1	3		T2	3		T4	1
auto[0]	values[3]	valids[0x1]	347	1			T1	7		T4	3		T15	4
auto[0]	values[4]	valids[0x0]	567	1			T1	9		T2	4		T3	4
auto[0]	values[4]	valids[0x1]	286	1			T1	3		T2	4		T15	6
auto[0]	values[5]	valids[0x0]	528	1			T1	11		T2	2		T4	3
auto[0]	values[5]	valids[0x1]	270	1			T1	9		T2	2		T15	8
auto[0]	values[6]	valids[0x0]	532	1			T1	9		T2	4		T4	2
auto[0]	values[6]	valids[0x1]	299	1			T1	2		T2	5		T4	4
auto[0]	values[7]	valids[0x0]	579	1			T1	8		T2	1		T4	1
auto[0]	values[7]	valids[0x1]	320	1			T1	3		T2	2		T15	5
auto[0]	values[8]	valids[0x0]	3512	1			T1	46		T2	26		T3	6
auto[0]	values[8]	valids[0x1]	2010	1			T1	27		T2	14		T4	9
auto[1]	values[0]	valids[0x0]	4305	1			T1	6		T9	64		T16	4
auto[1]	values[0]	valids[0x1]	18761	1			T1	6		T9	361		T16	31
auto[1]	values[1]	valids[0x1]	599	1			T1	2		T9	6		T36	2
auto[1]	values[2]	valids[0x0]	417	1			T9	6		T68	3		T18	6
auto[1]	values[2]	valids[0x1]	271	1			T9	11		T36	1		T68	3
auto[1]	values[3]	valids[0x0]	415	1			T1	1		T9	4		T36	2
auto[1]	values[3]	valids[0x1]	249	1			T9	3		T68	5		T18	1
auto[1]	values[4]	valids[0x0]	398	1			T9	5		T31	1		T68	2
auto[1]	values[4]	valids[0x1]	279	1			T9	8		T16	1		T68	1
auto[1]	values[5]	valids[0x0]	413	1			T9	8		T14	3		T36	3
auto[1]	values[5]	valids[0x1]	302	1			T1	1		T9	12		T68	1
auto[1]	values[6]	valids[0x0]	467	1			T9	4		T36	2		T68	4
auto[1]	values[6]	valids[0x1]	306	1			T9	3		T36	2		T68	6
auto[1]	values[7]	valids[0x0]	389	1			T9	9		T68	2		T18	3
auto[1]	values[7]	valids[0x1]	280	1			T1	2		T9	7		T68	2
auto[1]	values[8]	valids[0x0]	2753	1			T9	32		T14	5		T31	3
auto[1]	values[8]	valids[0x1]	1899	1			T1	2		T9	24		T16	1