Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3527278

1

T1

12447

T2

18267

T3

1

auto[1]

29922

1

T1

38

T2

19

T4

7

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

954200

1

T1

76

T2

43

T3

1

auto[1]

2603000

1

T1

12409

T2

18243

T4

2497

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	671709	1			T1	281		T2	1907		T3	1
auto[524288:1048575]	428685	1			T1	2921		T2	541		T4	133
auto[1048576:1572863]	427029	1			T1	3104		T2	9		T9	10
auto[1572864:2097151]	415165	1			T1	137		T2	5802		T9	1032
auto[2097152:2621439]	363368	1			T1	777		T2	4060		T4	17
auto[2621440:3145727]	400718	1			T1	3799		T2	2673		T9	3019
auto[3145728:3670015]	414700	1			T1	19		T2	519		T9	97
auto[3670016:4194303]	435826	1			T1	1447		T2	2775		T6	3

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2636792

1

T1

12483

T2

18283

T3

1

auto[1]

920408

1

T1

2

T2

3

T6

9714

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3073950

1

T1

11822

T2

13693

T3

1

auto[1]

483250

1

T1

663

T2

4593

T4

2

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	223910	1			T1	3		T2	5		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	368627	1			T1	261		T2	4		T4	2359
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	108281	1			T1	5		T2	3		T4	5
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	272485	1			T1	2912		T2	257		T4	128
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	113823	1			T1	3		T2	1		T9	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	241676	1			T1	2584		T2	6		T9	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	83479	1			T1	6		T2	4		T9	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	266449	1			T1	1		T2	5798		T9	1025
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	79102	1			T1	2		T2	2		T4	7
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	231562	1			T1	773		T2	4054		T4	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	90425	1			T1	5		T2	3		T9	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	260391	1			T1	3783		T2	256		T9	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	103739	1			T1	4		T2	5		T9	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	237262	1			T1	4		T2	512		T9	92
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	134527	1			T1	15		T2	1		T6	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	233303	1			T1	1423		T2	2774		T9	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	841	1			T1	2		T2	1		T15	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	73698	1			T1	4		T2	1896		T15	513
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1473	1			T1	1		T2	6		T9	8
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	42289	1			T2	257		T9	2431		T15	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3310	1			T1	3		T2	2		T15	11
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	63853	1			T1	512		T15	648		T68	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2284	1			T9	2		T15	4		T28	13
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	59619	1			T1	130		T15	4439		T18	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2508	1			T1	2		T2	4		T4	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	47223	1			T9	752		T17	640		T68	770
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	807	1			T1	3		T2	1		T9	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	45499	1			T2	2413		T9	2998		T29	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1072	1			T1	5		T2	2		T15	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	68992	1			T15	2007		T36	128		T18	2121
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	742	1			T1	1		T9	11		T13	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	64027	1			T9	580		T29	1		T36	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	474	1			T1	5		T2	1		T4	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3483	1			T1	6		T4	4		T9	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	387	1			T1	2		T2	1		T9	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2974	1			T1	1		T2	6		T9	39
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	408	1			T1	1		T15	2		T36	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3210	1			T1	1		T15	34		T36	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	350	1			T28	3		T29	4		T17	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2406	1			T29	110		T17	27		T68	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	382	1			T4	2		T9	3		T15	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2252	1			T9	10		T15	17		T16	10
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	364	1			T1	1		T9	1		T29	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2575	1			T1	7		T9	9		T29	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	386	1			T1	1		T15	7		T29	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2534	1			T1	5		T15	129		T29	11
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	416	1			T1	6		T9	2		T15	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2308	1			T1	2		T9	61		T15	14
auto[1]	auto[1]	auto[0:524287]	auto[0]	96	1			T15	1		T36	1		T148	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	580	1			T15	4		T36	17		T148	8
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	84	1			T2	1		T9	2		T15	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	712	1			T2	10		T9	101		T15	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	81	1			T15	3		T68	1		T47	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	668	1			T15	14		T68	3		T47	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	121	1			T15	1		T18	1		T47	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	457	1			T15	6		T18	11		T47	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	104	1			T9	5		T78	23		T253	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	235	1			T9	21		T253	27		T20	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	89	1			T9	1		T29	1		T36	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	568	1			T9	6		T29	30		T36	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	70	1			T19	1		T268	2		T245	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	645	1			T19	3		T268	48		T275	67
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	65	1			T9	4		T29	1		T68	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	438	1			T9	15		T29	62		T68	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2137176	1			T1	11784		T2	13684		T3	1
auto[0]	auto[0]	auto[1]	911865	1			T2	1		T6	9714		T9	3
auto[0]	auto[1]	auto[0]	470295	1			T1	663		T2	4582		T4	2
auto[0]	auto[1]	auto[1]	7942	1			T9	4		T13	2		T29	1
auto[1]	auto[0]	auto[0]	24401	1			T1	36		T2	7		T4	7
auto[1]	auto[0]	auto[1]	508	1			T1	2		T2	1		T9	1
auto[1]	auto[1]	auto[0]	4920	1			T2	10		T9	154		T15	35
auto[1]	auto[1]	auto[1]	93	1			T2	1		T9	1		T36	2