Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2796537	1			T1	100483		T2	57498		T3	1
all_pins[1]	2796537	1			T1	100483		T2	57498		T3	1
all_pins[2]	2796537	1			T1	100483		T2	57498		T3	1
all_pins[3]	2796537	1			T1	100483		T2	57498		T3	1
all_pins[4]	2796537	1			T1	100483		T2	57498		T3	1
all_pins[5]	2796537	1			T1	100483		T2	57498		T3	1
all_pins[6]	2796537	1			T1	100483		T2	57498		T3	1
all_pins[7]	2796537	1			T1	100483		T2	57498		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22287925	1			T1	803852		T2	459984		T3	8
values[0x1]	84371	1			T1	12		T4	40		T9	62
transitions[0x0=>0x1]	82988	1			T1	12		T4	29		T9	51
transitions[0x1=>0x0]	82999	1			T1	12		T4	29		T9	51

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2795884	1			T1	100481		T2	57498		T3	1
all_pins[0]	values[0x1]	653	1			T1	2		T4	3		T9	6
all_pins[0]	transitions[0x0=>0x1]	553	1			T1	2		T4	1		T9	6
all_pins[0]	transitions[0x1=>0x0]	304	1			T1	1		T4	3		T9	7
all_pins[1]	values[0x0]	2796133	1			T1	100482		T2	57498		T3	1
all_pins[1]	values[0x1]	404	1			T1	1		T4	5		T9	7
all_pins[1]	transitions[0x0=>0x1]	308	1			T1	1		T4	3		T9	2
all_pins[1]	transitions[0x1=>0x0]	165	1			T1	2		T4	2		T9	5
all_pins[2]	values[0x0]	2796276	1			T1	100481		T2	57498		T3	1
all_pins[2]	values[0x1]	261	1			T1	2		T4	4		T9	10
all_pins[2]	transitions[0x0=>0x1]	220	1			T1	2		T4	4		T9	9
all_pins[2]	transitions[0x1=>0x0]	129	1			T1	2		T4	5		T9	6
all_pins[3]	values[0x0]	2796367	1			T1	100481		T2	57498		T3	1
all_pins[3]	values[0x1]	170	1			T1	2		T4	5		T9	7
all_pins[3]	transitions[0x0=>0x1]	127	1			T1	2		T4	3		T9	6
all_pins[3]	transitions[0x1=>0x0]	142	1			T1	2		T4	4		T9	7
all_pins[4]	values[0x0]	2796352	1			T1	100481		T2	57498		T3	1
all_pins[4]	values[0x1]	185	1			T1	2		T4	6		T9	8
all_pins[4]	transitions[0x0=>0x1]	159	1			T1	2		T4	4		T9	6
all_pins[4]	transitions[0x1=>0x0]	2142	1			T1	1		T4	3		T9	9
all_pins[5]	values[0x0]	2794369	1			T1	100482		T2	57498		T3	1
all_pins[5]	values[0x1]	2168	1			T1	1		T4	5		T9	11
all_pins[5]	transitions[0x0=>0x1]	1200	1			T1	1		T4	5		T9	10
all_pins[5]	transitions[0x1=>0x0]	79368	1			T1	1		T4	6		T9	5
all_pins[6]	values[0x0]	2716201	1			T1	100482		T2	57498		T3	1
all_pins[6]	values[0x1]	80336	1			T1	1		T4	6		T9	6
all_pins[6]	transitions[0x0=>0x1]	80281	1			T1	1		T4	3		T9	5
all_pins[6]	transitions[0x1=>0x0]	139	1			T1	1		T4	3		T9	6
all_pins[7]	values[0x0]	2796343	1			T1	100482		T2	57498		T3	1
all_pins[7]	values[0x1]	194	1			T1	1		T4	6		T9	7
all_pins[7]	transitions[0x0=>0x1]	140	1			T1	1		T4	6		T9	7
all_pins[7]	transitions[0x1=>0x0]	610	1			T1	2		T4	3		T9	6