Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17656

1

T1

185

T2

109

T3

14

auto[1]

13655

1

T1

153

T2

70

T4

37

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3461	1			T1	21		T2	51		T4	22
values[1]	4714	1			T1	61		T2	20		T11	6
values[2]	3403	1			T1	34		T2	40		T4	20
values[3]	3972	1			T1	40		T15	302		T18	44
values[4]	4341	1			T1	20		T2	21		T29	86
values[5]	4386	1			T2	20		T15	62		T28	20
values[6]	3488	1			T1	121		T10	4		T15	40
values[7]	3546	1			T1	41		T2	27		T3	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4116	1			T1	61		T2	20		T3	14
values[1]	4496	1			T15	85		T28	20		T29	20
values[2]	3669	1			T1	50		T2	21		T11	6
values[3]	3804	1			T1	95		T2	51		T15	27
values[4]	3692	1			T1	41		T4	25		T10	4
values[5]	3872	1			T1	50		T2	47		T4	20
values[6]	3789	1			T1	20		T2	20		T15	20
values[7]	3873	1			T1	21		T2	20		T4	22

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	267	1			T15	9		T184	46		T232	17
auto[0]	values[0]	values[1]	222	1			T28	12		T18	32		T114	8
auto[0]	values[0]	values[2]	201	1			T1	10		T15	18		T47	11
auto[0]	values[0]	values[3]	242	1			T2	36		T17	13		T79	11
auto[0]	values[0]	values[4]	313	1			T148	36		T22	12		T166	10
auto[0]	values[0]	values[5]	252	1			T45	6		T190	8		T116	71
auto[0]	values[0]	values[6]	128	1			T20	9		T196	4		T213	12
auto[0]	values[0]	values[7]	293	1			T4	8		T15	15		T72	17
auto[0]	values[1]	values[0]	388	1			T1	9		T62	4		T170	23
auto[0]	values[1]	values[1]	372	1			T162	8		T20	12		T158	12
auto[0]	values[1]	values[2]	173	1			T11	6		T188	6		T34	10
auto[0]	values[1]	values[3]	392	1			T1	30		T29	23		T18	9
auto[0]	values[1]	values[4]	395	1			T15	48		T75	11		T156	9
auto[0]	values[1]	values[5]	282	1			T2	14		T17	19		T165	10
auto[0]	values[1]	values[6]	235	1			T159	6		T276	8		T172	10
auto[0]	values[1]	values[7]	493	1			T29	12		T165	11		T199	4
auto[0]	values[2]	values[0]	203	1			T2	11		T20	12		T166	35
auto[0]	values[2]	values[1]	174	1			T75	12		T156	13		T277	2
auto[0]	values[2]	values[2]	272	1			T17	18		T47	16		T22	18
auto[0]	values[2]	values[3]	170	1			T1	11		T79	14		T278	8
auto[0]	values[2]	values[4]	258	1			T20	11		T279	2		T166	26
auto[0]	values[2]	values[5]	250	1			T4	14		T20	12		T22	11
auto[0]	values[2]	values[6]	240	1			T2	12		T29	41		T17	8
auto[0]	values[2]	values[7]	194	1			T13	8		T47	10		T114	51
auto[0]	values[3]	values[0]	172	1			T15	11		T280	8		T206	9
auto[0]	values[3]	values[1]	274	1			T15	57		T20	50		T273	4
auto[0]	values[3]	values[2]	306	1			T47	23		T79	9		T259	4
auto[0]	values[3]	values[3]	291	1			T1	11		T47	15		T159	16
auto[0]	values[3]	values[4]	236	1			T1	13		T18	9		T175	20
auto[0]	values[3]	values[5]	484	1			T15	14		T19	13		T47	16
auto[0]	values[3]	values[6]	164	1			T20	14		T173	15		T75	7
auto[0]	values[3]	values[7]	261	1			T18	13		T19	20		T74	2
auto[0]	values[4]	values[0]	308	1			T1	12		T19	32		T20	10
auto[0]	values[4]	values[1]	411	1			T151	26		T205	11		T218	10
auto[0]	values[4]	values[2]	230	1			T2	19		T18	13		T47	18
auto[0]	values[4]	values[3]	348	1			T79	14		T22	17		T75	28
auto[0]	values[4]	values[4]	408	1			T114	21		T76	28		T255	22
auto[0]	values[4]	values[5]	214	1			T182	6		T75	11		T200	13
auto[0]	values[4]	values[6]	379	1			T34	25		T165	14		T22	21
auto[0]	values[4]	values[7]	217	1			T29	77		T232	11		T170	5
auto[0]	values[5]	values[0]	393	1			T29	168		T17	5		T47	9
auto[0]	values[5]	values[1]	325	1			T29	13		T34	10		T251	14
auto[0]	values[5]	values[2]	289	1			T28	10		T34	43		T165	12
auto[0]	values[5]	values[3]	323	1			T15	13		T34	5		T47	21
auto[0]	values[5]	values[4]	195	1			T17	11		T161	6		T114	6
auto[0]	values[5]	values[5]	174	1			T152	7		T264	16		T281	2
auto[0]	values[5]	values[6]	425	1			T195	14		T170	7		T282	8
auto[0]	values[5]	values[7]	446	1			T2	5		T15	8		T29	135
auto[0]	values[6]	values[0]	303	1			T1	13		T75	11		T283	73
auto[0]	values[6]	values[1]	321	1			T17	22		T34	89		T75	12
auto[0]	values[6]	values[2]	276	1			T1	12		T30	22		T34	25
auto[0]	values[6]	values[3]	269	1			T18	67		T34	6		T156	15
auto[0]	values[6]	values[4]	189	1			T17	11		T18	17		T20	16
auto[0]	values[6]	values[5]	326	1			T1	14		T15	12		T187	2
auto[0]	values[6]	values[6]	182	1			T1	12		T15	14		T18	16
auto[0]	values[6]	values[7]	136	1			T1	11		T29	11		T20	12
auto[0]	values[7]	values[0]	157	1			T3	14		T34	12		T208	11
auto[0]	values[7]	values[1]	348	1			T17	15		T79	14		T20	19
auto[0]	values[7]	values[2]	247	1			T18	15		T34	47		T47	12
auto[0]	values[7]	values[3]	317	1			T167	35		T168	129		T198	16
auto[0]	values[7]	values[4]	209	1			T1	16		T4	8		T166	12
auto[0]	values[7]	values[5]	157	1			T1	11		T2	12		T75	10
auto[0]	values[7]	values[6]	389	1			T28	11		T29	14		T160	10
auto[0]	values[7]	values[7]	148	1			T176	2		T167	15		T284	2
auto[1]	values[0]	values[0]	282	1			T15	18		T184	4		T232	7
auto[1]	values[0]	values[1]	214	1			T28	8		T18	8		T114	78
auto[1]	values[0]	values[2]	172	1			T1	11		T15	10		T47	12
auto[1]	values[0]	values[3]	138	1			T2	15		T17	7		T79	9
auto[1]	values[0]	values[4]	80	1			T148	10		T22	8		T166	11
auto[1]	values[0]	values[5]	281	1			T155	42		T151	11		T121	7
auto[1]	values[0]	values[6]	133	1			T20	12		T213	8		T285	6
auto[1]	values[0]	values[7]	243	1			T4	14		T15	5		T72	3
auto[1]	values[1]	values[0]	232	1			T1	11		T170	8		T178	10
auto[1]	values[1]	values[1]	293	1			T20	50		T159	9		T166	89
auto[1]	values[1]	values[2]	295	1			T34	18		T20	10		T114	76
auto[1]	values[1]	values[3]	283	1			T1	11		T29	9		T18	11
auto[1]	values[1]	values[4]	275	1			T15	16		T75	9		T156	21
auto[1]	values[1]	values[5]	295	1			T2	6		T17	7		T165	12
auto[1]	values[1]	values[6]	152	1			T159	28		T172	10		T26	14
auto[1]	values[1]	values[7]	159	1			T29	8		T165	15		T166	3
auto[1]	values[2]	values[0]	216	1			T2	9		T20	8		T166	4
auto[1]	values[2]	values[1]	279	1			T75	8		T156	38		T59	4
auto[1]	values[2]	values[2]	140	1			T17	8		T47	5		T22	10
auto[1]	values[2]	values[3]	159	1			T1	23		T79	6		T169	10
auto[1]	values[2]	values[4]	227	1			T20	15		T166	24		T156	25
auto[1]	values[2]	values[5]	169	1			T4	6		T20	8		T22	9
auto[1]	values[2]	values[6]	267	1			T2	8		T29	10		T17	29
auto[1]	values[2]	values[7]	185	1			T47	10		T114	7		T173	7
auto[1]	values[3]	values[0]	300	1			T15	74		T206	11		T184	11
auto[1]	values[3]	values[1]	222	1			T15	28		T20	9		T61	8
auto[1]	values[3]	values[2]	196	1			T47	8		T79	11		T143	28
auto[1]	values[3]	values[3]	91	1			T1	9		T47	5		T159	8
auto[1]	values[3]	values[4]	122	1			T1	7		T18	15		T156	12
auto[1]	values[3]	values[5]	289	1			T15	118		T19	7		T47	12
auto[1]	values[3]	values[6]	130	1			T20	6		T173	5		T75	13
auto[1]	values[3]	values[7]	434	1			T18	7		T19	4		T20	10
auto[1]	values[4]	values[0]	321	1			T1	8		T19	6		T20	10
auto[1]	values[4]	values[1]	233	1			T151	18		T205	28		T218	10
auto[1]	values[4]	values[2]	122	1			T2	2		T18	29		T47	7
auto[1]	values[4]	values[3]	132	1			T79	6		T22	8		T75	12
auto[1]	values[4]	values[4]	379	1			T114	8		T206	8		T172	12
auto[1]	values[4]	values[5]	268	1			T75	9		T200	7		T151	12
auto[1]	values[4]	values[6]	179	1			T34	4		T165	6		T22	12
auto[1]	values[4]	values[7]	192	1			T29	9		T232	9		T170	31
auto[1]	values[5]	values[0]	176	1			T29	8		T17	44		T47	21
auto[1]	values[5]	values[1]	225	1			T29	7		T34	59		T114	19
auto[1]	values[5]	values[2]	285	1			T28	10		T34	10		T165	8
auto[1]	values[5]	values[3]	297	1			T15	14		T34	23		T47	19
auto[1]	values[5]	values[4]	155	1			T17	26		T114	14		T163	11
auto[1]	values[5]	values[5]	126	1			T152	13		T286	20		T201	8
auto[1]	values[5]	values[6]	371	1			T170	13		T178	6		T287	10
auto[1]	values[5]	values[7]	181	1			T2	15		T15	27		T29	11
auto[1]	values[6]	values[0]	240	1			T1	8		T75	9		T226	10
auto[1]	values[6]	values[1]	174	1			T17	25		T34	8		T75	8
auto[1]	values[6]	values[2]	238	1			T1	17		T34	11		T20	34
auto[1]	values[6]	values[3]	146	1			T18	10		T34	14		T156	7
auto[1]	values[6]	values[4]	144	1			T10	4		T17	9		T18	9
auto[1]	values[6]	values[5]	203	1			T1	16		T15	8		T114	11
auto[1]	values[6]	values[6]	130	1			T1	8		T15	6		T18	24
auto[1]	values[6]	values[7]	211	1			T1	10		T29	126		T20	20
auto[1]	values[7]	values[0]	158	1			T34	8		T208	58		T201	5
auto[1]	values[7]	values[1]	409	1			T17	5		T79	6		T20	22
auto[1]	values[7]	values[2]	227	1			T18	79		T34	10		T47	8
auto[1]	values[7]	values[3]	206	1			T167	7		T198	4		T223	10
auto[1]	values[7]	values[4]	107	1			T1	5		T4	17		T166	10
auto[1]	values[7]	values[5]	102	1			T1	9		T2	15		T75	10
auto[1]	values[7]	values[6]	285	1			T28	9		T29	6		T166	8
auto[1]	values[7]	values[7]	80	1			T167	5		T200	10		T227	8