Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	428	1			T1	5		T15	5		T29	2
auto[ReadAddrCrossIntoMailbox]	312	1			T15	1		T28	1		T29	1
auto[ReadAddrCrossOutOfMailbox]	325	1			T1	3		T2	1		T11	2
auto[ReadAddrCrossAllMailbox]	219	1			T1	2		T11	2		T15	2
auto[ReadAddrOutsideMailbox]	3544	1			T1	57		T2	29		T3	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2401

1

T1

29

T2

14

T3

2

auto[1]

2427

1

T1

38

T2

16

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	785	1			T1	13		T2	8		T3	2
read_ops[0x0b]	749	1			T1	12		T2	3		T4	3
read_ops[0x3b]	812	1			T1	12		T2	7		T15	11
read_ops[0x6b]	802	1			T1	8		T2	5		T3	2
read_ops[0xbb]	835	1			T1	13		T2	5		T4	2
read_ops[0xeb]	845	1			T1	9		T2	2		T4	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T15	1		T19	1		T47	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T1	1		T15	1		T18	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T188	1		T34	1		T47	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T188	1		T18	1		T34	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T2	1		T166	1		T200	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T15	1		T18	1		T20	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T200	1		T151	1		T226	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T1	2		T20	1		T22	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T1	6		T2	3		T3	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T1	4		T2	4		T3	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T15	1		T59	2		T282	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T15	1		T47	2		T20	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T22	1		T151	1		T288	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T34	1		T79	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T11	1		T15	1		T28	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T11	1		T17	1		T18	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T11	1		T19	1		T47	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T11	1		T15	1		T47	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	254	1			T1	2		T4	1		T15	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T1	10		T2	3		T4	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T17	1		T160	2		T79	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T1	2		T17	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T47	1		T166	1		T75	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T47	1		T75	2		T151	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T17	1		T20	1		T22	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T15	1		T17	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T15	1		T188	1		T167	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T188	1		T173	1		T75	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T1	6		T2	3		T15	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T1	4		T2	4		T15	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	49	1			T17	1		T34	1		T251	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T29	1		T19	1		T251	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T28	1		T17	1		T47	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T29	1		T20	1		T159	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T1	1		T156	1		T151	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T19	2		T47	2		T156	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T28	1		T160	1		T166	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T160	1		T20	1		T159	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T1	4		T2	3		T3	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	260	1			T1	3		T2	2		T3	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T29	1		T17	1		T18	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T1	1		T47	1		T195	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T161	1		T156	1		T170	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T161	1		T20	1		T75	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T28	1		T17	1		T18	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T1	1		T15	1		T18	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T20	1		T114	1		T75	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T20	2		T173	1		T178	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	344	1			T1	5		T2	2		T4	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T1	6		T2	3		T15	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T15	1		T47	1		T20	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T1	1		T159	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T15	1		T20	1		T114	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T18	1		T75	1		T156	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T1	1		T34	1		T161	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T15	2		T161	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T34	1		T22	1		T289	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T20	1		T166	1		T289	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T1	4		T2	2		T4	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	327	1			T1	3		T4	4		T15	1