Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	846	1			T1	7		T4	18		T9	30
all_values[1]	846	1			T1	7		T4	18		T9	30
all_values[2]	846	1			T1	7		T4	18		T9	30
all_values[3]	846	1			T1	7		T4	18		T9	30
all_values[4]	846	1			T1	7		T4	18		T9	30
all_values[5]	846	1			T1	7		T4	18		T9	30
all_values[6]	846	1			T1	7		T4	18		T9	30
all_values[7]	846	1			T1	7		T4	18		T9	30

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3718

1

T1

32

T4

74

T9

138

auto[1]

3050

1

T1

24

T4

70

T9

102

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2717

1

T1

19

T4

57

T9

102

auto[1]

4051

1

T1

37

T4

87

T9

138

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3894

1

T1

30

T4

78

T9

138

auto[1]

2874

1

T1

26

T4

66

T9

102

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	150	1			T4	3		T9	10		T20	3
all_values[0]	auto[0]	auto[0]	auto[1]	89	1			T1	1		T4	1		T9	1
all_values[0]	auto[0]	auto[1]	auto[0]	149	1			T1	2		T4	6		T9	7
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T4	1		T9	2		T18	3
all_values[0]	auto[1]	auto[0]	auto[1]	205	1			T1	2		T4	2		T9	5
all_values[0]	auto[1]	auto[1]	auto[1]	170	1			T1	2		T4	5		T9	5
all_values[1]	auto[0]	auto[0]	auto[0]	181	1			T1	1		T4	7		T9	6
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T1	1		T9	7		T20	2
all_values[1]	auto[0]	auto[1]	auto[0]	123	1			T1	1		T4	2		T9	2
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T4	1		T9	1		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T1	2		T4	5		T9	8
all_values[1]	auto[1]	auto[1]	auto[1]	172	1			T1	2		T4	3		T9	6
all_values[2]	auto[0]	auto[0]	auto[0]	157	1			T4	3		T9	7		T17	1
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T1	1		T4	2		T9	2
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T4	1		T9	7		T17	1
all_values[2]	auto[0]	auto[1]	auto[1]	89	1			T1	1		T4	1		T9	3
all_values[2]	auto[1]	auto[0]	auto[1]	202	1			T1	4		T4	6		T9	4
all_values[2]	auto[1]	auto[1]	auto[1]	165	1			T1	1		T4	5		T9	7
all_values[3]	auto[0]	auto[0]	auto[0]	202	1			T1	2		T4	1		T9	3
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T1	1		T9	1		T22	1
all_values[3]	auto[0]	auto[1]	auto[0]	140	1			T1	1		T4	3		T9	6
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T1	2		T4	2		T9	3
all_values[3]	auto[1]	auto[0]	auto[1]	205	1			T1	1		T4	4		T9	13
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T4	8		T9	4		T17	1
all_values[4]	auto[0]	auto[0]	auto[0]	207	1			T1	2		T4	2		T9	7
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T1	2		T4	1		T9	5
all_values[4]	auto[0]	auto[1]	auto[0]	148	1			T4	5		T9	5		T17	1
all_values[4]	auto[0]	auto[1]	auto[1]	79	1			T1	1		T4	3		T9	1
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T1	2		T4	4		T9	4
all_values[4]	auto[1]	auto[1]	auto[1]	137	1			T4	3		T9	8		T18	1
all_values[5]	auto[0]	auto[0]	auto[0]	261	1			T1	2		T4	6		T9	10
all_values[5]	auto[0]	auto[1]	auto[0]	214	1			T1	3		T4	3		T9	6
all_values[5]	auto[1]	auto[0]	auto[1]	206	1			T4	5		T9	6		T18	2
all_values[5]	auto[1]	auto[1]	auto[1]	165	1			T1	2		T4	4		T9	8
all_values[6]	auto[0]	auto[0]	auto[0]	167	1			T4	6		T9	12		T22	2
all_values[6]	auto[0]	auto[0]	auto[1]	92	1			T1	1		T4	3		T9	2
all_values[6]	auto[0]	auto[1]	auto[0]	144	1			T9	5		T17	2		T18	3
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T4	3		T9	2		T18	1
all_values[6]	auto[1]	auto[0]	auto[1]	206	1			T1	4		T4	5		T9	5
all_values[6]	auto[1]	auto[1]	auto[1]	153	1			T1	2		T4	1		T9	4
all_values[7]	auto[0]	auto[0]	auto[0]	184	1			T1	2		T4	6		T9	4
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T9	6		T17	1		T19	1
all_values[7]	auto[0]	auto[1]	auto[0]	146	1			T1	3		T4	3		T9	5
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T4	3		T18	1		T22	3
all_values[7]	auto[1]	auto[0]	auto[1]	189	1			T1	1		T4	2		T9	10
all_values[7]	auto[1]	auto[1]	auto[1]	161	1			T1	1		T4	4		T9	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal