Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1793

1

T1

11

T2

6

T4

4

auto[1]

1770

1

T1

8

T2

5

T4

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1974

1

T1

16

T2

9

T4

11

auto[1]

1589

1

T1

3

T2

2

T9

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2768

1

T1

10

T2

9

T4

7

auto[1]

795

1

T1

9

T2

2

T4

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	705	1			T1	2		T2	4		T4	1
valid[1]	657	1			T1	9		T2	1		T4	2
valid[2]	721	1			T1	4		T2	3		T4	3
valid[3]	738	1			T1	3		T2	1		T4	4
valid[4]	742	1			T1	1		T2	2		T4	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	128	1			T2	1		T4	1		T9	1
auto[0]	auto[0]	valid[0]	auto[1]	149	1			T23	5		T73	3		T301	1
auto[0]	auto[0]	valid[1]	auto[0]	109	1			T1	3		T8	2		T15	1
auto[0]	auto[0]	valid[1]	auto[1]	157	1			T2	1		T16	1		T23	1
auto[0]	auto[0]	valid[2]	auto[0]	145	1			T2	3		T4	1		T9	1
auto[0]	auto[0]	valid[2]	auto[1]	150	1			T1	1		T23	4		T35	2
auto[0]	auto[0]	valid[3]	auto[0]	129	1			T4	2		T8	1		T68	1
auto[0]	auto[0]	valid[3]	auto[1]	151	1			T23	4		T301	1		T310	3
auto[0]	auto[0]	valid[4]	auto[0]	112	1			T1	1		T9	3		T17	1
auto[0]	auto[0]	valid[4]	auto[1]	161	1			T23	5		T35	1		T73	1
auto[0]	auto[1]	valid[0]	auto[0]	107	1			T1	1		T2	2		T35	1
auto[0]	auto[1]	valid[0]	auto[1]	171	1			T23	1		T71	1		T18	2
auto[0]	auto[1]	valid[1]	auto[0]	108	1			T4	2		T8	1		T15	2
auto[0]	auto[1]	valid[1]	auto[1]	138	1			T1	1		T23	3		T19	1
auto[0]	auto[1]	valid[2]	auto[0]	111	1			T1	1		T4	1		T9	1
auto[0]	auto[1]	valid[2]	auto[1]	156	1			T1	1		T15	2		T23	3
auto[0]	auto[1]	valid[3]	auto[0]	114	1			T1	1		T9	4		T15	2
auto[0]	auto[1]	valid[3]	auto[1]	176	1			T2	1		T15	1		T16	1
auto[0]	auto[1]	valid[4]	auto[0]	116	1			T2	1		T8	1		T9	1
auto[0]	auto[1]	valid[4]	auto[1]	180	1			T9	1		T23	2		T35	1
auto[1]	auto[0]	valid[0]	auto[0]	80	1			T1	1		T2	1		T9	1
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T1	3		T16	1		T301	1
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T1	1		T8	1		T9	1
auto[1]	auto[0]	valid[3]	auto[0]	85	1			T1	1		T8	1		T9	1
auto[1]	auto[0]	valid[4]	auto[0]	75	1			T301	2		T47	2		T300	1
auto[1]	auto[1]	valid[0]	auto[0]	70	1			T8	1		T15	1		T35	1
auto[1]	auto[1]	valid[1]	auto[0]	64	1			T1	2		T15	1		T68	1
auto[1]	auto[1]	valid[2]	auto[0]	78	1			T4	1		T8	1		T35	1
auto[1]	auto[1]	valid[3]	auto[0]	83	1			T1	1		T4	2		T9	1
auto[1]	auto[1]	valid[4]	auto[0]	98	1			T2	1		T4	1		T15	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal