Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49504

1

T1

597

T2

124

T4

315

auto[1]

17777

1

T1

125

T2

24

T9

33

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49059

1

T1

487

T2

105

T4

207

auto[1]

18222

1

T1

235

T2

43

T4

108

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34952	1			T1	384		T2	77		T4	174
others[1]	5669	1			T1	54		T2	14		T4	21
others[2]	5546	1			T1	53		T2	16		T4	30
others[3]	6328	1			T1	64		T2	16		T4	32
interest[1]	3637	1			T1	38		T2	6		T4	15
interest[4]	22846	1			T1	243		T2	43		T4	118
interest[64]	11149	1			T1	129		T2	19		T4	43

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16324	1			T1	198		T2	43		T4	110
auto[0]	auto[0]	others[1]	2648	1			T1	26		T2	8		T4	16
auto[0]	auto[0]	others[2]	2596	1			T1	24		T2	12		T4	19
auto[0]	auto[0]	others[3]	2900	1			T1	32		T2	6		T4	23
auto[0]	auto[0]	interest[1]	1654	1			T1	23		T2	2		T4	9
auto[0]	auto[0]	interest[4]	10637	1			T1	127		T2	24		T4	76
auto[0]	auto[0]	interest[64]	5160	1			T1	59		T2	10		T4	30
auto[0]	auto[1]	others[0]	9251	1			T1	59		T2	13		T9	11
auto[0]	auto[1]	others[1]	1512	1			T1	11		T2	2		T9	8
auto[0]	auto[1]	others[2]	1431	1			T1	11		T2	2		T9	5
auto[0]	auto[1]	others[3]	1710	1			T1	14		T2	3		T9	4
auto[0]	auto[1]	interest[1]	995	1			T1	7		T2	1		T9	2
auto[0]	auto[1]	interest[4]	6068	1			T1	32		T2	8		T9	7
auto[0]	auto[1]	interest[64]	2878	1			T1	23		T2	3		T9	3
auto[1]	auto[0]	others[0]	9377	1			T1	127		T2	21		T4	64
auto[1]	auto[0]	others[1]	1509	1			T1	17		T2	4		T4	5
auto[1]	auto[0]	others[2]	1519	1			T1	18		T2	2		T4	11
auto[1]	auto[0]	others[3]	1718	1			T1	18		T2	7		T4	9
auto[1]	auto[0]	interest[1]	988	1			T1	8		T2	3		T4	6
auto[1]	auto[0]	interest[4]	6141	1			T1	84		T2	11		T4	42
auto[1]	auto[0]	interest[64]	3111	1			T1	47		T2	6		T4	13

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal