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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1130
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T97 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3024381554 Aug 08 07:42:33 PM PDT 24 Aug 08 07:42:37 PM PDT 24 147909214 ps
T110 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3839246126 Aug 08 07:42:35 PM PDT 24 Aug 08 07:42:37 PM PDT 24 53043126 ps
T1021 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2271804286 Aug 08 07:42:31 PM PDT 24 Aug 08 07:42:34 PM PDT 24 209565444 ps
T1022 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3445487287 Aug 08 07:42:33 PM PDT 24 Aug 08 07:42:35 PM PDT 24 225484831 ps
T1023 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2949487020 Aug 08 07:43:05 PM PDT 24 Aug 08 07:43:06 PM PDT 24 14368492 ps
T1024 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3932560879 Aug 08 07:42:24 PM PDT 24 Aug 08 07:42:39 PM PDT 24 219563045 ps
T1025 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1791087353 Aug 08 07:42:54 PM PDT 24 Aug 08 07:42:55 PM PDT 24 24452991 ps
T1026 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.44697861 Aug 08 07:42:23 PM PDT 24 Aug 08 07:42:58 PM PDT 24 7528687254 ps
T141 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4164579149 Aug 08 07:42:43 PM PDT 24 Aug 08 07:42:47 PM PDT 24 289294468 ps
T1027 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1535292789 Aug 08 07:43:03 PM PDT 24 Aug 08 07:43:04 PM PDT 24 27704238 ps
T1028 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.947616471 Aug 08 07:42:55 PM PDT 24 Aug 08 07:42:56 PM PDT 24 12854965 ps
T1029 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3956670154 Aug 08 07:43:05 PM PDT 24 Aug 08 07:43:06 PM PDT 24 60939758 ps
T1030 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4122180575 Aug 08 07:42:22 PM PDT 24 Aug 08 07:42:23 PM PDT 24 18726874 ps
T92 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2554567817 Aug 08 07:42:22 PM PDT 24 Aug 08 07:42:35 PM PDT 24 203813735 ps
T85 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.369620431 Aug 08 07:42:36 PM PDT 24 Aug 08 07:42:38 PM PDT 24 33070456 ps
T243 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.757889592 Aug 08 07:42:37 PM PDT 24 Aug 08 07:42:52 PM PDT 24 1312878435 ps
T93 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2132766978 Aug 08 07:42:33 PM PDT 24 Aug 08 07:42:37 PM PDT 24 142352514 ps
T88 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1281702616 Aug 08 07:42:33 PM PDT 24 Aug 08 07:42:36 PM PDT 24 428150350 ps
T1031 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1571017410 Aug 08 07:42:47 PM PDT 24 Aug 08 07:42:48 PM PDT 24 21097959 ps
T1032 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.434265080 Aug 08 07:43:05 PM PDT 24 Aug 08 07:43:05 PM PDT 24 21976486 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3194364268 Aug 08 07:42:33 PM PDT 24 Aug 08 07:43:08 PM PDT 24 3079023006 ps
T1034 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2751721207 Aug 08 07:43:04 PM PDT 24 Aug 08 07:43:05 PM PDT 24 19211604 ps
T1035 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2390878196 Aug 08 07:42:42 PM PDT 24 Aug 08 07:42:43 PM PDT 24 15627992 ps
T109 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2673351164 Aug 08 07:42:32 PM PDT 24 Aug 08 07:42:34 PM PDT 24 291578727 ps
T1036 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1066026488 Aug 08 07:42:44 PM PDT 24 Aug 08 07:42:52 PM PDT 24 1440849624 ps
T241 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1521660643 Aug 08 07:42:42 PM PDT 24 Aug 08 07:42:50 PM PDT 24 4336163025 ps
T1037 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1866248837 Aug 08 07:42:41 PM PDT 24 Aug 08 07:42:46 PM PDT 24 333892171 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.281094237 Aug 08 07:42:23 PM PDT 24 Aug 08 07:42:25 PM PDT 24 25557359 ps
T1039 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1003498315 Aug 08 07:42:36 PM PDT 24 Aug 08 07:42:44 PM PDT 24 121584696 ps
T89 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1808427961 Aug 08 07:42:48 PM PDT 24 Aug 08 07:42:52 PM PDT 24 329097962 ps
T91 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.941024754 Aug 08 07:42:34 PM PDT 24 Aug 08 07:42:40 PM PDT 24 2318318446 ps
T1040 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1402910000 Aug 08 07:42:24 PM PDT 24 Aug 08 07:42:25 PM PDT 24 44282965 ps
T1041 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4154341425 Aug 08 07:43:12 PM PDT 24 Aug 08 07:43:13 PM PDT 24 13567932 ps
T242 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2719838777 Aug 08 07:42:58 PM PDT 24 Aug 08 07:43:19 PM PDT 24 1903000743 ps
T1042 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.683187346 Aug 08 07:42:32 PM PDT 24 Aug 08 07:42:33 PM PDT 24 55012870 ps
T1043 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1424122789 Aug 08 07:42:55 PM PDT 24 Aug 08 07:42:56 PM PDT 24 25857577 ps
T1044 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3979225473 Aug 08 07:42:56 PM PDT 24 Aug 08 07:42:57 PM PDT 24 16609479 ps
T1045 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4090262294 Aug 08 07:43:04 PM PDT 24 Aug 08 07:43:05 PM PDT 24 16662255 ps
T1046 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1713122906 Aug 08 07:42:54 PM PDT 24 Aug 08 07:42:55 PM PDT 24 21465301 ps
T1047 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.888485351 Aug 08 07:42:45 PM PDT 24 Aug 08 07:42:47 PM PDT 24 256439914 ps
T1048 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2973074372 Aug 08 07:42:47 PM PDT 24 Aug 08 07:42:51 PM PDT 24 63908866 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3534851369 Aug 08 07:42:34 PM PDT 24 Aug 08 07:42:56 PM PDT 24 902035164 ps
T239 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2640845322 Aug 08 07:42:44 PM PDT 24 Aug 08 07:43:03 PM PDT 24 1234136698 ps
T1050 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1183230111 Aug 08 07:43:05 PM PDT 24 Aug 08 07:43:05 PM PDT 24 37606504 ps
T1051 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2495384382 Aug 08 07:42:30 PM PDT 24 Aug 08 07:42:37 PM PDT 24 546022948 ps
T1052 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1738837861 Aug 08 07:42:24 PM PDT 24 Aug 08 07:42:27 PM PDT 24 148412940 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2552809224 Aug 08 07:42:23 PM PDT 24 Aug 08 07:42:25 PM PDT 24 398930048 ps
T1054 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3371335986 Aug 08 07:42:52 PM PDT 24 Aug 08 07:42:59 PM PDT 24 411825917 ps
T1055 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1234808121 Aug 08 07:43:00 PM PDT 24 Aug 08 07:43:02 PM PDT 24 130507798 ps
T1056 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2740819841 Aug 08 07:42:21 PM PDT 24 Aug 08 07:42:23 PM PDT 24 20805985 ps
T94 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3500411599 Aug 08 07:42:45 PM PDT 24 Aug 08 07:42:47 PM PDT 24 351543805 ps
T1057 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3453834760 Aug 08 07:42:48 PM PDT 24 Aug 08 07:42:49 PM PDT 24 13621941 ps
T1058 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.915166663 Aug 08 07:42:33 PM PDT 24 Aug 08 07:42:37 PM PDT 24 175174141 ps
T240 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2718998279 Aug 08 07:42:56 PM PDT 24 Aug 08 07:43:12 PM PDT 24 657114269 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3648460930 Aug 08 07:42:23 PM PDT 24 Aug 08 07:42:25 PM PDT 24 211704277 ps
T1060 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4284370596 Aug 08 07:42:37 PM PDT 24 Aug 08 07:42:40 PM PDT 24 117177166 ps
T90 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2275212096 Aug 08 07:42:37 PM PDT 24 Aug 08 07:42:42 PM PDT 24 847010948 ps
T1061 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1916143235 Aug 08 07:42:22 PM PDT 24 Aug 08 07:42:24 PM PDT 24 205693327 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2487745913 Aug 08 07:42:42 PM PDT 24 Aug 08 07:42:43 PM PDT 24 17819227 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3890502742 Aug 08 07:42:23 PM PDT 24 Aug 08 07:42:36 PM PDT 24 1010007557 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.426008976 Aug 08 07:42:23 PM PDT 24 Aug 08 07:42:43 PM PDT 24 3224582878 ps
T1065 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3748973730 Aug 08 07:43:04 PM PDT 24 Aug 08 07:43:05 PM PDT 24 11697659 ps
T237 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3034616401 Aug 08 07:42:43 PM PDT 24 Aug 08 07:42:47 PM PDT 24 1055298132 ps
T1066 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4253223488 Aug 08 07:42:31 PM PDT 24 Aug 08 07:42:32 PM PDT 24 122372706 ps
T1067 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.409921943 Aug 08 07:42:56 PM PDT 24 Aug 08 07:43:01 PM PDT 24 216958289 ps
T1068 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4253420348 Aug 08 07:43:04 PM PDT 24 Aug 08 07:43:05 PM PDT 24 12164746 ps
T1069 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1996139111 Aug 08 07:42:24 PM PDT 24 Aug 08 07:42:28 PM PDT 24 61965092 ps
T1070 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3158023606 Aug 08 07:42:34 PM PDT 24 Aug 08 07:42:36 PM PDT 24 23278394 ps
T1071 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3116215089 Aug 08 07:42:31 PM PDT 24 Aug 08 07:42:35 PM PDT 24 645018101 ps
T244 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3528700597 Aug 08 07:42:45 PM PDT 24 Aug 08 07:43:01 PM PDT 24 343967431 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1210789371 Aug 08 07:42:34 PM PDT 24 Aug 08 07:42:35 PM PDT 24 13204097 ps
T1073 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.457371111 Aug 08 07:42:54 PM PDT 24 Aug 08 07:42:55 PM PDT 24 108850472 ps
T1074 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4140416791 Aug 08 07:42:35 PM PDT 24 Aug 08 07:42:35 PM PDT 24 11109238 ps
T1075 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2525720374 Aug 08 07:43:00 PM PDT 24 Aug 08 07:43:01 PM PDT 24 16621754 ps
T1076 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2094633225 Aug 08 07:42:31 PM PDT 24 Aug 08 07:42:32 PM PDT 24 17568916 ps
T1077 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.977539619 Aug 08 07:43:02 PM PDT 24 Aug 08 07:43:02 PM PDT 24 19963389 ps
T1078 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2493261864 Aug 08 07:42:55 PM PDT 24 Aug 08 07:42:58 PM PDT 24 39621942 ps
T1079 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.405540489 Aug 08 07:42:40 PM PDT 24 Aug 08 07:42:42 PM PDT 24 62995007 ps
T1080 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2036855559 Aug 08 07:42:56 PM PDT 24 Aug 08 07:42:56 PM PDT 24 20139964 ps
T1081 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.480274602 Aug 08 07:42:55 PM PDT 24 Aug 08 07:42:57 PM PDT 24 355157348 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4025920529 Aug 08 07:42:32 PM PDT 24 Aug 08 07:42:34 PM PDT 24 24705869 ps
T1083 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3463735724 Aug 08 07:42:30 PM PDT 24 Aug 08 07:42:32 PM PDT 24 264622858 ps
T1084 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.86737794 Aug 08 07:43:04 PM PDT 24 Aug 08 07:43:05 PM PDT 24 12025721 ps
T1085 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3586204086 Aug 08 07:43:04 PM PDT 24 Aug 08 07:43:05 PM PDT 24 54904900 ps
T1086 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1096235508 Aug 08 07:42:56 PM PDT 24 Aug 08 07:42:59 PM PDT 24 1097953346 ps
T1087 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2010614400 Aug 08 07:43:02 PM PDT 24 Aug 08 07:43:03 PM PDT 24 42361036 ps
T1088 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1917546312 Aug 08 07:42:45 PM PDT 24 Aug 08 07:42:47 PM PDT 24 759737594 ps
T1089 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2409683260 Aug 08 07:42:53 PM PDT 24 Aug 08 07:42:56 PM PDT 24 411805009 ps
T1090 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4284365368 Aug 08 07:42:35 PM PDT 24 Aug 08 07:42:35 PM PDT 24 27765366 ps
T1091 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3267143301 Aug 08 07:42:56 PM PDT 24 Aug 08 07:42:57 PM PDT 24 49610079 ps
T70 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3697864538 Aug 08 07:42:32 PM PDT 24 Aug 08 07:42:34 PM PDT 24 137628954 ps
T1092 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.737883955 Aug 08 07:42:56 PM PDT 24 Aug 08 07:42:59 PM PDT 24 149727010 ps
T1093 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4199198459 Aug 08 07:42:40 PM PDT 24 Aug 08 07:42:42 PM PDT 24 169868748 ps
T1094 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3874370941 Aug 08 07:42:32 PM PDT 24 Aug 08 07:42:34 PM PDT 24 74775000 ps
T1095 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1632484585 Aug 08 07:42:48 PM PDT 24 Aug 08 07:42:50 PM PDT 24 85769502 ps
T1096 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1443546694 Aug 08 07:42:21 PM PDT 24 Aug 08 07:42:23 PM PDT 24 87077426 ps
T1097 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1140619907 Aug 08 07:43:01 PM PDT 24 Aug 08 07:43:02 PM PDT 24 47781965 ps
T1098 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3834615375 Aug 08 07:42:43 PM PDT 24 Aug 08 07:42:47 PM PDT 24 492970234 ps
T1099 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1479807416 Aug 08 07:43:05 PM PDT 24 Aug 08 07:43:06 PM PDT 24 41222575 ps
T1100 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2554053442 Aug 08 07:42:45 PM PDT 24 Aug 08 07:42:45 PM PDT 24 46269967 ps
T1101 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.123317723 Aug 08 07:42:57 PM PDT 24 Aug 08 07:42:59 PM PDT 24 142837950 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.850075177 Aug 08 07:42:37 PM PDT 24 Aug 08 07:42:38 PM PDT 24 20039385 ps
T1103 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1585126635 Aug 08 07:42:43 PM PDT 24 Aug 08 07:42:47 PM PDT 24 2445063964 ps
T1104 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4065389883 Aug 08 07:42:47 PM PDT 24 Aug 08 07:42:50 PM PDT 24 78302052 ps
T1105 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2717232688 Aug 08 07:43:03 PM PDT 24 Aug 08 07:43:04 PM PDT 24 16942387 ps
T1106 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2547483971 Aug 08 07:43:05 PM PDT 24 Aug 08 07:43:06 PM PDT 24 29484204 ps
T1107 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.210242225 Aug 08 07:42:22 PM PDT 24 Aug 08 07:42:25 PM PDT 24 102843770 ps
T1108 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1082882795 Aug 08 07:42:20 PM PDT 24 Aug 08 07:42:27 PM PDT 24 466258696 ps
T1109 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.980479538 Aug 08 07:42:21 PM PDT 24 Aug 08 07:42:24 PM PDT 24 97479040 ps
T1110 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1977285766 Aug 08 07:42:33 PM PDT 24 Aug 08 07:42:34 PM PDT 24 15438492 ps
T1111 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3289704959 Aug 08 07:42:45 PM PDT 24 Aug 08 07:42:46 PM PDT 24 60363119 ps
T1112 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3581461625 Aug 08 07:42:23 PM PDT 24 Aug 08 07:42:25 PM PDT 24 781233643 ps
T1113 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1259602263 Aug 08 07:42:40 PM PDT 24 Aug 08 07:42:57 PM PDT 24 295725491 ps
T1114 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3018328299 Aug 08 07:42:21 PM PDT 24 Aug 08 07:42:24 PM PDT 24 198756920 ps
T1115 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3219599104 Aug 08 07:43:03 PM PDT 24 Aug 08 07:43:04 PM PDT 24 146747292 ps
T1116 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3470633887 Aug 08 07:42:31 PM PDT 24 Aug 08 07:42:37 PM PDT 24 391331556 ps
T1117 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.49540212 Aug 08 07:42:43 PM PDT 24 Aug 08 07:42:45 PM PDT 24 62579342 ps
T1118 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1760836421 Aug 08 07:42:23 PM PDT 24 Aug 08 07:42:24 PM PDT 24 32356581 ps
T1119 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2228839903 Aug 08 07:43:05 PM PDT 24 Aug 08 07:43:06 PM PDT 24 59955143 ps
T1120 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3842058755 Aug 08 07:42:56 PM PDT 24 Aug 08 07:42:59 PM PDT 24 215716347 ps
T1121 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.690204389 Aug 08 07:42:20 PM PDT 24 Aug 08 07:42:28 PM PDT 24 4218001520 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4141786282 Aug 08 07:42:33 PM PDT 24 Aug 08 07:42:35 PM PDT 24 56468478 ps
T1123 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.507974438 Aug 08 07:42:55 PM PDT 24 Aug 08 07:42:56 PM PDT 24 15030102 ps
T1124 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2205475576 Aug 08 07:42:56 PM PDT 24 Aug 08 07:42:57 PM PDT 24 32488840 ps
T1125 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.286096549 Aug 08 07:42:44 PM PDT 24 Aug 08 07:42:48 PM PDT 24 155282333 ps
T1126 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.335013458 Aug 08 07:42:45 PM PDT 24 Aug 08 07:43:08 PM PDT 24 820818109 ps
T1127 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2595166330 Aug 08 07:42:44 PM PDT 24 Aug 08 07:42:48 PM PDT 24 65201783 ps
T1128 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.211504497 Aug 08 07:42:46 PM PDT 24 Aug 08 07:42:49 PM PDT 24 794350631 ps
T1129 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3770212267 Aug 08 07:42:55 PM PDT 24 Aug 08 07:42:57 PM PDT 24 131203553 ps
T1130 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1072082479 Aug 08 07:42:33 PM PDT 24 Aug 08 07:42:37 PM PDT 24 159061404 ps

Test location /workspace/coverage/default/31.spi_device_stress_all.1872971607
Short name T1
Test name
Test status
Simulation time 121665191618 ps
CPU time 861.61 seconds
Started Aug 08 07:48:01 PM PDT 24
Finished Aug 08 08:02:23 PM PDT 24
Peak memory 273408 kb
Host smart-6c4d0d86-4237-4fa8-be64-fd229e59e66e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872971607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1872971607
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1928671256
Short name T15
Test name
Test status
Simulation time 17663652766 ps
CPU time 130.6 seconds
Started Aug 08 07:48:08 PM PDT 24
Finished Aug 08 07:50:19 PM PDT 24
Peak memory 269224 kb
Host smart-44b9863d-64a2-465f-b940-bffeb773cca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928671256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1928671256
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2266723028
Short name T96
Test name
Test status
Simulation time 169099639 ps
CPU time 2.52 seconds
Started Aug 08 07:42:34 PM PDT 24
Finished Aug 08 07:42:37 PM PDT 24
Peak memory 217500 kb
Host smart-e51dfe96-bb61-4397-b9c3-412f80c381db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266723028 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2266723028
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2083645405
Short name T9
Test name
Test status
Simulation time 20299707093 ps
CPU time 115.34 seconds
Started Aug 08 07:46:15 PM PDT 24
Finished Aug 08 07:48:10 PM PDT 24
Peak memory 266832 kb
Host smart-58953d6a-96f4-46ee-8e64-ba0552ce16ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083645405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2083645405
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1654750340
Short name T20
Test name
Test status
Simulation time 165475992341 ps
CPU time 415.39 seconds
Started Aug 08 07:49:02 PM PDT 24
Finished Aug 08 07:55:58 PM PDT 24
Peak memory 300892 kb
Host smart-df6dd38b-cc33-443c-92f9-99f812f40a55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654750340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1654750340
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4222254724
Short name T53
Test name
Test status
Simulation time 16648693 ps
CPU time 0.73 seconds
Started Aug 08 07:45:53 PM PDT 24
Finished Aug 08 07:45:54 PM PDT 24
Peak memory 216472 kb
Host smart-e5793fd1-11a2-4ba1-b809-5e687d429c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222254724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4222254724
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1674823137
Short name T47
Test name
Test status
Simulation time 127552645696 ps
CPU time 1099.49 seconds
Started Aug 08 07:47:24 PM PDT 24
Finished Aug 08 08:05:44 PM PDT 24
Peak memory 270740 kb
Host smart-3900e00d-6b69-4666-afe2-c03957188a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674823137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1674823137
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2306592029
Short name T147
Test name
Test status
Simulation time 94561143129 ps
CPU time 929.89 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 08:02:05 PM PDT 24
Peak memory 298196 kb
Host smart-15a86473-677a-4bb6-854d-7d6768b856f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306592029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2306592029
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4020359179
Short name T83
Test name
Test status
Simulation time 392449883 ps
CPU time 8.72 seconds
Started Aug 08 07:42:37 PM PDT 24
Finished Aug 08 07:42:46 PM PDT 24
Peak memory 215432 kb
Host smart-6d3ec052-3d09-443f-aff8-c2c760fc9379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020359179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4020359179
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.543121134
Short name T166
Test name
Test status
Simulation time 48206266603 ps
CPU time 188.32 seconds
Started Aug 08 07:46:43 PM PDT 24
Finished Aug 08 07:49:52 PM PDT 24
Peak memory 263080 kb
Host smart-9e914d39-844f-4f14-ae59-b5373b721f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543121134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.543121134
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.205621785
Short name T365
Test name
Test status
Simulation time 27131689 ps
CPU time 0.69 seconds
Started Aug 08 07:46:34 PM PDT 24
Finished Aug 08 07:46:35 PM PDT 24
Peak memory 205244 kb
Host smart-49d27639-a6e1-4c30-8ca2-613e0d412066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205621785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.205621785
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2551336610
Short name T75
Test name
Test status
Simulation time 36662752991 ps
CPU time 275.87 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:51:11 PM PDT 24
Peak memory 262072 kb
Host smart-7fe6f7c0-17ee-49a9-943b-02470a6fea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551336610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2551336610
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3693317169
Short name T121
Test name
Test status
Simulation time 267224164268 ps
CPU time 375.17 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:53:23 PM PDT 24
Peak memory 265140 kb
Host smart-c174a268-6a38-435f-a2b0-c53d4f56d43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693317169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3693317169
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2613825017
Short name T128
Test name
Test status
Simulation time 1697515722 ps
CPU time 3.96 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:07 PM PDT 24
Peak memory 220928 kb
Host smart-33f6f61c-9db6-4a7f-95c3-601d6296e2c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2613825017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2613825017
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.932501227
Short name T18
Test name
Test status
Simulation time 11634953956 ps
CPU time 190.47 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:50:18 PM PDT 24
Peak memory 266132 kb
Host smart-3dfbe3c6-1bdb-49de-998e-67aa05171208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932501227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.932501227
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1433619128
Short name T69
Test name
Test status
Simulation time 129707525 ps
CPU time 1.24 seconds
Started Aug 08 07:42:21 PM PDT 24
Finished Aug 08 07:42:22 PM PDT 24
Peak memory 207184 kb
Host smart-32d1899f-1473-4bd3-9482-ed5bf4cd9056
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433619128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1433619128
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3434605987
Short name T52
Test name
Test status
Simulation time 148655341 ps
CPU time 3.96 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:38 PM PDT 24
Peak memory 215244 kb
Host smart-f3c7af4d-a3e6-4f6c-b447-f4317941df53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434605987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
434605987
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4114750078
Short name T203
Test name
Test status
Simulation time 4604952415 ps
CPU time 105.42 seconds
Started Aug 08 07:48:39 PM PDT 24
Finished Aug 08 07:50:25 PM PDT 24
Peak memory 264300 kb
Host smart-8e24f660-b3c5-4e93-b173-f17fd53afcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114750078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4114750078
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3138618348
Short name T193
Test name
Test status
Simulation time 419371791072 ps
CPU time 339.8 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:52:30 PM PDT 24
Peak memory 256308 kb
Host smart-17371a73-1702-4167-8e07-0a9f76ffb733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138618348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3138618348
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3085471907
Short name T56
Test name
Test status
Simulation time 40185113 ps
CPU time 0.97 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:04 PM PDT 24
Peak memory 236920 kb
Host smart-2ba3dc1d-d87c-4cae-9db8-a28001220c84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085471907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3085471907
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2640845322
Short name T239
Test name
Test status
Simulation time 1234136698 ps
CPU time 18.49 seconds
Started Aug 08 07:42:44 PM PDT 24
Finished Aug 08 07:43:03 PM PDT 24
Peak memory 215152 kb
Host smart-867785d4-30bf-4804-886d-7a930962666d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640845322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2640845322
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2968743937
Short name T211
Test name
Test status
Simulation time 16429559813 ps
CPU time 84.62 seconds
Started Aug 08 07:47:43 PM PDT 24
Finished Aug 08 07:49:08 PM PDT 24
Peak memory 256108 kb
Host smart-29c21646-a142-4c60-8a53-faa03b53a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968743937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2968743937
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1759394279
Short name T226
Test name
Test status
Simulation time 40164620565 ps
CPU time 170.74 seconds
Started Aug 08 07:48:44 PM PDT 24
Finished Aug 08 07:51:35 PM PDT 24
Peak memory 249604 kb
Host smart-4c50f8fc-2b9f-41ac-8616-a7ea118b6994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759394279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1759394279
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.121042222
Short name T4
Test name
Test status
Simulation time 6790069242 ps
CPU time 58.38 seconds
Started Aug 08 07:46:18 PM PDT 24
Finished Aug 08 07:47:16 PM PDT 24
Peak memory 251592 kb
Host smart-3a154ad4-d8ae-4a21-8128-dab2d4a9a1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121042222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.121042222
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2470635768
Short name T14
Test name
Test status
Simulation time 2886480193 ps
CPU time 9.73 seconds
Started Aug 08 07:48:59 PM PDT 24
Finished Aug 08 07:49:09 PM PDT 24
Peak memory 225016 kb
Host smart-441fc9f2-e07d-4d64-b764-5a6f75bc69b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470635768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2470635768
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1533287790
Short name T34
Test name
Test status
Simulation time 28105383782 ps
CPU time 246.39 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:50:28 PM PDT 24
Peak memory 266748 kb
Host smart-e510c794-6711-4620-98b1-5c8fb2510d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533287790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1533287790
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2275212096
Short name T90
Test name
Test status
Simulation time 847010948 ps
CPU time 5.17 seconds
Started Aug 08 07:42:37 PM PDT 24
Finished Aug 08 07:42:42 PM PDT 24
Peak memory 215396 kb
Host smart-cd080b86-f726-4596-8723-9c534b48bc79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275212096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
275212096
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1279303421
Short name T783
Test name
Test status
Simulation time 62774986480 ps
CPU time 587.91 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:58:25 PM PDT 24
Peak memory 257700 kb
Host smart-18ca7c51-d484-45ba-bdc4-0b2a50fe1438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279303421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1279303421
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.724790703
Short name T159
Test name
Test status
Simulation time 6442425185 ps
CPU time 88.23 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:48:07 PM PDT 24
Peak memory 249700 kb
Host smart-d61e061c-76d9-4577-8fe8-99a30f6c58d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724790703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.724790703
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2324107523
Short name T209
Test name
Test status
Simulation time 26357620301 ps
CPU time 108.08 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:49:41 PM PDT 24
Peak memory 256308 kb
Host smart-a84f51bc-51ce-4d28-879a-e4547978a09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324107523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2324107523
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.18011852
Short name T26
Test name
Test status
Simulation time 205855424784 ps
CPU time 494.45 seconds
Started Aug 08 07:49:01 PM PDT 24
Finished Aug 08 07:57:15 PM PDT 24
Peak memory 253284 kb
Host smart-e315273b-06e0-4ed5-a528-b55f0ed4b637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18011852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress
_all.18011852
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2718998279
Short name T240
Test name
Test status
Simulation time 657114269 ps
CPU time 14.98 seconds
Started Aug 08 07:42:56 PM PDT 24
Finished Aug 08 07:43:12 PM PDT 24
Peak memory 215248 kb
Host smart-54d80dbb-f983-496e-8ee4-922744a97bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718998279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2718998279
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3800173298
Short name T151
Test name
Test status
Simulation time 300143871474 ps
CPU time 767.53 seconds
Started Aug 08 07:46:32 PM PDT 24
Finished Aug 08 07:59:19 PM PDT 24
Peak memory 257848 kb
Host smart-5f4f1719-59c6-463b-b6f7-51223154dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800173298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3800173298
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3669789938
Short name T402
Test name
Test status
Simulation time 6069614689 ps
CPU time 34.81 seconds
Started Aug 08 07:46:57 PM PDT 24
Finished Aug 08 07:47:32 PM PDT 24
Peak memory 241436 kb
Host smart-967076e8-1c38-4815-b1cd-97f86ce6ad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669789938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3669789938
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3834810301
Short name T131
Test name
Test status
Simulation time 815651505 ps
CPU time 8.24 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:47:16 PM PDT 24
Peak memory 233224 kb
Host smart-e8bb4b8f-b408-474a-bd3e-74cbd9a8479f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834810301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3834810301
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.163995842
Short name T221
Test name
Test status
Simulation time 108025887990 ps
CPU time 253.86 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:52:07 PM PDT 24
Peak memory 257208 kb
Host smart-cb5c3999-6516-47e5-9346-95d4ab0a7f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163995842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.163995842
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2020482391
Short name T10
Test name
Test status
Simulation time 300969038 ps
CPU time 2.14 seconds
Started Aug 08 07:47:34 PM PDT 24
Finished Aug 08 07:47:37 PM PDT 24
Peak memory 224840 kb
Host smart-24d22763-8022-488d-ad02-92a2c39850e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020482391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2020482391
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.409921943
Short name T1067
Test name
Test status
Simulation time 216958289 ps
CPU time 4.88 seconds
Started Aug 08 07:42:56 PM PDT 24
Finished Aug 08 07:43:01 PM PDT 24
Peak memory 216352 kb
Host smart-03bc8dbc-5d4c-4dd9-8252-2fe06d3d7021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409921943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.409921943
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4044350717
Short name T31
Test name
Test status
Simulation time 807366676 ps
CPU time 5.67 seconds
Started Aug 08 07:49:19 PM PDT 24
Finished Aug 08 07:49:25 PM PDT 24
Peak memory 224952 kb
Host smart-df18bb70-ce31-4975-8dc8-2859d51d43e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044350717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4044350717
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.477763418
Short name T249
Test name
Test status
Simulation time 27506648222 ps
CPU time 274.02 seconds
Started Aug 08 07:46:43 PM PDT 24
Finished Aug 08 07:51:17 PM PDT 24
Peak memory 257752 kb
Host smart-fafff4ce-3aad-4d58-927a-27f0114886e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477763418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.477763418
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3605638875
Short name T294
Test name
Test status
Simulation time 217281968 ps
CPU time 6.3 seconds
Started Aug 08 07:46:38 PM PDT 24
Finished Aug 08 07:46:45 PM PDT 24
Peak memory 224936 kb
Host smart-b963aeb1-5762-4e5e-8467-b2c5704ab2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605638875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3605638875
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1420852466
Short name T189
Test name
Test status
Simulation time 1489879881 ps
CPU time 12.71 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:47:03 PM PDT 24
Peak memory 233112 kb
Host smart-83134a41-d960-4a7b-b8e1-026bc3f35b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420852466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1420852466
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3281592070
Short name T235
Test name
Test status
Simulation time 385788265175 ps
CPU time 903.37 seconds
Started Aug 08 07:46:51 PM PDT 24
Finished Aug 08 08:01:55 PM PDT 24
Peak memory 302380 kb
Host smart-c6ada1a6-a9fd-4afe-abc7-c463f3cc2576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281592070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3281592070
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2440966158
Short name T308
Test name
Test status
Simulation time 4562171501 ps
CPU time 26.83 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:32 PM PDT 24
Peak memory 216800 kb
Host smart-0357ebff-a83a-4eb1-8f9a-0c8c5d161ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440966158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2440966158
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4220262542
Short name T229
Test name
Test status
Simulation time 7375281687 ps
CPU time 109.58 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:49:34 PM PDT 24
Peak memory 257868 kb
Host smart-e629f975-66c9-4c79-89cc-e6085682ff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220262542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4220262542
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2211743231
Short name T220
Test name
Test status
Simulation time 27686546946 ps
CPU time 209.24 seconds
Started Aug 08 07:46:18 PM PDT 24
Finished Aug 08 07:49:47 PM PDT 24
Peak memory 257816 kb
Host smart-9252bf80-0811-44f5-b568-caa38c19735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211743231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2211743231
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3697864538
Short name T70
Test name
Test status
Simulation time 137628954 ps
CPU time 1.46 seconds
Started Aug 08 07:42:32 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 207148 kb
Host smart-eb482343-1918-450f-b632-617f2687b6f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697864538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3697864538
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3456396860
Short name T136
Test name
Test status
Simulation time 4557228512 ps
CPU time 22.85 seconds
Started Aug 08 07:42:20 PM PDT 24
Finished Aug 08 07:42:43 PM PDT 24
Peak memory 215244 kb
Host smart-7ee3738c-4561-486f-9d03-618184d1e51b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456396860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3456396860
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3890502742
Short name T1063
Test name
Test status
Simulation time 1010007557 ps
CPU time 13.05 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:36 PM PDT 24
Peak memory 215228 kb
Host smart-dcac35cb-5d6e-4b9d-8a26-5c52d0376d5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890502742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3890502742
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2270442874
Short name T104
Test name
Test status
Simulation time 219116230 ps
CPU time 0.99 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:24 PM PDT 24
Peak memory 206792 kb
Host smart-811da9cc-def1-45be-a305-0830cb920931
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270442874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2270442874
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3151661672
Short name T95
Test name
Test status
Simulation time 28207446 ps
CPU time 1.71 seconds
Started Aug 08 07:42:22 PM PDT 24
Finished Aug 08 07:42:24 PM PDT 24
Peak memory 215388 kb
Host smart-74299594-f79e-4826-899b-2bc3b41d49d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151661672 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3151661672
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4148031880
Short name T1016
Test name
Test status
Simulation time 34062011 ps
CPU time 1.3 seconds
Started Aug 08 07:42:21 PM PDT 24
Finished Aug 08 07:42:23 PM PDT 24
Peak memory 206944 kb
Host smart-432ff14a-f08b-4cfa-b199-7f1ea3ca7995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148031880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
148031880
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1760836421
Short name T1118
Test name
Test status
Simulation time 32356581 ps
CPU time 0.76 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:24 PM PDT 24
Peak memory 203696 kb
Host smart-f27a0046-dcfe-4a9b-89c3-202a2b306cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760836421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
760836421
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3009875548
Short name T103
Test name
Test status
Simulation time 72178547 ps
CPU time 1.28 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:25 PM PDT 24
Peak memory 215112 kb
Host smart-536147ff-413f-44b1-88e2-484e4ce8a1b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009875548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3009875548
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.221054678
Short name T1010
Test name
Test status
Simulation time 30065476 ps
CPU time 0.64 seconds
Started Aug 08 07:42:21 PM PDT 24
Finished Aug 08 07:42:22 PM PDT 24
Peak memory 203640 kb
Host smart-863a0502-3c89-49d9-a277-aa41cea77b5f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221054678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.221054678
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1916143235
Short name T1061
Test name
Test status
Simulation time 205693327 ps
CPU time 1.64 seconds
Started Aug 08 07:42:22 PM PDT 24
Finished Aug 08 07:42:24 PM PDT 24
Peak memory 206892 kb
Host smart-767a78d9-0927-4be3-8eb9-0561ef2ca8f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916143235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1916143235
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3018328299
Short name T1114
Test name
Test status
Simulation time 198756920 ps
CPU time 2.41 seconds
Started Aug 08 07:42:21 PM PDT 24
Finished Aug 08 07:42:24 PM PDT 24
Peak memory 215284 kb
Host smart-804cdefb-4373-4161-8fae-dea32a3e27f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018328299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
018328299
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.426008976
Short name T1064
Test name
Test status
Simulation time 3224582878 ps
CPU time 19.78 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:43 PM PDT 24
Peak memory 215320 kb
Host smart-73973ebb-6ce6-433e-801e-762b60f81fad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426008976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.426008976
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3673689470
Short name T99
Test name
Test status
Simulation time 911485787 ps
CPU time 23.22 seconds
Started Aug 08 07:42:24 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 215284 kb
Host smart-9d7c7d32-f314-48ad-982b-f121a51186d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673689470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3673689470
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.44697861
Short name T1026
Test name
Test status
Simulation time 7528687254 ps
CPU time 34.35 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:58 PM PDT 24
Peak memory 207032 kb
Host smart-ed31c977-2b59-453e-94d3-4e2ba9d6e4b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44697861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
bit_bash.44697861
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.980479538
Short name T1109
Test name
Test status
Simulation time 97479040 ps
CPU time 2.94 seconds
Started Aug 08 07:42:21 PM PDT 24
Finished Aug 08 07:42:24 PM PDT 24
Peak memory 218500 kb
Host smart-5a9a4f85-74dc-485f-8b31-3d11feaf62a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980479538 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.980479538
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1738837861
Short name T1052
Test name
Test status
Simulation time 148412940 ps
CPU time 2.42 seconds
Started Aug 08 07:42:24 PM PDT 24
Finished Aug 08 07:42:27 PM PDT 24
Peak memory 206924 kb
Host smart-b3ded8ea-5b6a-4949-b9e0-07ecea5d6472
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738837861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
738837861
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4122180575
Short name T1030
Test name
Test status
Simulation time 18726874 ps
CPU time 0.78 seconds
Started Aug 08 07:42:22 PM PDT 24
Finished Aug 08 07:42:23 PM PDT 24
Peak memory 203556 kb
Host smart-b56232ef-d69b-4c27-9f6c-91e57e0e6827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122180575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
122180575
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1438458406
Short name T98
Test name
Test status
Simulation time 22940687 ps
CPU time 1.7 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:25 PM PDT 24
Peak memory 215152 kb
Host smart-3e79918c-cb6b-46d6-9e0a-fdecdb06e43d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438458406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1438458406
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2740819841
Short name T1056
Test name
Test status
Simulation time 20805985 ps
CPU time 0.67 seconds
Started Aug 08 07:42:21 PM PDT 24
Finished Aug 08 07:42:23 PM PDT 24
Peak memory 203648 kb
Host smart-b3a82d38-9cef-4ebc-b30a-404d850006d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740819841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2740819841
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2552809224
Short name T1053
Test name
Test status
Simulation time 398930048 ps
CPU time 2.13 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:25 PM PDT 24
Peak memory 215152 kb
Host smart-927da0d6-c338-427f-a1c4-bc60e00ea346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552809224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2552809224
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1443546694
Short name T1096
Test name
Test status
Simulation time 87077426 ps
CPU time 2.26 seconds
Started Aug 08 07:42:21 PM PDT 24
Finished Aug 08 07:42:23 PM PDT 24
Peak memory 216408 kb
Host smart-88b05424-790f-44cb-b687-34f95e6c4ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443546694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
443546694
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1082882795
Short name T1108
Test name
Test status
Simulation time 466258696 ps
CPU time 6.68 seconds
Started Aug 08 07:42:20 PM PDT 24
Finished Aug 08 07:42:27 PM PDT 24
Peak memory 215224 kb
Host smart-ebab3732-8e7a-47e5-89e4-13b25d630a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082882795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1082882795
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4164579149
Short name T141
Test name
Test status
Simulation time 289294468 ps
CPU time 3.86 seconds
Started Aug 08 07:42:43 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 217708 kb
Host smart-f58ab693-dd87-47ff-b95d-99f794ef15fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164579149 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4164579149
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.888485351
Short name T1047
Test name
Test status
Simulation time 256439914 ps
CPU time 1.94 seconds
Started Aug 08 07:42:45 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 215180 kb
Host smart-711e1be1-883a-47f3-9401-9186a94e9c3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888485351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.888485351
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1032999401
Short name T1011
Test name
Test status
Simulation time 19826247 ps
CPU time 0.7 seconds
Started Aug 08 07:42:42 PM PDT 24
Finished Aug 08 07:42:43 PM PDT 24
Peak memory 203928 kb
Host smart-cef52ea3-a647-475a-b65e-5cee7bc0f21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032999401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1032999401
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.49540212
Short name T1117
Test name
Test status
Simulation time 62579342 ps
CPU time 1.99 seconds
Started Aug 08 07:42:43 PM PDT 24
Finished Aug 08 07:42:45 PM PDT 24
Peak memory 215236 kb
Host smart-4b289335-8424-4726-a08c-d488cfea87a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49540212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sp
i_device_same_csr_outstanding.49540212
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1281702616
Short name T88
Test name
Test status
Simulation time 428150350 ps
CPU time 3.02 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:36 PM PDT 24
Peak memory 216396 kb
Host smart-da19bbfb-1060-4407-9f7c-2d9ffa6d0dae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281702616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1281702616
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1585126635
Short name T1103
Test name
Test status
Simulation time 2445063964 ps
CPU time 3.64 seconds
Started Aug 08 07:42:43 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 216348 kb
Host smart-9e1731c5-abb9-4003-9560-fd104363f1b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585126635 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1585126635
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1917546312
Short name T1088
Test name
Test status
Simulation time 759737594 ps
CPU time 2.43 seconds
Started Aug 08 07:42:45 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 214992 kb
Host smart-34632a92-c416-48a4-b078-49c761cb0d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917546312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1917546312
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1571017410
Short name T1031
Test name
Test status
Simulation time 21097959 ps
CPU time 0.76 seconds
Started Aug 08 07:42:47 PM PDT 24
Finished Aug 08 07:42:48 PM PDT 24
Peak memory 203980 kb
Host smart-7fec0bb8-d044-440a-a4e5-3c0e9b083d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571017410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1571017410
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.286096549
Short name T1125
Test name
Test status
Simulation time 155282333 ps
CPU time 3.84 seconds
Started Aug 08 07:42:44 PM PDT 24
Finished Aug 08 07:42:48 PM PDT 24
Peak memory 215124 kb
Host smart-6d4dc14e-8ead-4512-ac43-9f8f056a7f65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286096549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.286096549
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1808427961
Short name T89
Test name
Test status
Simulation time 329097962 ps
CPU time 4.1 seconds
Started Aug 08 07:42:48 PM PDT 24
Finished Aug 08 07:42:52 PM PDT 24
Peak memory 215400 kb
Host smart-163e40e5-044b-49f8-99c8-37c6809c0194
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808427961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1808427961
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3528700597
Short name T244
Test name
Test status
Simulation time 343967431 ps
CPU time 16.46 seconds
Started Aug 08 07:42:45 PM PDT 24
Finished Aug 08 07:43:01 PM PDT 24
Peak memory 215056 kb
Host smart-6509c4e3-554a-461b-9257-19c39458555d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528700597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3528700597
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4065389883
Short name T1104
Test name
Test status
Simulation time 78302052 ps
CPU time 2.72 seconds
Started Aug 08 07:42:47 PM PDT 24
Finished Aug 08 07:42:50 PM PDT 24
Peak memory 218132 kb
Host smart-003475d5-359d-4dc2-9ae7-5daa5c8b63ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065389883 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4065389883
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4121021961
Short name T106
Test name
Test status
Simulation time 139283696 ps
CPU time 2.35 seconds
Started Aug 08 07:42:45 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 215248 kb
Host smart-c92f2610-48ff-4fe2-9ae5-84b59f17809d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121021961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4121021961
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.623924554
Short name T1014
Test name
Test status
Simulation time 26255246 ps
CPU time 0.73 seconds
Started Aug 08 07:42:44 PM PDT 24
Finished Aug 08 07:42:44 PM PDT 24
Peak memory 203736 kb
Host smart-63b82125-d108-4990-a15f-b9b60d8136a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623924554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.623924554
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1866248837
Short name T1037
Test name
Test status
Simulation time 333892171 ps
CPU time 4.23 seconds
Started Aug 08 07:42:41 PM PDT 24
Finished Aug 08 07:42:46 PM PDT 24
Peak memory 215208 kb
Host smart-22aef604-9763-40d9-98ac-74a3ef97d7c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866248837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1866248837
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3034616401
Short name T237
Test name
Test status
Simulation time 1055298132 ps
CPU time 4.47 seconds
Started Aug 08 07:42:43 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 216240 kb
Host smart-195c4a9e-ee2e-41a0-b00d-029666ff21d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034616401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3034616401
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.335013458
Short name T1126
Test name
Test status
Simulation time 820818109 ps
CPU time 22.62 seconds
Started Aug 08 07:42:45 PM PDT 24
Finished Aug 08 07:43:08 PM PDT 24
Peak memory 215288 kb
Host smart-9f099117-b11e-49b7-9632-a4ad040b02ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335013458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.335013458
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1632484585
Short name T1095
Test name
Test status
Simulation time 85769502 ps
CPU time 1.71 seconds
Started Aug 08 07:42:48 PM PDT 24
Finished Aug 08 07:42:50 PM PDT 24
Peak memory 215212 kb
Host smart-13a0058a-e3f7-4478-82de-78d83ea5225b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632484585 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1632484585
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3679182997
Short name T101
Test name
Test status
Simulation time 380966716 ps
CPU time 2.57 seconds
Started Aug 08 07:42:42 PM PDT 24
Finished Aug 08 07:42:44 PM PDT 24
Peak memory 215248 kb
Host smart-7401b675-0bdb-45f1-971d-b57bb8428bae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679182997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3679182997
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2390878196
Short name T1035
Test name
Test status
Simulation time 15627992 ps
CPU time 0.75 seconds
Started Aug 08 07:42:42 PM PDT 24
Finished Aug 08 07:42:43 PM PDT 24
Peak memory 203668 kb
Host smart-69a45cbb-9e24-4d81-aeb9-62bc608e25d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390878196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2390878196
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.821005382
Short name T126
Test name
Test status
Simulation time 1062059389 ps
CPU time 4.02 seconds
Started Aug 08 07:42:42 PM PDT 24
Finished Aug 08 07:42:46 PM PDT 24
Peak memory 215272 kb
Host smart-97a767bf-f484-4a59-9feb-da0f9ee5cb9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821005382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.821005382
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3500411599
Short name T94
Test name
Test status
Simulation time 351543805 ps
CPU time 2.41 seconds
Started Aug 08 07:42:45 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 215268 kb
Host smart-8154c090-d8bf-44b1-855e-948bdb3d99fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500411599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3500411599
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2301787460
Short name T51
Test name
Test status
Simulation time 188376222 ps
CPU time 11.62 seconds
Started Aug 08 07:42:43 PM PDT 24
Finished Aug 08 07:42:54 PM PDT 24
Peak memory 215248 kb
Host smart-de539bde-3f83-4c90-af40-e8f3c890c183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301787460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2301787460
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3289704959
Short name T1111
Test name
Test status
Simulation time 60363119 ps
CPU time 1.67 seconds
Started Aug 08 07:42:45 PM PDT 24
Finished Aug 08 07:42:46 PM PDT 24
Peak memory 216388 kb
Host smart-15cf8ff0-439c-4db7-b993-f77da4062093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289704959 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3289704959
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1934790876
Short name T1017
Test name
Test status
Simulation time 99295151 ps
CPU time 2.85 seconds
Started Aug 08 07:42:44 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 215196 kb
Host smart-8954e126-63f5-444a-9a6c-2166586d89d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934790876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1934790876
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2554053442
Short name T1100
Test name
Test status
Simulation time 46269967 ps
CPU time 0.73 seconds
Started Aug 08 07:42:45 PM PDT 24
Finished Aug 08 07:42:45 PM PDT 24
Peak memory 203724 kb
Host smart-09a1f4fb-0018-40c0-85d1-46b190810a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554053442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2554053442
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2377741787
Short name T139
Test name
Test status
Simulation time 709218113 ps
CPU time 4.05 seconds
Started Aug 08 07:42:44 PM PDT 24
Finished Aug 08 07:42:48 PM PDT 24
Peak memory 215232 kb
Host smart-b812552f-e4b3-46a6-8515-7cc5bdb7889c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377741787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2377741787
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.508790211
Short name T84
Test name
Test status
Simulation time 334126718 ps
CPU time 2.87 seconds
Started Aug 08 07:42:45 PM PDT 24
Finished Aug 08 07:42:48 PM PDT 24
Peak memory 215296 kb
Host smart-b334af66-fd89-4032-8f43-5ade57ead8b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508790211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.508790211
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3834615375
Short name T1098
Test name
Test status
Simulation time 492970234 ps
CPU time 3.86 seconds
Started Aug 08 07:42:43 PM PDT 24
Finished Aug 08 07:42:47 PM PDT 24
Peak memory 217988 kb
Host smart-ce5c9316-2e3a-40db-8d8a-ceb346710da7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834615375 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3834615375
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4199198459
Short name T1093
Test name
Test status
Simulation time 169868748 ps
CPU time 1.34 seconds
Started Aug 08 07:42:40 PM PDT 24
Finished Aug 08 07:42:42 PM PDT 24
Peak memory 219676 kb
Host smart-1c84f631-9f21-471e-b0d1-8d293c1cd65f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199198459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4199198459
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2487745913
Short name T1062
Test name
Test status
Simulation time 17819227 ps
CPU time 0.75 seconds
Started Aug 08 07:42:42 PM PDT 24
Finished Aug 08 07:42:43 PM PDT 24
Peak memory 203664 kb
Host smart-f531c4b9-7a40-4378-818f-f0f33f004a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487745913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2487745913
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2973074372
Short name T1048
Test name
Test status
Simulation time 63908866 ps
CPU time 3.89 seconds
Started Aug 08 07:42:47 PM PDT 24
Finished Aug 08 07:42:51 PM PDT 24
Peak memory 215196 kb
Host smart-a1f643f6-3fb0-4c60-8c0b-b7b689a7dbdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973074372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2973074372
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2595166330
Short name T1127
Test name
Test status
Simulation time 65201783 ps
CPU time 4.09 seconds
Started Aug 08 07:42:44 PM PDT 24
Finished Aug 08 07:42:48 PM PDT 24
Peak memory 216408 kb
Host smart-9832990d-a665-4abc-b166-bec694458b17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595166330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2595166330
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1521660643
Short name T241
Test name
Test status
Simulation time 4336163025 ps
CPU time 7.17 seconds
Started Aug 08 07:42:42 PM PDT 24
Finished Aug 08 07:42:50 PM PDT 24
Peak memory 215356 kb
Host smart-ea624c20-8efd-470c-abe4-9976b09e8d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521660643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1521660643
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.480274602
Short name T1081
Test name
Test status
Simulation time 355157348 ps
CPU time 2.42 seconds
Started Aug 08 07:42:55 PM PDT 24
Finished Aug 08 07:42:57 PM PDT 24
Peak memory 216336 kb
Host smart-35b5cfc5-c1c9-4292-9339-b3e93e3b608a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480274602 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.480274602
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3842058755
Short name T1120
Test name
Test status
Simulation time 215716347 ps
CPU time 2.61 seconds
Started Aug 08 07:42:56 PM PDT 24
Finished Aug 08 07:42:59 PM PDT 24
Peak memory 215152 kb
Host smart-a77f0578-a200-4673-aee5-26f900809b02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842058755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3842058755
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3453834760
Short name T1057
Test name
Test status
Simulation time 13621941 ps
CPU time 0.72 seconds
Started Aug 08 07:42:48 PM PDT 24
Finished Aug 08 07:42:49 PM PDT 24
Peak memory 203988 kb
Host smart-545a7e7c-8071-4456-956d-4ee5a7e76cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453834760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3453834760
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2409683260
Short name T1089
Test name
Test status
Simulation time 411805009 ps
CPU time 2.96 seconds
Started Aug 08 07:42:53 PM PDT 24
Finished Aug 08 07:42:56 PM PDT 24
Peak memory 206972 kb
Host smart-ccf08768-cab6-470b-a445-798068cce704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409683260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2409683260
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.211504497
Short name T1128
Test name
Test status
Simulation time 794350631 ps
CPU time 3.79 seconds
Started Aug 08 07:42:46 PM PDT 24
Finished Aug 08 07:42:49 PM PDT 24
Peak memory 216384 kb
Host smart-733de7d1-1b04-42a4-b279-4aa90a072526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211504497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.211504497
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1066026488
Short name T1036
Test name
Test status
Simulation time 1440849624 ps
CPU time 8.17 seconds
Started Aug 08 07:42:44 PM PDT 24
Finished Aug 08 07:42:52 PM PDT 24
Peak memory 215672 kb
Host smart-6db60d3a-4719-4173-90b0-b05fae1e8b17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066026488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1066026488
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.123317723
Short name T1101
Test name
Test status
Simulation time 142837950 ps
CPU time 1.68 seconds
Started Aug 08 07:42:57 PM PDT 24
Finished Aug 08 07:42:59 PM PDT 24
Peak memory 215248 kb
Host smart-a4a7304a-eb1e-4b2d-82a8-1290696d6adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123317723 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.123317723
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1234808121
Short name T1055
Test name
Test status
Simulation time 130507798 ps
CPU time 1.37 seconds
Started Aug 08 07:43:00 PM PDT 24
Finished Aug 08 07:43:02 PM PDT 24
Peak memory 215120 kb
Host smart-f908256e-dee0-417d-bbdc-4021e8e8da0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234808121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1234808121
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2205475576
Short name T1124
Test name
Test status
Simulation time 32488840 ps
CPU time 0.72 seconds
Started Aug 08 07:42:56 PM PDT 24
Finished Aug 08 07:42:57 PM PDT 24
Peak memory 203660 kb
Host smart-c8eddaa2-783a-4295-b213-fbfa05889b24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205475576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2205475576
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1096235508
Short name T1086
Test name
Test status
Simulation time 1097953346 ps
CPU time 2.87 seconds
Started Aug 08 07:42:56 PM PDT 24
Finished Aug 08 07:42:59 PM PDT 24
Peak memory 215224 kb
Host smart-8d9bbd65-3a3b-4c08-84f1-c8e601abc04c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096235508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1096235508
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2387114476
Short name T50
Test name
Test status
Simulation time 125487122 ps
CPU time 2.09 seconds
Started Aug 08 07:42:51 PM PDT 24
Finished Aug 08 07:42:54 PM PDT 24
Peak memory 215300 kb
Host smart-60a54929-ae72-4a05-8407-cd99534c52b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387114476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2387114476
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2719838777
Short name T242
Test name
Test status
Simulation time 1903000743 ps
CPU time 20.37 seconds
Started Aug 08 07:42:58 PM PDT 24
Finished Aug 08 07:43:19 PM PDT 24
Peak memory 215292 kb
Host smart-891580aa-a89a-45bf-9a5a-e59fa51ab78d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719838777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2719838777
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.737883955
Short name T1092
Test name
Test status
Simulation time 149727010 ps
CPU time 2.73 seconds
Started Aug 08 07:42:56 PM PDT 24
Finished Aug 08 07:42:59 PM PDT 24
Peak memory 216240 kb
Host smart-addabf8f-16ac-4ab1-8587-03fc4c6f3b1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737883955 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.737883955
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.510003370
Short name T140
Test name
Test status
Simulation time 198519881 ps
CPU time 1.35 seconds
Started Aug 08 07:42:58 PM PDT 24
Finished Aug 08 07:43:00 PM PDT 24
Peak memory 215220 kb
Host smart-37380b9e-f86e-4e9c-9d5d-cf21ebe2eb3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510003370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.510003370
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2525720374
Short name T1075
Test name
Test status
Simulation time 16621754 ps
CPU time 0.71 seconds
Started Aug 08 07:43:00 PM PDT 24
Finished Aug 08 07:43:01 PM PDT 24
Peak memory 203916 kb
Host smart-bc956f00-d5a0-4a12-8241-d759e079aef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525720374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2525720374
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3770212267
Short name T1129
Test name
Test status
Simulation time 131203553 ps
CPU time 1.87 seconds
Started Aug 08 07:42:55 PM PDT 24
Finished Aug 08 07:42:57 PM PDT 24
Peak memory 215176 kb
Host smart-fe3a3bd6-ef55-4aab-ac50-97e23c5af108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770212267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3770212267
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2493261864
Short name T1078
Test name
Test status
Simulation time 39621942 ps
CPU time 2.5 seconds
Started Aug 08 07:42:55 PM PDT 24
Finished Aug 08 07:42:58 PM PDT 24
Peak memory 216788 kb
Host smart-98a659df-2deb-44c5-81e7-f15d977fe68c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493261864 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2493261864
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.457371111
Short name T1073
Test name
Test status
Simulation time 108850472 ps
CPU time 1.8 seconds
Started Aug 08 07:42:54 PM PDT 24
Finished Aug 08 07:42:55 PM PDT 24
Peak memory 215240 kb
Host smart-5a098e84-5a5e-437c-8e6c-02973ea147ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457371111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.457371111
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.947616471
Short name T1028
Test name
Test status
Simulation time 12854965 ps
CPU time 0.84 seconds
Started Aug 08 07:42:55 PM PDT 24
Finished Aug 08 07:42:56 PM PDT 24
Peak memory 204012 kb
Host smart-07939f61-c07c-4078-a960-aec528c83d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947616471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.947616471
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3267143301
Short name T1091
Test name
Test status
Simulation time 49610079 ps
CPU time 1.67 seconds
Started Aug 08 07:42:56 PM PDT 24
Finished Aug 08 07:42:57 PM PDT 24
Peak memory 215132 kb
Host smart-8c1e2728-d753-4fcf-9588-7151e3fd87c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267143301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3267143301
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2145133901
Short name T86
Test name
Test status
Simulation time 241004030 ps
CPU time 3.87 seconds
Started Aug 08 07:42:53 PM PDT 24
Finished Aug 08 07:42:57 PM PDT 24
Peak memory 215412 kb
Host smart-bc51b2a1-f227-43a0-a2ff-8eb517f1e355
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145133901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2145133901
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3371335986
Short name T1054
Test name
Test status
Simulation time 411825917 ps
CPU time 6.59 seconds
Started Aug 08 07:42:52 PM PDT 24
Finished Aug 08 07:42:59 PM PDT 24
Peak memory 215556 kb
Host smart-653853e6-fc6b-4163-9590-8b2bfe1fc0fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371335986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3371335986
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3932560879
Short name T1024
Test name
Test status
Simulation time 219563045 ps
CPU time 14.48 seconds
Started Aug 08 07:42:24 PM PDT 24
Finished Aug 08 07:42:39 PM PDT 24
Peak memory 215264 kb
Host smart-c74da7e6-4046-4039-ae37-645c5e6e7dd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932560879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3932560879
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3702535591
Short name T102
Test name
Test status
Simulation time 2169168760 ps
CPU time 35.68 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:59 PM PDT 24
Peak memory 207084 kb
Host smart-fba03537-c08a-4e96-b51e-db305bf90694
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702535591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3702535591
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3355511642
Short name T100
Test name
Test status
Simulation time 16398828 ps
CPU time 0.93 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:24 PM PDT 24
Peak memory 206748 kb
Host smart-09fcdc92-8a9e-4945-a94a-9a3d5fdef087
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355511642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3355511642
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3581461625
Short name T1112
Test name
Test status
Simulation time 781233643 ps
CPU time 1.59 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:25 PM PDT 24
Peak memory 215204 kb
Host smart-666be960-ff93-49f1-8558-cfe3f82ce96b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581461625 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3581461625
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.281094237
Short name T1038
Test name
Test status
Simulation time 25557359 ps
CPU time 1.26 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:25 PM PDT 24
Peak memory 207036 kb
Host smart-8f8954f5-3cd5-41c4-865a-120950c54f0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281094237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.281094237
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1402910000
Short name T1040
Test name
Test status
Simulation time 44282965 ps
CPU time 0.73 seconds
Started Aug 08 07:42:24 PM PDT 24
Finished Aug 08 07:42:25 PM PDT 24
Peak memory 203692 kb
Host smart-4279bbaa-ca0f-4e05-932e-46aa8d5a848d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402910000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
402910000
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3648460930
Short name T1059
Test name
Test status
Simulation time 211704277 ps
CPU time 1.57 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:25 PM PDT 24
Peak memory 215192 kb
Host smart-8c38421b-fd3e-4286-8942-41b708af5c1d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648460930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3648460930
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1040616474
Short name T1013
Test name
Test status
Simulation time 12829096 ps
CPU time 0.65 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:24 PM PDT 24
Peak memory 203648 kb
Host smart-dec0467c-88fa-4a38-a482-bf15972e97d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040616474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1040616474
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1996139111
Short name T1069
Test name
Test status
Simulation time 61965092 ps
CPU time 3.66 seconds
Started Aug 08 07:42:24 PM PDT 24
Finished Aug 08 07:42:28 PM PDT 24
Peak memory 215228 kb
Host smart-a85b750e-5422-48d6-83c6-a59ffc6d00e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996139111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1996139111
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1204786110
Short name T87
Test name
Test status
Simulation time 130944608 ps
CPU time 3.31 seconds
Started Aug 08 07:42:23 PM PDT 24
Finished Aug 08 07:42:26 PM PDT 24
Peak memory 215300 kb
Host smart-51ffd5b7-f34c-4483-85c6-6fc11b1d0c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204786110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
204786110
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2554567817
Short name T92
Test name
Test status
Simulation time 203813735 ps
CPU time 12.79 seconds
Started Aug 08 07:42:22 PM PDT 24
Finished Aug 08 07:42:35 PM PDT 24
Peak memory 215544 kb
Host smart-2523e72b-8f42-450e-8ee0-e50efe7ba84e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554567817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2554567817
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1519179177
Short name T1020
Test name
Test status
Simulation time 18170915 ps
CPU time 0.72 seconds
Started Aug 08 07:43:00 PM PDT 24
Finished Aug 08 07:43:00 PM PDT 24
Peak memory 203924 kb
Host smart-b74e62f0-f35a-45d1-8b31-174d68dd6d75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519179177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1519179177
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1607639043
Short name T1008
Test name
Test status
Simulation time 34839996 ps
CPU time 0.68 seconds
Started Aug 08 07:42:54 PM PDT 24
Finished Aug 08 07:42:54 PM PDT 24
Peak memory 203956 kb
Host smart-db7fb969-501f-4a0d-8a87-5e3c8441d437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607639043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1607639043
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3979225473
Short name T1044
Test name
Test status
Simulation time 16609479 ps
CPU time 0.74 seconds
Started Aug 08 07:42:56 PM PDT 24
Finished Aug 08 07:42:57 PM PDT 24
Peak memory 203972 kb
Host smart-96f8c375-7935-4cf7-83d8-1162e3f91b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979225473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3979225473
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1424122789
Short name T1043
Test name
Test status
Simulation time 25857577 ps
CPU time 0.74 seconds
Started Aug 08 07:42:55 PM PDT 24
Finished Aug 08 07:42:56 PM PDT 24
Peak memory 204172 kb
Host smart-65dc391b-147b-451e-9aad-dd1210aea12c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424122789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1424122789
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1791087353
Short name T1025
Test name
Test status
Simulation time 24452991 ps
CPU time 0.7 seconds
Started Aug 08 07:42:54 PM PDT 24
Finished Aug 08 07:42:55 PM PDT 24
Peak memory 203956 kb
Host smart-ea65b5e7-4a18-4b5a-a9d1-887765df544b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791087353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1791087353
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.507974438
Short name T1123
Test name
Test status
Simulation time 15030102 ps
CPU time 0.72 seconds
Started Aug 08 07:42:55 PM PDT 24
Finished Aug 08 07:42:56 PM PDT 24
Peak memory 203712 kb
Host smart-496ec4d8-da3b-4f82-9ccf-964741afc7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507974438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.507974438
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2036855559
Short name T1080
Test name
Test status
Simulation time 20139964 ps
CPU time 0.71 seconds
Started Aug 08 07:42:56 PM PDT 24
Finished Aug 08 07:42:56 PM PDT 24
Peak memory 203636 kb
Host smart-a6ede7bd-4208-44e0-9007-1b92e0a05903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036855559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2036855559
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4293883975
Short name T1019
Test name
Test status
Simulation time 22572979 ps
CPU time 0.71 seconds
Started Aug 08 07:42:54 PM PDT 24
Finished Aug 08 07:42:55 PM PDT 24
Peak memory 203664 kb
Host smart-1dd9ce04-5956-4e95-b8ef-357d6882f2ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293883975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4293883975
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1713122906
Short name T1046
Test name
Test status
Simulation time 21465301 ps
CPU time 0.69 seconds
Started Aug 08 07:42:54 PM PDT 24
Finished Aug 08 07:42:55 PM PDT 24
Peak memory 203704 kb
Host smart-48c075b4-dc1a-4be5-8ede-15bd09a9eb63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713122906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1713122906
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3219599104
Short name T1115
Test name
Test status
Simulation time 146747292 ps
CPU time 0.8 seconds
Started Aug 08 07:43:03 PM PDT 24
Finished Aug 08 07:43:04 PM PDT 24
Peak memory 203712 kb
Host smart-d1768c80-b73a-41a0-a8fd-65248eef7968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219599104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3219599104
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1003498315
Short name T1039
Test name
Test status
Simulation time 121584696 ps
CPU time 8.16 seconds
Started Aug 08 07:42:36 PM PDT 24
Finished Aug 08 07:42:44 PM PDT 24
Peak memory 206868 kb
Host smart-0d9493d3-a421-4496-98c9-6ba548c8b52a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003498315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1003498315
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3194364268
Short name T1033
Test name
Test status
Simulation time 3079023006 ps
CPU time 33.73 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:43:08 PM PDT 24
Peak memory 207008 kb
Host smart-af2048f8-8032-4f8b-a813-08489f43b409
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194364268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3194364268
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2094633225
Short name T1076
Test name
Test status
Simulation time 17568916 ps
CPU time 0.96 seconds
Started Aug 08 07:42:31 PM PDT 24
Finished Aug 08 07:42:32 PM PDT 24
Peak memory 206752 kb
Host smart-3abf8020-9fcb-4301-8d80-9dada6f6b2e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094633225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2094633225
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1072082479
Short name T1130
Test name
Test status
Simulation time 159061404 ps
CPU time 3.79 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:37 PM PDT 24
Peak memory 216740 kb
Host smart-0d25712d-ef8c-44e4-bbde-fab674c3693c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072082479 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1072082479
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.189263066
Short name T105
Test name
Test status
Simulation time 355826403 ps
CPU time 2.4 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:36 PM PDT 24
Peak memory 215244 kb
Host smart-d32d8e36-36e6-4a2f-a454-8b17a69310bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189263066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.189263066
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.352942916
Short name T1018
Test name
Test status
Simulation time 16626662 ps
CPU time 0.76 seconds
Started Aug 08 07:42:34 PM PDT 24
Finished Aug 08 07:42:35 PM PDT 24
Peak memory 203664 kb
Host smart-2b69ab6c-8013-478e-8eff-d467681337e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352942916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.352942916
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3839246126
Short name T110
Test name
Test status
Simulation time 53043126 ps
CPU time 1.99 seconds
Started Aug 08 07:42:35 PM PDT 24
Finished Aug 08 07:42:37 PM PDT 24
Peak memory 215140 kb
Host smart-462fa94b-15cd-4f5f-b09b-bceb21d3e865
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839246126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3839246126
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.850075177
Short name T1102
Test name
Test status
Simulation time 20039385 ps
CPU time 0.65 seconds
Started Aug 08 07:42:37 PM PDT 24
Finished Aug 08 07:42:38 PM PDT 24
Peak memory 203660 kb
Host smart-dfd1cdcf-49cf-47d7-81f7-63eca8e35cba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850075177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.850075177
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4141786282
Short name T1122
Test name
Test status
Simulation time 56468478 ps
CPU time 1.82 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:35 PM PDT 24
Peak memory 207004 kb
Host smart-c62950f5-880f-4ff9-a85e-26c48c79e124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141786282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4141786282
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.210242225
Short name T1107
Test name
Test status
Simulation time 102843770 ps
CPU time 3.46 seconds
Started Aug 08 07:42:22 PM PDT 24
Finished Aug 08 07:42:25 PM PDT 24
Peak memory 215256 kb
Host smart-e7d1c8f8-06bb-4869-b6ef-3662631822f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210242225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.210242225
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.690204389
Short name T1121
Test name
Test status
Simulation time 4218001520 ps
CPU time 8.31 seconds
Started Aug 08 07:42:20 PM PDT 24
Finished Aug 08 07:42:28 PM PDT 24
Peak memory 216392 kb
Host smart-3df6937a-4949-4642-a650-e6388eb66589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690204389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.690204389
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1535292789
Short name T1027
Test name
Test status
Simulation time 27704238 ps
CPU time 0.68 seconds
Started Aug 08 07:43:03 PM PDT 24
Finished Aug 08 07:43:04 PM PDT 24
Peak memory 203688 kb
Host smart-189dc40f-aaea-4d99-a02f-bb4985904c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535292789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1535292789
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.434265080
Short name T1032
Test name
Test status
Simulation time 21976486 ps
CPU time 0.74 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 203944 kb
Host smart-ecf402e1-7b4a-448c-ad10-19787143441e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434265080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.434265080
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2547483971
Short name T1106
Test name
Test status
Simulation time 29484204 ps
CPU time 0.7 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 203716 kb
Host smart-da48a903-d3d1-4c68-b1cb-76cf9239c960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547483971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2547483971
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1183230111
Short name T1050
Test name
Test status
Simulation time 37606504 ps
CPU time 0.69 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 203684 kb
Host smart-46ed915c-152e-4501-93be-acbfc9ecb9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183230111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1183230111
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3586204086
Short name T1085
Test name
Test status
Simulation time 54904900 ps
CPU time 0.7 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 203696 kb
Host smart-fed40123-e428-4afd-bf0d-61f3e3c6ff3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586204086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3586204086
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2949487020
Short name T1023
Test name
Test status
Simulation time 14368492 ps
CPU time 0.8 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 203664 kb
Host smart-4e32f521-09cf-4d3a-87f0-1505fbf4295e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949487020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2949487020
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2003369662
Short name T1009
Test name
Test status
Simulation time 33401155 ps
CPU time 0.69 seconds
Started Aug 08 07:43:06 PM PDT 24
Finished Aug 08 07:43:07 PM PDT 24
Peak memory 204036 kb
Host smart-3744e55f-c73d-4945-a3d1-d38a2cc638d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003369662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2003369662
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2717232688
Short name T1105
Test name
Test status
Simulation time 16942387 ps
CPU time 0.72 seconds
Started Aug 08 07:43:03 PM PDT 24
Finished Aug 08 07:43:04 PM PDT 24
Peak memory 203688 kb
Host smart-a6fb8c3c-5865-4024-bbe8-9bc788c7a095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717232688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2717232688
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1140619907
Short name T1097
Test name
Test status
Simulation time 47781965 ps
CPU time 0.71 seconds
Started Aug 08 07:43:01 PM PDT 24
Finished Aug 08 07:43:02 PM PDT 24
Peak memory 203680 kb
Host smart-98c2b3ac-a395-4315-9de2-71f2eaf125c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140619907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1140619907
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3748973730
Short name T1065
Test name
Test status
Simulation time 11697659 ps
CPU time 0.71 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 203644 kb
Host smart-2ec2f22c-44c0-4b52-a367-d633b3f359b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748973730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3748973730
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3534851369
Short name T1049
Test name
Test status
Simulation time 902035164 ps
CPU time 21.46 seconds
Started Aug 08 07:42:34 PM PDT 24
Finished Aug 08 07:42:56 PM PDT 24
Peak memory 216248 kb
Host smart-214c4d03-c053-42d0-b97f-651df1137974
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534851369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3534851369
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2138922808
Short name T107
Test name
Test status
Simulation time 4106195430 ps
CPU time 13.69 seconds
Started Aug 08 07:42:32 PM PDT 24
Finished Aug 08 07:42:46 PM PDT 24
Peak memory 215232 kb
Host smart-89ac6fca-bb25-422a-8474-91d5c2ebf99e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138922808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2138922808
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3463735724
Short name T1083
Test name
Test status
Simulation time 264622858 ps
CPU time 1.63 seconds
Started Aug 08 07:42:30 PM PDT 24
Finished Aug 08 07:42:32 PM PDT 24
Peak memory 216248 kb
Host smart-b340b390-7816-4516-a918-ab776640cef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463735724 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3463735724
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3545764093
Short name T138
Test name
Test status
Simulation time 149500583 ps
CPU time 1.24 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 207000 kb
Host smart-094e9376-cbe3-42cd-8ea9-7f767d987257
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545764093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
545764093
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1982564996
Short name T1012
Test name
Test status
Simulation time 13797786 ps
CPU time 0.73 seconds
Started Aug 08 07:42:34 PM PDT 24
Finished Aug 08 07:42:35 PM PDT 24
Peak memory 203684 kb
Host smart-8960f792-eb4d-4dec-92af-8c1b34ba650d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982564996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
982564996
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4025920529
Short name T1082
Test name
Test status
Simulation time 24705869 ps
CPU time 1.67 seconds
Started Aug 08 07:42:32 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 215168 kb
Host smart-e9d0380a-1b97-4d35-b2e8-660d807c79cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025920529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4025920529
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1210789371
Short name T1072
Test name
Test status
Simulation time 13204097 ps
CPU time 0.68 seconds
Started Aug 08 07:42:34 PM PDT 24
Finished Aug 08 07:42:35 PM PDT 24
Peak memory 203904 kb
Host smart-49d56e82-1e87-40cb-9357-c0c53173b35a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210789371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1210789371
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2271804286
Short name T1021
Test name
Test status
Simulation time 209565444 ps
CPU time 2.91 seconds
Started Aug 08 07:42:31 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 215152 kb
Host smart-fb4c2a5b-1cca-463e-b1d3-21c0844cbefc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271804286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2271804286
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1051633385
Short name T238
Test name
Test status
Simulation time 105857361 ps
CPU time 6.05 seconds
Started Aug 08 07:42:34 PM PDT 24
Finished Aug 08 07:42:40 PM PDT 24
Peak memory 215276 kb
Host smart-c2dddce0-2e6e-4844-978f-0814a48773e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051633385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1051633385
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3956670154
Short name T1029
Test name
Test status
Simulation time 60939758 ps
CPU time 0.72 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 204036 kb
Host smart-f6154df4-be8c-44f9-87e9-3e94320fb46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956670154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3956670154
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.977539619
Short name T1077
Test name
Test status
Simulation time 19963389 ps
CPU time 0.73 seconds
Started Aug 08 07:43:02 PM PDT 24
Finished Aug 08 07:43:02 PM PDT 24
Peak memory 203680 kb
Host smart-a1befc02-c42f-4285-9257-3ed6f87ee8ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977539619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.977539619
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4090262294
Short name T1045
Test name
Test status
Simulation time 16662255 ps
CPU time 0.73 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 203684 kb
Host smart-33270d1e-5663-4e59-bbde-83de4e5ad6fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090262294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4090262294
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2228839903
Short name T1119
Test name
Test status
Simulation time 59955143 ps
CPU time 0.78 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 203656 kb
Host smart-af75edde-d898-4bd1-a125-9d317b2df525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228839903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2228839903
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1479807416
Short name T1099
Test name
Test status
Simulation time 41222575 ps
CPU time 0.73 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 203700 kb
Host smart-8ee3bd02-49f4-4404-a827-4d789afd162f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479807416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1479807416
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2751721207
Short name T1034
Test name
Test status
Simulation time 19211604 ps
CPU time 0.79 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 203660 kb
Host smart-9f15292e-30b6-4f2f-876e-69059d644483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751721207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2751721207
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4154341425
Short name T1041
Test name
Test status
Simulation time 13567932 ps
CPU time 0.77 seconds
Started Aug 08 07:43:12 PM PDT 24
Finished Aug 08 07:43:13 PM PDT 24
Peak memory 203724 kb
Host smart-0447ad08-4566-4cc3-adab-0a1c66e3aeb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154341425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4154341425
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.86737794
Short name T1084
Test name
Test status
Simulation time 12025721 ps
CPU time 0.73 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 203624 kb
Host smart-143569a6-edc4-498c-a4e2-5836cfaff533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86737794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.86737794
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2010614400
Short name T1087
Test name
Test status
Simulation time 42361036 ps
CPU time 0.74 seconds
Started Aug 08 07:43:02 PM PDT 24
Finished Aug 08 07:43:03 PM PDT 24
Peak memory 203660 kb
Host smart-208d97e6-f6fc-49e0-952f-2e5bf264fb6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010614400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2010614400
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4253420348
Short name T1068
Test name
Test status
Simulation time 12164746 ps
CPU time 0.76 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 203976 kb
Host smart-74fbe781-2573-440c-a10a-d269583ed716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253420348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4253420348
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3024381554
Short name T97
Test name
Test status
Simulation time 147909214 ps
CPU time 3.61 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:37 PM PDT 24
Peak memory 217108 kb
Host smart-0950aa3a-4e5a-4b10-8de5-3304963c875a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024381554 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3024381554
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2494479976
Short name T108
Test name
Test status
Simulation time 146140787 ps
CPU time 2.44 seconds
Started Aug 08 07:42:30 PM PDT 24
Finished Aug 08 07:42:33 PM PDT 24
Peak memory 215144 kb
Host smart-ab6d0155-f53c-4dc4-bc1a-7429e748d77b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494479976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
494479976
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.683187346
Short name T1042
Test name
Test status
Simulation time 55012870 ps
CPU time 0.76 seconds
Started Aug 08 07:42:32 PM PDT 24
Finished Aug 08 07:42:33 PM PDT 24
Peak memory 203704 kb
Host smart-14468f50-4b60-43c0-93a6-ccf8fd6ed327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683187346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.683187346
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4284370596
Short name T1060
Test name
Test status
Simulation time 117177166 ps
CPU time 3.8 seconds
Started Aug 08 07:42:37 PM PDT 24
Finished Aug 08 07:42:40 PM PDT 24
Peak memory 216328 kb
Host smart-552cfef8-1af4-4d8f-aba0-4726176841e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284370596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4284370596
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3158023606
Short name T1070
Test name
Test status
Simulation time 23278394 ps
CPU time 1.66 seconds
Started Aug 08 07:42:34 PM PDT 24
Finished Aug 08 07:42:36 PM PDT 24
Peak memory 215292 kb
Host smart-4d37ecc4-9d55-4da3-9a2e-9765afcf8849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158023606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
158023606
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1509943096
Short name T82
Test name
Test status
Simulation time 548651748 ps
CPU time 15.06 seconds
Started Aug 08 07:42:39 PM PDT 24
Finished Aug 08 07:42:55 PM PDT 24
Peak memory 215936 kb
Host smart-d0e9dede-7184-4127-8d1d-774eeb0e0f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509943096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1509943096
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2132766978
Short name T93
Test name
Test status
Simulation time 142352514 ps
CPU time 3.52 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:37 PM PDT 24
Peak memory 216332 kb
Host smart-95b11968-f200-45c1-8818-ff243411d056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132766978 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2132766978
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2673351164
Short name T109
Test name
Test status
Simulation time 291578727 ps
CPU time 2.4 seconds
Started Aug 08 07:42:32 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 215172 kb
Host smart-674c23cb-18ae-4c35-8307-ebf35b93ccf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673351164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
673351164
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4140416791
Short name T1074
Test name
Test status
Simulation time 11109238 ps
CPU time 0.71 seconds
Started Aug 08 07:42:35 PM PDT 24
Finished Aug 08 07:42:35 PM PDT 24
Peak memory 203972 kb
Host smart-97fadca7-f2a3-4e25-9a40-2c964b9fcaa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140416791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
140416791
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2690402775
Short name T125
Test name
Test status
Simulation time 147203802 ps
CPU time 2.68 seconds
Started Aug 08 07:42:31 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 215104 kb
Host smart-978c4788-bad5-4d63-b74f-46cb5c778ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690402775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2690402775
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3470633887
Short name T1116
Test name
Test status
Simulation time 391331556 ps
CPU time 5.86 seconds
Started Aug 08 07:42:31 PM PDT 24
Finished Aug 08 07:42:37 PM PDT 24
Peak memory 215256 kb
Host smart-04ae77f2-3992-48c0-8a7b-1132ef136bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470633887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3470633887
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1150967554
Short name T124
Test name
Test status
Simulation time 31415717 ps
CPU time 1.16 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 215312 kb
Host smart-9de2c367-0f2e-40c7-8740-d86361eca87f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150967554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
150967554
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1945376099
Short name T1015
Test name
Test status
Simulation time 19743282 ps
CPU time 0.66 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 203704 kb
Host smart-26a33630-0b71-4f77-8db3-a10602a4485b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945376099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
945376099
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3874370941
Short name T1094
Test name
Test status
Simulation time 74775000 ps
CPU time 1.62 seconds
Started Aug 08 07:42:32 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 215216 kb
Host smart-793995b3-7d43-4a05-bf98-dda3a417c0ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874370941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3874370941
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3705232888
Short name T81
Test name
Test status
Simulation time 3243612942 ps
CPU time 4.53 seconds
Started Aug 08 07:42:34 PM PDT 24
Finished Aug 08 07:42:39 PM PDT 24
Peak memory 215316 kb
Host smart-76a6dd34-22e2-4f6a-af15-b8fb9293eadc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705232888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
705232888
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.757889592
Short name T243
Test name
Test status
Simulation time 1312878435 ps
CPU time 15.03 seconds
Started Aug 08 07:42:37 PM PDT 24
Finished Aug 08 07:42:52 PM PDT 24
Peak memory 215672 kb
Host smart-c73f91f7-9081-48ac-9054-8239c73224c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757889592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.757889592
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.915166663
Short name T1058
Test name
Test status
Simulation time 175174141 ps
CPU time 3.62 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:37 PM PDT 24
Peak memory 217484 kb
Host smart-f9ea5eb6-5c20-407b-9bdf-2b03f9f693fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915166663 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.915166663
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2704604667
Short name T137
Test name
Test status
Simulation time 272218334 ps
CPU time 1.4 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 207000 kb
Host smart-e5960e3c-5538-46b7-86bd-809d7b4010f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704604667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
704604667
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1977285766
Short name T1110
Test name
Test status
Simulation time 15438492 ps
CPU time 0.71 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:34 PM PDT 24
Peak memory 203944 kb
Host smart-41a81f26-33e0-45b5-a4c5-fce24128677c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977285766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
977285766
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3445487287
Short name T1022
Test name
Test status
Simulation time 225484831 ps
CPU time 1.81 seconds
Started Aug 08 07:42:33 PM PDT 24
Finished Aug 08 07:42:35 PM PDT 24
Peak memory 215136 kb
Host smart-7be8ce2e-3b65-4b3b-aebc-2e4ae47babd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445487287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3445487287
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.369620431
Short name T85
Test name
Test status
Simulation time 33070456 ps
CPU time 2.29 seconds
Started Aug 08 07:42:36 PM PDT 24
Finished Aug 08 07:42:38 PM PDT 24
Peak memory 215172 kb
Host smart-24f17a59-e155-436d-8570-3504f0dd5804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369620431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.369620431
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2495384382
Short name T1051
Test name
Test status
Simulation time 546022948 ps
CPU time 6.92 seconds
Started Aug 08 07:42:30 PM PDT 24
Finished Aug 08 07:42:37 PM PDT 24
Peak memory 215184 kb
Host smart-d7448424-8231-4ee0-b71b-68ad0c733731
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495384382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2495384382
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.405540489
Short name T1079
Test name
Test status
Simulation time 62995007 ps
CPU time 1.71 seconds
Started Aug 08 07:42:40 PM PDT 24
Finished Aug 08 07:42:42 PM PDT 24
Peak memory 215272 kb
Host smart-3a4ebf6d-2a32-432c-95b4-658c734a49ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405540489 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.405540489
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4253223488
Short name T1066
Test name
Test status
Simulation time 122372706 ps
CPU time 1.21 seconds
Started Aug 08 07:42:31 PM PDT 24
Finished Aug 08 07:42:32 PM PDT 24
Peak memory 215264 kb
Host smart-7b84094e-4816-40eb-86ef-bd13ca97a91e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253223488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
253223488
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4284365368
Short name T1090
Test name
Test status
Simulation time 27765366 ps
CPU time 0.71 seconds
Started Aug 08 07:42:35 PM PDT 24
Finished Aug 08 07:42:35 PM PDT 24
Peak memory 203720 kb
Host smart-7fbab6e9-c839-471d-a8d3-91eea769c34b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284365368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
284365368
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3116215089
Short name T1071
Test name
Test status
Simulation time 645018101 ps
CPU time 3.87 seconds
Started Aug 08 07:42:31 PM PDT 24
Finished Aug 08 07:42:35 PM PDT 24
Peak memory 215228 kb
Host smart-ccc92650-a795-451f-8c44-31e169541575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116215089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3116215089
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.941024754
Short name T91
Test name
Test status
Simulation time 2318318446 ps
CPU time 5.52 seconds
Started Aug 08 07:42:34 PM PDT 24
Finished Aug 08 07:42:40 PM PDT 24
Peak memory 215352 kb
Host smart-f6a36e5a-fc69-42a2-b484-212ed3f3e064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941024754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.941024754
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1259602263
Short name T1113
Test name
Test status
Simulation time 295725491 ps
CPU time 17.1 seconds
Started Aug 08 07:42:40 PM PDT 24
Finished Aug 08 07:42:57 PM PDT 24
Peak memory 215216 kb
Host smart-6cf4b509-4f38-4e5a-a25b-4d5e25679f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259602263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1259602263
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3955651768
Short name T415
Test name
Test status
Simulation time 58431121 ps
CPU time 0.72 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:46:06 PM PDT 24
Peak memory 205280 kb
Host smart-4828bb73-5b70-47f4-97fb-dc9cf8459b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955651768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
955651768
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3920666622
Short name T177
Test name
Test status
Simulation time 2138223987 ps
CPU time 5.08 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:46:11 PM PDT 24
Peak memory 224968 kb
Host smart-b0dee538-8ef4-44a5-a9df-85b5bf39e0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920666622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3920666622
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3954772876
Short name T455
Test name
Test status
Simulation time 36509097 ps
CPU time 0.77 seconds
Started Aug 08 07:45:56 PM PDT 24
Finished Aug 08 07:45:57 PM PDT 24
Peak memory 205880 kb
Host smart-836b9245-c60f-4b47-b411-e013b766741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954772876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3954772876
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2618393195
Short name T437
Test name
Test status
Simulation time 23518423512 ps
CPU time 87.13 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:47:28 PM PDT 24
Peak memory 235852 kb
Host smart-44bde8e9-425a-444a-a3b1-a563b03b31e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618393195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2618393195
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.280456183
Short name T442
Test name
Test status
Simulation time 81175279706 ps
CPU time 387.12 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:52:30 PM PDT 24
Peak memory 256480 kb
Host smart-728551e5-3330-472e-a041-7537ae3be03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280456183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.280456183
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.907799545
Short name T173
Test name
Test status
Simulation time 13232720909 ps
CPU time 63.06 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:47:04 PM PDT 24
Peak memory 241440 kb
Host smart-63767038-7af7-44e6-ad1c-a6638012bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907799545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
907799545
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2737405647
Short name T298
Test name
Test status
Simulation time 1218202700 ps
CPU time 20.8 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 233184 kb
Host smart-97ee4460-efa5-429c-b551-5c6125318dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737405647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2737405647
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3005168691
Short name T225
Test name
Test status
Simulation time 36898844930 ps
CPU time 199.04 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:49:22 PM PDT 24
Peak memory 256000 kb
Host smart-a52e4f00-f714-48b4-96e4-250a20d0fc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005168691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3005168691
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3682700424
Short name T388
Test name
Test status
Simulation time 280684489 ps
CPU time 2.2 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:46:03 PM PDT 24
Peak memory 224240 kb
Host smart-e98aef62-ccbe-40ca-b5bf-5be9b8b838af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682700424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3682700424
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1392334299
Short name T160
Test name
Test status
Simulation time 5863683150 ps
CPU time 14.43 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:16 PM PDT 24
Peak memory 224940 kb
Host smart-224b043f-a7e0-49f5-ab86-8582add27abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392334299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1392334299
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4211140511
Short name T700
Test name
Test status
Simulation time 4301884571 ps
CPU time 13.85 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:46:18 PM PDT 24
Peak memory 233352 kb
Host smart-243b4472-60b8-45bf-b948-10a9f382326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211140511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4211140511
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4173521694
Short name T194
Test name
Test status
Simulation time 6335758882 ps
CPU time 8.94 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:12 PM PDT 24
Peak memory 233200 kb
Host smart-76f10335-6ce7-450c-841c-5cf55e8e1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173521694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4173521694
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3937489581
Short name T953
Test name
Test status
Simulation time 228061440 ps
CPU time 5.44 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:46:07 PM PDT 24
Peak memory 219848 kb
Host smart-f9695747-50b4-41b2-9ea9-b189fa6e77a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3937489581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3937489581
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2353005189
Short name T17
Test name
Test status
Simulation time 119106068071 ps
CPU time 338.99 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:51:40 PM PDT 24
Peak memory 262872 kb
Host smart-da7f8c5b-d55b-46f9-b1d8-b3b80a851639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353005189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2353005189
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.246316723
Short name T651
Test name
Test status
Simulation time 256883346 ps
CPU time 3.96 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:46:09 PM PDT 24
Peak memory 216704 kb
Host smart-4c4abf30-8a23-4c53-b4a1-4fa33bcc9886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246316723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.246316723
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.426843723
Short name T836
Test name
Test status
Simulation time 3845143417 ps
CPU time 2.58 seconds
Started Aug 08 07:45:56 PM PDT 24
Finished Aug 08 07:45:59 PM PDT 24
Peak memory 216540 kb
Host smart-e1f15e0f-3435-492b-9182-7d56c0603136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426843723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.426843723
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3511279802
Short name T754
Test name
Test status
Simulation time 20607642 ps
CPU time 0.71 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:03 PM PDT 24
Peak memory 206056 kb
Host smart-439cd0c0-22f2-49be-a46f-7fa3a1d1e9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511279802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3511279802
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.700722040
Short name T867
Test name
Test status
Simulation time 262112185 ps
CPU time 0.9 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:46:02 PM PDT 24
Peak memory 206420 kb
Host smart-87b92597-dc03-436a-827f-6787ba2380f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700722040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.700722040
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1399820896
Short name T168
Test name
Test status
Simulation time 454816979 ps
CPU time 5.38 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:07 PM PDT 24
Peak memory 239620 kb
Host smart-f9c5ebeb-509d-4360-93b4-01479e125ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399820896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1399820896
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.973728152
Short name T688
Test name
Test status
Simulation time 23193578 ps
CPU time 0.73 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:03 PM PDT 24
Peak memory 205828 kb
Host smart-ed0cd2ae-27bd-4a7a-b584-29ff707684a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973728152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.973728152
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.741323976
Short name T500
Test name
Test status
Simulation time 1583629177 ps
CPU time 7.49 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:11 PM PDT 24
Peak memory 233144 kb
Host smart-dee2abf5-7db5-4b11-81a6-607f92590e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741323976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.741323976
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3151017220
Short name T440
Test name
Test status
Simulation time 33366803 ps
CPU time 0.74 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:04 PM PDT 24
Peak memory 206220 kb
Host smart-63011604-091a-4252-86a6-8d44d1c3e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151017220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3151017220
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.242216506
Short name T929
Test name
Test status
Simulation time 24350783553 ps
CPU time 47.89 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:46:52 PM PDT 24
Peak memory 249592 kb
Host smart-0dc218e3-f124-4f48-b6ef-cc2f27f9bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242216506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.242216506
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.64470135
Short name T959
Test name
Test status
Simulation time 9732134998 ps
CPU time 47.99 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:51 PM PDT 24
Peak memory 257712 kb
Host smart-95a91cca-e093-493f-9297-6d1b9aa383d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64470135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.64470135
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.139239797
Short name T660
Test name
Test status
Simulation time 862938715 ps
CPU time 10.73 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:46:12 PM PDT 24
Peak memory 224976 kb
Host smart-467d2dad-b606-49f5-ab7f-656c2dd16968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139239797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
139239797
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1735681407
Short name T860
Test name
Test status
Simulation time 2090502121 ps
CPU time 33.56 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:46:39 PM PDT 24
Peak memory 233088 kb
Host smart-74716d8f-0729-4f4a-b04f-58fb6bc1cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735681407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1735681407
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2334793401
Short name T59
Test name
Test status
Simulation time 2526250038 ps
CPU time 35.04 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:39 PM PDT 24
Peak memory 241768 kb
Host smart-7154b532-47a4-4249-960a-c1208dfb0b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334793401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2334793401
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2958119352
Short name T276
Test name
Test status
Simulation time 1972565595 ps
CPU time 7.89 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:10 PM PDT 24
Peak memory 224964 kb
Host smart-1d5395e6-99c1-4a3c-b4c6-cfc0429eec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958119352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2958119352
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2393147521
Short name T698
Test name
Test status
Simulation time 14162893238 ps
CPU time 23.5 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:27 PM PDT 24
Peak memory 240896 kb
Host smart-a8859c6c-b0e3-43c7-80a9-ff17e3a37b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393147521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2393147521
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1103549910
Short name T520
Test name
Test status
Simulation time 2359361626 ps
CPU time 8.69 seconds
Started Aug 08 07:46:00 PM PDT 24
Finished Aug 08 07:46:09 PM PDT 24
Peak memory 233268 kb
Host smart-81ec4d65-4473-40db-acbd-48519f8cd8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103549910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1103549910
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1372414718
Short name T967
Test name
Test status
Simulation time 22906845395 ps
CPU time 15.52 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:46:19 PM PDT 24
Peak memory 233384 kb
Host smart-76f0507d-5892-4ea2-9f82-2ef03cc927d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372414718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1372414718
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2366639537
Short name T54
Test name
Test status
Simulation time 133968701 ps
CPU time 1.11 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:46:05 PM PDT 24
Peak memory 236868 kb
Host smart-3386d9ec-f8a1-4d3a-8b62-c36fa5743c3a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366639537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2366639537
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1367250659
Short name T534
Test name
Test status
Simulation time 1095056601 ps
CPU time 2.47 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:04 PM PDT 24
Peak memory 223160 kb
Host smart-5842711d-4553-4710-8ec0-da93af4ecb2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367250659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1367250659
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3012811829
Short name T762
Test name
Test status
Simulation time 7381943888 ps
CPU time 14.31 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:16 PM PDT 24
Peak memory 216748 kb
Host smart-66d53b4d-0b3b-447e-9619-b4aa12aa2101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012811829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3012811829
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.470209566
Short name T772
Test name
Test status
Simulation time 4038845428 ps
CPU time 11.28 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:46:12 PM PDT 24
Peak memory 216800 kb
Host smart-80ef1e93-bfa1-41e3-bc32-cf245d0da5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470209566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.470209566
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1064365191
Short name T806
Test name
Test status
Simulation time 178550316 ps
CPU time 1.33 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:46:02 PM PDT 24
Peak memory 208308 kb
Host smart-b8c0dd49-1f7e-4eef-997f-a0a63a4fbe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064365191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1064365191
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3843770835
Short name T661
Test name
Test status
Simulation time 45585755 ps
CPU time 0.91 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:46:06 PM PDT 24
Peak memory 207324 kb
Host smart-0c35b9b5-1b20-4801-b958-72eba4c1d2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843770835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3843770835
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1157913179
Short name T757
Test name
Test status
Simulation time 1760097941 ps
CPU time 3.7 seconds
Started Aug 08 07:46:01 PM PDT 24
Finished Aug 08 07:46:04 PM PDT 24
Peak memory 224892 kb
Host smart-6a7d1c20-7c60-468e-8855-268bb1ff2d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157913179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1157913179
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3640091388
Short name T777
Test name
Test status
Simulation time 343200100 ps
CPU time 2.44 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:46:39 PM PDT 24
Peak memory 224948 kb
Host smart-86615444-a9f9-48dd-81f8-13f46635153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640091388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3640091388
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4228401767
Short name T794
Test name
Test status
Simulation time 86884773 ps
CPU time 0.78 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:34 PM PDT 24
Peak memory 206968 kb
Host smart-4da5dea9-6640-4d3b-9a2d-797a03368deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228401767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4228401767
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.187061299
Short name T424
Test name
Test status
Simulation time 21048077 ps
CPU time 0.78 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:36 PM PDT 24
Peak memory 216152 kb
Host smart-1d186df8-d0e4-43fa-9581-61ada7dc0fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187061299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.187061299
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.948981895
Short name T656
Test name
Test status
Simulation time 1308153687 ps
CPU time 14.07 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:49 PM PDT 24
Peak memory 217884 kb
Host smart-a594441a-ed6e-416f-9da7-f6a246449412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948981895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.948981895
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2612125091
Short name T814
Test name
Test status
Simulation time 778945575 ps
CPU time 4.02 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:39 PM PDT 24
Peak memory 224948 kb
Host smart-a3ef5c97-9f22-45ea-9712-89ff15af5dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612125091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2612125091
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2206820243
Short name T510
Test name
Test status
Simulation time 35363750852 ps
CPU time 21.71 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:55 PM PDT 24
Peak memory 233188 kb
Host smart-06f0ed99-6c38-4e0e-933a-6a53ba773a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206820243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2206820243
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1721563652
Short name T164
Test name
Test status
Simulation time 14813393228 ps
CPU time 23.44 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:47:01 PM PDT 24
Peak memory 233184 kb
Host smart-5b4f2ffa-7e2b-4363-b088-12277f56ab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721563652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1721563652
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.757018269
Short name T512
Test name
Test status
Simulation time 944886491 ps
CPU time 3.08 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:38 PM PDT 24
Peak memory 233096 kb
Host smart-b25ccdbc-4522-4151-8cc9-bfc87e279548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757018269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.757018269
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2358165545
Short name T3
Test name
Test status
Simulation time 458676515 ps
CPU time 6.44 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:39 PM PDT 24
Peak memory 240900 kb
Host smart-4777c284-59c7-4a16-9d08-0f84d815f8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358165545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2358165545
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2225341069
Short name T662
Test name
Test status
Simulation time 482536147 ps
CPU time 4.81 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:38 PM PDT 24
Peak memory 219252 kb
Host smart-f31ab772-aae8-4e2b-a081-d10c93446e3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2225341069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2225341069
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2885632495
Short name T311
Test name
Test status
Simulation time 4752626960 ps
CPU time 22.25 seconds
Started Aug 08 07:46:34 PM PDT 24
Finished Aug 08 07:46:57 PM PDT 24
Peak memory 216980 kb
Host smart-e3c9fe63-a36d-4675-97b3-b016343f63d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885632495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2885632495
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.538204754
Short name T895
Test name
Test status
Simulation time 1577951387 ps
CPU time 4.52 seconds
Started Aug 08 07:46:36 PM PDT 24
Finished Aug 08 07:46:41 PM PDT 24
Peak memory 216692 kb
Host smart-0476e695-bff7-4813-8123-7fef6b480625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538204754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.538204754
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.366309941
Short name T884
Test name
Test status
Simulation time 109323952 ps
CPU time 2.91 seconds
Started Aug 08 07:46:30 PM PDT 24
Finished Aug 08 07:46:33 PM PDT 24
Peak memory 216612 kb
Host smart-c1897670-5a82-40eb-96b5-800963ca08ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366309941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.366309941
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2258655726
Short name T451
Test name
Test status
Simulation time 105155526 ps
CPU time 0.93 seconds
Started Aug 08 07:46:34 PM PDT 24
Finished Aug 08 07:46:35 PM PDT 24
Peak memory 206332 kb
Host smart-81bfc987-04c0-407c-a6b6-72ab16fd5ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258655726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2258655726
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1467857909
Short name T196
Test name
Test status
Simulation time 516690888 ps
CPU time 6.11 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:39 PM PDT 24
Peak memory 233180 kb
Host smart-7e020cba-9e60-4ea4-a6f3-170bb0b24123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467857909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1467857909
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2437952554
Short name T616
Test name
Test status
Simulation time 23416033 ps
CPU time 0.7 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:46:38 PM PDT 24
Peak memory 206180 kb
Host smart-8167d213-1bb0-4870-a18b-8828e3f0edc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437952554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2437952554
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2636093441
Short name T540
Test name
Test status
Simulation time 705791783 ps
CPU time 7.11 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:41 PM PDT 24
Peak memory 224888 kb
Host smart-33533634-de53-4bee-ab48-7b1d9355ad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636093441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2636093441
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.82257521
Short name T696
Test name
Test status
Simulation time 15669825 ps
CPU time 0.73 seconds
Started Aug 08 07:46:30 PM PDT 24
Finished Aug 08 07:46:31 PM PDT 24
Peak memory 205964 kb
Host smart-ae7deb8d-326e-45c1-8843-9cc8ca55aa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82257521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.82257521
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3722255451
Short name T554
Test name
Test status
Simulation time 6923261040 ps
CPU time 74.22 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:47:52 PM PDT 24
Peak memory 257488 kb
Host smart-5b436a74-0246-45a3-8ddf-c0dd21e9a5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722255451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3722255451
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2660979507
Short name T459
Test name
Test status
Simulation time 2254677606 ps
CPU time 40.43 seconds
Started Aug 08 07:46:36 PM PDT 24
Finished Aug 08 07:47:17 PM PDT 24
Peak memory 251812 kb
Host smart-e1f555c3-3589-4085-b487-f4d33c011315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660979507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2660979507
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1124210420
Short name T854
Test name
Test status
Simulation time 205347868 ps
CPU time 4.69 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:38 PM PDT 24
Peak memory 224960 kb
Host smart-7a401df4-03aa-4fc6-8ac3-4f80886c84af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124210420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1124210420
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2078564824
Short name T421
Test name
Test status
Simulation time 5445374639 ps
CPU time 51.03 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:47:28 PM PDT 24
Peak memory 252500 kb
Host smart-f79e6dbc-057d-4b6f-b0fa-4f77f12252d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078564824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2078564824
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2547977125
Short name T763
Test name
Test status
Simulation time 2754862815 ps
CPU time 15.75 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:51 PM PDT 24
Peak memory 225012 kb
Host smart-c4e2658a-6b8b-4ced-a7e3-dcadc8b21af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547977125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2547977125
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1433853417
Short name T182
Test name
Test status
Simulation time 410791449 ps
CPU time 4.42 seconds
Started Aug 08 07:46:36 PM PDT 24
Finished Aug 08 07:46:41 PM PDT 24
Peak memory 233148 kb
Host smart-93585e75-3577-472e-a510-8e91beb17fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433853417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1433853417
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2930088084
Short name T657
Test name
Test status
Simulation time 9033526973 ps
CPU time 8.72 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:42 PM PDT 24
Peak memory 225036 kb
Host smart-042bcaba-0b10-4ad0-91d7-954a78e90862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930088084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2930088084
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3970724087
Short name T759
Test name
Test status
Simulation time 15909108707 ps
CPU time 14 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:49 PM PDT 24
Peak memory 233224 kb
Host smart-20499393-1640-4c4e-8834-2010c097c28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970724087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3970724087
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.130911939
Short name T752
Test name
Test status
Simulation time 964088118 ps
CPU time 4.87 seconds
Started Aug 08 07:46:46 PM PDT 24
Finished Aug 08 07:46:51 PM PDT 24
Peak memory 223260 kb
Host smart-c2b52df2-af7e-470b-8fa2-59f39a1934c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=130911939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.130911939
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2427417163
Short name T789
Test name
Test status
Simulation time 128587773924 ps
CPU time 1177.45 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 08:06:14 PM PDT 24
Peak memory 276504 kb
Host smart-d6803891-869c-4795-9ad8-1db78bdb2fd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427417163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2427417163
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2187845802
Short name T35
Test name
Test status
Simulation time 1561179723 ps
CPU time 23.4 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:47:00 PM PDT 24
Peak memory 216816 kb
Host smart-6663f018-4c64-49bc-9f13-07adb3855fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187845802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2187845802
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2091916470
Short name T718
Test name
Test status
Simulation time 18243675355 ps
CPU time 13.2 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:46:53 PM PDT 24
Peak memory 216644 kb
Host smart-e1d433c9-9796-4205-a399-18979e75516c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091916470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2091916470
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1002795882
Short name T893
Test name
Test status
Simulation time 458780787 ps
CPU time 4.52 seconds
Started Aug 08 07:46:32 PM PDT 24
Finished Aug 08 07:46:37 PM PDT 24
Peak memory 216740 kb
Host smart-e10a250e-fdea-4997-96e6-ae57b9b0d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002795882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1002795882
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1216448074
Short name T768
Test name
Test status
Simulation time 58061350 ps
CPU time 0.78 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:36 PM PDT 24
Peak memory 206340 kb
Host smart-d2a94515-3012-466d-bb73-379a3c582924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216448074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1216448074
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3655280308
Short name T1001
Test name
Test status
Simulation time 110761994 ps
CPU time 2.45 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:46:40 PM PDT 24
Peak memory 225012 kb
Host smart-8e00b0c0-1cfc-4c61-b27c-74efcdb350e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655280308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3655280308
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2757011935
Short name T971
Test name
Test status
Simulation time 29329126 ps
CPU time 0.68 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:46:40 PM PDT 24
Peak memory 205212 kb
Host smart-c1f52a36-1a17-4202-b2d8-15479e9129c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757011935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2757011935
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2851108696
Short name T740
Test name
Test status
Simulation time 1106510512 ps
CPU time 13.32 seconds
Started Aug 08 07:46:46 PM PDT 24
Finished Aug 08 07:47:00 PM PDT 24
Peak memory 233120 kb
Host smart-e97d2bf1-1e24-4894-80dd-ec14416c8025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851108696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2851108696
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4231072644
Short name T472
Test name
Test status
Simulation time 17869221 ps
CPU time 0.8 seconds
Started Aug 08 07:46:46 PM PDT 24
Finished Aug 08 07:46:47 PM PDT 24
Peak memory 206284 kb
Host smart-dea73edf-0226-4c31-93ca-5c00a7dc06c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231072644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4231072644
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1089241362
Short name T542
Test name
Test status
Simulation time 12232276888 ps
CPU time 58.37 seconds
Started Aug 08 07:46:40 PM PDT 24
Finished Aug 08 07:47:38 PM PDT 24
Peak memory 265764 kb
Host smart-b36ee813-f346-4444-9381-573141109930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089241362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1089241362
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2638984403
Short name T722
Test name
Test status
Simulation time 6933542773 ps
CPU time 23.82 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 218088 kb
Host smart-8c2f452d-5e2b-40bf-9369-d8dc715f792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638984403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2638984403
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.103146343
Short name T206
Test name
Test status
Simulation time 1934821239 ps
CPU time 42.12 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:47:21 PM PDT 24
Peak memory 249520 kb
Host smart-3930fce6-4cbd-4347-a3e6-9160b5ff60e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103146343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.103146343
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1027029287
Short name T701
Test name
Test status
Simulation time 1000016943 ps
CPU time 12.44 seconds
Started Aug 08 07:46:45 PM PDT 24
Finished Aug 08 07:46:58 PM PDT 24
Peak memory 233144 kb
Host smart-7f25b533-9f6b-4796-8c6e-7f6e84409b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027029287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1027029287
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3259145324
Short name T710
Test name
Test status
Simulation time 17190192555 ps
CPU time 33.76 seconds
Started Aug 08 07:46:38 PM PDT 24
Finished Aug 08 07:47:12 PM PDT 24
Peak memory 241148 kb
Host smart-ceb9a2d1-c844-469c-82d2-5bbeecf5d634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259145324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3259145324
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1165642764
Short name T192
Test name
Test status
Simulation time 7334996650 ps
CPU time 23.44 seconds
Started Aug 08 07:46:46 PM PDT 24
Finished Aug 08 07:47:10 PM PDT 24
Peak memory 233200 kb
Host smart-19ba503f-8116-4791-a004-4addcd5ec752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165642764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1165642764
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1875870537
Short name T799
Test name
Test status
Simulation time 12380430225 ps
CPU time 9.65 seconds
Started Aug 08 07:46:45 PM PDT 24
Finished Aug 08 07:46:55 PM PDT 24
Peak memory 241348 kb
Host smart-121be5c8-4aab-40d5-94b2-613f47841051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875870537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1875870537
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2476756258
Short name T134
Test name
Test status
Simulation time 3398796175 ps
CPU time 24.7 seconds
Started Aug 08 07:46:46 PM PDT 24
Finished Aug 08 07:47:11 PM PDT 24
Peak memory 220000 kb
Host smart-ebcd80ce-1118-4d4e-abca-3f8ccffc9e80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2476756258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2476756258
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.338120057
Short name T833
Test name
Test status
Simulation time 6243340746 ps
CPU time 103.05 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:48:22 PM PDT 24
Peak memory 255484 kb
Host smart-2bd1813c-5af1-4039-9cca-5fcff1ac9c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338120057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.338120057
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3785900722
Short name T594
Test name
Test status
Simulation time 6187193112 ps
CPU time 35.91 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:47:15 PM PDT 24
Peak memory 216688 kb
Host smart-b680b52a-cedd-48f4-bf7e-dd282d39067b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785900722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3785900722
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.733102854
Short name T489
Test name
Test status
Simulation time 15130970706 ps
CPU time 24.33 seconds
Started Aug 08 07:46:38 PM PDT 24
Finished Aug 08 07:47:03 PM PDT 24
Peak memory 216708 kb
Host smart-a5702a7e-3adf-47c4-a842-63245df0ae61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733102854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.733102854
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3262956151
Short name T591
Test name
Test status
Simulation time 169598300 ps
CPU time 2.81 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:46:40 PM PDT 24
Peak memory 216668 kb
Host smart-de787b75-e253-48b1-be72-b37ba1d9fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262956151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3262956151
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.886931220
Short name T819
Test name
Test status
Simulation time 20035418 ps
CPU time 0.8 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:46:40 PM PDT 24
Peak memory 206328 kb
Host smart-84108fb1-c7ee-4da5-97a5-5dc33b427447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886931220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.886931220
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.965933279
Short name T503
Test name
Test status
Simulation time 8894372435 ps
CPU time 9.66 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:46:47 PM PDT 24
Peak memory 224984 kb
Host smart-cfe9cb67-94d1-4344-8150-246eb16c4e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965933279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.965933279
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3586982718
Short name T395
Test name
Test status
Simulation time 87592874 ps
CPU time 0.71 seconds
Started Aug 08 07:46:49 PM PDT 24
Finished Aug 08 07:46:50 PM PDT 24
Peak memory 205268 kb
Host smart-3d26af0f-ba9d-481e-a9d8-b9d3a4d1308c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586982718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3586982718
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2000275350
Short name T337
Test name
Test status
Simulation time 73366361 ps
CPU time 2.58 seconds
Started Aug 08 07:46:45 PM PDT 24
Finished Aug 08 07:46:48 PM PDT 24
Peak memory 233076 kb
Host smart-bf5a4102-a2d8-479f-904b-1d7ae729efa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000275350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2000275350
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3658933878
Short name T668
Test name
Test status
Simulation time 53752198 ps
CPU time 0.77 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:45 PM PDT 24
Peak memory 206028 kb
Host smart-6c319ac2-50f7-4f79-8c34-c21f3e6bedec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658933878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3658933878
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2969082033
Short name T148
Test name
Test status
Simulation time 3107621100 ps
CPU time 25.38 seconds
Started Aug 08 07:46:40 PM PDT 24
Finished Aug 08 07:47:05 PM PDT 24
Peak memory 233204 kb
Host smart-144b172f-dcd3-4489-a37c-873b04148cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969082033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2969082033
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2259445056
Short name T434
Test name
Test status
Simulation time 5490332648 ps
CPU time 30.24 seconds
Started Aug 08 07:46:46 PM PDT 24
Finished Aug 08 07:47:16 PM PDT 24
Peak memory 241436 kb
Host smart-15097d1f-75f6-476c-8840-0f28be8116ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259445056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2259445056
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1013336843
Short name T597
Test name
Test status
Simulation time 406949014 ps
CPU time 5.51 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:50 PM PDT 24
Peak memory 239420 kb
Host smart-9d20fa81-fa8a-4401-a711-263a24759643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013336843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1013336843
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2229871094
Short name T247
Test name
Test status
Simulation time 5833447582 ps
CPU time 52.58 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:47:32 PM PDT 24
Peak memory 252268 kb
Host smart-dbae404c-5a4e-46a0-9689-41e8cd0a0b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229871094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2229871094
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.450245690
Short name T795
Test name
Test status
Simulation time 834462667 ps
CPU time 4.74 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:49 PM PDT 24
Peak memory 233212 kb
Host smart-25f81faf-6115-4310-ac4e-736c4b9e68d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450245690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.450245690
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.190003678
Short name T185
Test name
Test status
Simulation time 28000235613 ps
CPU time 76.16 seconds
Started Aug 08 07:46:40 PM PDT 24
Finished Aug 08 07:47:56 PM PDT 24
Peak memory 233212 kb
Host smart-7c1dc8e7-8e13-4d26-bc07-f121fc77eab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190003678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.190003678
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3221060224
Short name T988
Test name
Test status
Simulation time 44442915255 ps
CPU time 21.54 seconds
Started Aug 08 07:46:40 PM PDT 24
Finished Aug 08 07:47:01 PM PDT 24
Peak memory 233244 kb
Host smart-4e5163af-599b-4a24-912c-c0021816e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221060224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3221060224
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2405884973
Short name T788
Test name
Test status
Simulation time 2400396170 ps
CPU time 8.01 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:52 PM PDT 24
Peak memory 240824 kb
Host smart-ed4880a7-31d7-44c9-89c3-0fa7200f3ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405884973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2405884973
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2361380874
Short name T558
Test name
Test status
Simulation time 318715425 ps
CPU time 4.65 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:49 PM PDT 24
Peak memory 223504 kb
Host smart-8886a1ea-75f0-4204-b70f-1e6c2e8c4638
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2361380874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2361380874
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.720823647
Short name T143
Test name
Test status
Simulation time 6389911668 ps
CPU time 25.56 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:47:05 PM PDT 24
Peak memory 233228 kb
Host smart-f5f80bc1-8050-4a4b-bf89-6f5b37636de9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720823647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.720823647
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.192625602
Short name T989
Test name
Test status
Simulation time 241157963 ps
CPU time 5.3 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:49 PM PDT 24
Peak memory 216692 kb
Host smart-85c36b62-7617-46f3-9b98-6ba55cf78f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192625602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.192625602
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3267230188
Short name T891
Test name
Test status
Simulation time 1534159364 ps
CPU time 5.05 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:49 PM PDT 24
Peak memory 216644 kb
Host smart-3444b12a-0ce0-44e2-92cf-ff291ed618ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267230188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3267230188
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.249915821
Short name T682
Test name
Test status
Simulation time 133826371 ps
CPU time 1.38 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:46 PM PDT 24
Peak memory 208084 kb
Host smart-42a11326-60e7-450a-b521-602494f5c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249915821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.249915821
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3642677047
Short name T360
Test name
Test status
Simulation time 14517891 ps
CPU time 0.73 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:45 PM PDT 24
Peak memory 206368 kb
Host smart-bc0930ee-bda2-4c02-b6bd-046fa780203b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642677047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3642677047
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1150223404
Short name T281
Test name
Test status
Simulation time 356750698 ps
CPU time 6.39 seconds
Started Aug 08 07:46:44 PM PDT 24
Finished Aug 08 07:46:51 PM PDT 24
Peak memory 241044 kb
Host smart-8c4c3258-5336-40d8-af8d-dfd4bbf0f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150223404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1150223404
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.977112688
Short name T482
Test name
Test status
Simulation time 22239845 ps
CPU time 0.68 seconds
Started Aug 08 07:46:53 PM PDT 24
Finished Aug 08 07:46:53 PM PDT 24
Peak memory 205272 kb
Host smart-1717fd9d-21e0-49f5-8cef-dcba0fca50ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977112688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.977112688
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4011834865
Short name T466
Test name
Test status
Simulation time 17902535 ps
CPU time 0.79 seconds
Started Aug 08 07:46:49 PM PDT 24
Finished Aug 08 07:46:50 PM PDT 24
Peak memory 206276 kb
Host smart-2f8d9cc1-ba8d-4601-84ff-cfc93c0817c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011834865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4011834865
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1944864827
Short name T167
Test name
Test status
Simulation time 9189792570 ps
CPU time 32.56 seconds
Started Aug 08 07:46:54 PM PDT 24
Finished Aug 08 07:47:27 PM PDT 24
Peak memory 251800 kb
Host smart-7ed9ec0d-e40f-4513-b310-b0a5b9556ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944864827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1944864827
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3345838018
Short name T753
Test name
Test status
Simulation time 4277504725 ps
CPU time 31.24 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:47:21 PM PDT 24
Peak memory 238144 kb
Host smart-c3cdb54c-42b6-49c9-8ffb-1838843f5e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345838018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3345838018
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2381492406
Short name T931
Test name
Test status
Simulation time 6349050016 ps
CPU time 100.61 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:48:31 PM PDT 24
Peak memory 251576 kb
Host smart-8dd376b0-e31c-4b03-a727-a70d8553569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381492406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2381492406
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1634143800
Short name T874
Test name
Test status
Simulation time 481939799 ps
CPU time 7.1 seconds
Started Aug 08 07:46:51 PM PDT 24
Finished Aug 08 07:46:58 PM PDT 24
Peak memory 233152 kb
Host smart-3824a5e9-d726-41e4-8767-90fc6ab2201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634143800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1634143800
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.4084086830
Short name T886
Test name
Test status
Simulation time 3206901728 ps
CPU time 12.39 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:47:02 PM PDT 24
Peak memory 234228 kb
Host smart-e94652db-2d8d-4253-9999-fbdf7422ea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084086830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.4084086830
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3539433034
Short name T654
Test name
Test status
Simulation time 1216134378 ps
CPU time 3.23 seconds
Started Aug 08 07:46:56 PM PDT 24
Finished Aug 08 07:46:59 PM PDT 24
Peak memory 224904 kb
Host smart-ebd220e9-0a95-4967-bfaa-d703820da324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539433034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3539433034
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.453179930
Short name T426
Test name
Test status
Simulation time 2452383778 ps
CPU time 22.79 seconds
Started Aug 08 07:46:54 PM PDT 24
Finished Aug 08 07:47:17 PM PDT 24
Peak memory 233244 kb
Host smart-8217c39d-3b47-4d47-ae31-c2b4a03daf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453179930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.453179930
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3064616717
Short name T61
Test name
Test status
Simulation time 687318441 ps
CPU time 5.16 seconds
Started Aug 08 07:46:51 PM PDT 24
Finished Aug 08 07:46:57 PM PDT 24
Peak memory 233096 kb
Host smart-cbf2986e-ba77-4b6c-8689-e0b367547a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064616717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3064616717
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3527796794
Short name T171
Test name
Test status
Simulation time 5486675466 ps
CPU time 6.78 seconds
Started Aug 08 07:46:49 PM PDT 24
Finished Aug 08 07:46:56 PM PDT 24
Peak memory 233248 kb
Host smart-ee4546d2-047e-45d5-8565-b96605880c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527796794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3527796794
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3628595298
Short name T590
Test name
Test status
Simulation time 1465140428 ps
CPU time 5.79 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:46:56 PM PDT 24
Peak memory 223564 kb
Host smart-86608537-97e1-401a-aa1c-58a28ce7ff53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3628595298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3628595298
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3724983057
Short name T561
Test name
Test status
Simulation time 2915065439 ps
CPU time 27.72 seconds
Started Aug 08 07:46:51 PM PDT 24
Finished Aug 08 07:47:19 PM PDT 24
Peak memory 220868 kb
Host smart-8fe81e6c-9193-4058-864e-70ccd6e89437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724983057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3724983057
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3417768967
Short name T620
Test name
Test status
Simulation time 518836178 ps
CPU time 3.72 seconds
Started Aug 08 07:46:56 PM PDT 24
Finished Aug 08 07:47:00 PM PDT 24
Peak memory 216692 kb
Host smart-74a6804c-bd44-47b1-8847-4c00f066d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417768967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3417768967
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1926832120
Short name T965
Test name
Test status
Simulation time 350826581 ps
CPU time 1.8 seconds
Started Aug 08 07:46:55 PM PDT 24
Finished Aug 08 07:46:56 PM PDT 24
Peak memory 216672 kb
Host smart-192dee7d-7ef2-4f74-a889-59d08926b606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926832120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1926832120
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3373236802
Short name T966
Test name
Test status
Simulation time 236835567 ps
CPU time 0.88 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:46:51 PM PDT 24
Peak memory 206320 kb
Host smart-e8a3793e-9011-4268-b4a6-269207081ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373236802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3373236802
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3569492274
Short name T396
Test name
Test status
Simulation time 3259994387 ps
CPU time 6.44 seconds
Started Aug 08 07:46:51 PM PDT 24
Finished Aug 08 07:46:58 PM PDT 24
Peak memory 224956 kb
Host smart-6e67041c-e152-4085-9aa6-cf05963c5a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569492274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3569492274
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2620906830
Short name T325
Test name
Test status
Simulation time 19919966 ps
CPU time 0.76 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:08 PM PDT 24
Peak memory 206240 kb
Host smart-6a6847f5-62fa-4396-8a42-19ac65d1e542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620906830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2620906830
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.452121699
Short name T77
Test name
Test status
Simulation time 2299455870 ps
CPU time 12.4 seconds
Started Aug 08 07:46:49 PM PDT 24
Finished Aug 08 07:47:01 PM PDT 24
Peak memory 225068 kb
Host smart-d8cdbd9b-8af0-40af-99aa-56cebea9d127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452121699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.452121699
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4148903976
Short name T343
Test name
Test status
Simulation time 87972522 ps
CPU time 0.78 seconds
Started Aug 08 07:46:49 PM PDT 24
Finished Aug 08 07:46:50 PM PDT 24
Peak memory 207008 kb
Host smart-8e90b5ce-cac4-41fc-b4a3-7fea8b94609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148903976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4148903976
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.956700065
Short name T460
Test name
Test status
Simulation time 3628484908 ps
CPU time 47.22 seconds
Started Aug 08 07:46:48 PM PDT 24
Finished Aug 08 07:47:35 PM PDT 24
Peak memory 249616 kb
Host smart-e9a7efde-9f1c-4a00-95d4-481d44ed8edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956700065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.956700065
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2262782624
Short name T123
Test name
Test status
Simulation time 4422498584 ps
CPU time 57.33 seconds
Started Aug 08 07:46:48 PM PDT 24
Finished Aug 08 07:47:45 PM PDT 24
Peak memory 252772 kb
Host smart-09546b31-7971-4c65-9d43-9462a400d5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262782624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2262782624
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1022554703
Short name T1005
Test name
Test status
Simulation time 34536235992 ps
CPU time 171.41 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:49:58 PM PDT 24
Peak memory 249748 kb
Host smart-7f1b8df3-ca1c-4a35-ae88-83e360db45c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022554703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1022554703
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1117374681
Short name T972
Test name
Test status
Simulation time 7358866932 ps
CPU time 12.31 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:47:02 PM PDT 24
Peak memory 224988 kb
Host smart-f7b9b62b-654c-41fc-ad27-5f7505e9c0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117374681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1117374681
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.285412515
Short name T257
Test name
Test status
Simulation time 6667883759 ps
CPU time 10.21 seconds
Started Aug 08 07:46:51 PM PDT 24
Finished Aug 08 07:47:01 PM PDT 24
Peak memory 225020 kb
Host smart-d6171bc0-b56f-4847-90b3-5f19d2b373d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285412515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.285412515
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3955095663
Short name T720
Test name
Test status
Simulation time 1259569594 ps
CPU time 18.91 seconds
Started Aug 08 07:46:49 PM PDT 24
Finished Aug 08 07:47:08 PM PDT 24
Peak memory 233148 kb
Host smart-d919f10f-e52b-476a-aacb-b4341a8d258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955095663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3955095663
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3607708434
Short name T680
Test name
Test status
Simulation time 106575281 ps
CPU time 2.48 seconds
Started Aug 08 07:46:51 PM PDT 24
Finished Aug 08 07:46:53 PM PDT 24
Peak memory 232716 kb
Host smart-df9a51b0-4e17-4bc9-925f-385c27db2de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607708434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3607708434
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1972652702
Short name T690
Test name
Test status
Simulation time 1815131068 ps
CPU time 7.54 seconds
Started Aug 08 07:46:49 PM PDT 24
Finished Aug 08 07:46:57 PM PDT 24
Peak memory 233200 kb
Host smart-129dee28-a80e-4755-ae6c-fd9e0d38cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972652702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1972652702
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3790305465
Short name T842
Test name
Test status
Simulation time 227216582 ps
CPU time 4.39 seconds
Started Aug 08 07:46:51 PM PDT 24
Finished Aug 08 07:46:55 PM PDT 24
Peak memory 223016 kb
Host smart-3d7a74c6-943d-4105-a5f7-7d6b052c7bba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3790305465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3790305465
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2056577029
Short name T39
Test name
Test status
Simulation time 55224834553 ps
CPU time 277.73 seconds
Started Aug 08 07:47:04 PM PDT 24
Finished Aug 08 07:51:42 PM PDT 24
Peak memory 253108 kb
Host smart-86d18dd6-e786-40a9-a8f2-268b6f437a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056577029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2056577029
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.373012720
Short name T870
Test name
Test status
Simulation time 4017442108 ps
CPU time 17.56 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:47:08 PM PDT 24
Peak memory 220708 kb
Host smart-50ae87a5-b6d6-481f-ae53-19a7904445e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373012720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.373012720
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1262380010
Short name T713
Test name
Test status
Simulation time 7357513125 ps
CPU time 9.14 seconds
Started Aug 08 07:46:52 PM PDT 24
Finished Aug 08 07:47:02 PM PDT 24
Peak memory 216732 kb
Host smart-d9f64e97-8861-4e41-93c8-9642ed3a2262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262380010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1262380010
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4084081701
Short name T430
Test name
Test status
Simulation time 579307860 ps
CPU time 2.74 seconds
Started Aug 08 07:46:48 PM PDT 24
Finished Aug 08 07:46:51 PM PDT 24
Peak memory 216648 kb
Host smart-830362a8-9571-4b31-8243-c5f9a133e09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084081701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4084081701
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2141037181
Short name T418
Test name
Test status
Simulation time 52562815 ps
CPU time 0.86 seconds
Started Aug 08 07:46:52 PM PDT 24
Finished Aug 08 07:46:53 PM PDT 24
Peak memory 206320 kb
Host smart-53c7933c-4770-4e49-ab32-a17fc7cd58f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141037181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2141037181
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3380910976
Short name T911
Test name
Test status
Simulation time 4393696187 ps
CPU time 16.45 seconds
Started Aug 08 07:46:50 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 233184 kb
Host smart-73c6e524-15c7-45ab-b139-5e230bd875ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380910976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3380910976
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4242295780
Short name T805
Test name
Test status
Simulation time 47073013 ps
CPU time 0.71 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:05 PM PDT 24
Peak memory 205852 kb
Host smart-ec590a77-7045-4846-8660-894c6040a1cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242295780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4242295780
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2119030451
Short name T634
Test name
Test status
Simulation time 33699516 ps
CPU time 2.22 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 224940 kb
Host smart-862b16e4-c73f-4f8d-a172-c1f569048679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119030451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2119030451
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2220739125
Short name T438
Test name
Test status
Simulation time 64152017 ps
CPU time 0.75 seconds
Started Aug 08 07:46:58 PM PDT 24
Finished Aug 08 07:46:59 PM PDT 24
Peak memory 206036 kb
Host smart-c2d9f1c7-3a67-4c99-8ede-c5cc44ebaffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220739125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2220739125
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1797536300
Short name T184
Test name
Test status
Simulation time 56549101062 ps
CPU time 81.88 seconds
Started Aug 08 07:46:59 PM PDT 24
Finished Aug 08 07:48:21 PM PDT 24
Peak memory 257088 kb
Host smart-0e17e977-2cfb-4c58-ba58-f90dcacaef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797536300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1797536300
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.35495374
Short name T992
Test name
Test status
Simulation time 9640891976 ps
CPU time 63.08 seconds
Started Aug 08 07:47:04 PM PDT 24
Finished Aug 08 07:48:07 PM PDT 24
Peak memory 247120 kb
Host smart-5f884d77-4d68-45ac-a5d0-5b6267cca23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35495374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.35495374
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2280136162
Short name T202
Test name
Test status
Simulation time 23386897581 ps
CPU time 263.83 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:51:30 PM PDT 24
Peak memory 273944 kb
Host smart-1ef09f8d-a1e9-4697-9c2c-c47d76ca599d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280136162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2280136162
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3655096864
Short name T569
Test name
Test status
Simulation time 288734413 ps
CPU time 5.68 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:10 PM PDT 24
Peak memory 233132 kb
Host smart-76436d84-f798-4b11-9762-cbc29c96090d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655096864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3655096864
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.4097310582
Short name T215
Test name
Test status
Simulation time 631974327 ps
CPU time 7.8 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:14 PM PDT 24
Peak memory 235276 kb
Host smart-237c0ddf-b852-448d-aef3-7ba1065a2cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097310582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.4097310582
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2684120021
Short name T251
Test name
Test status
Simulation time 1004426060 ps
CPU time 6.13 seconds
Started Aug 08 07:47:01 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 233164 kb
Host smart-4248be36-ad63-495b-9810-053a5bf26186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684120021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2684120021
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.198266166
Short name T288
Test name
Test status
Simulation time 23182355812 ps
CPU time 94.05 seconds
Started Aug 08 07:46:57 PM PDT 24
Finished Aug 08 07:48:31 PM PDT 24
Peak memory 233176 kb
Host smart-d668bb6c-ae3b-4c2e-a2a3-0ca8e1dda4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198266166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.198266166
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.122436597
Short name T429
Test name
Test status
Simulation time 539023860 ps
CPU time 3.84 seconds
Started Aug 08 07:47:04 PM PDT 24
Finished Aug 08 07:47:08 PM PDT 24
Peak memory 224836 kb
Host smart-412b2d28-b5d4-44dc-b643-e0f30469ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122436597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.122436597
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.184959138
Short name T925
Test name
Test status
Simulation time 26004538592 ps
CPU time 12.59 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:47:20 PM PDT 24
Peak memory 233180 kb
Host smart-088154a4-ee96-4c24-beac-387e26782d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184959138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.184959138
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1648067633
Short name T727
Test name
Test status
Simulation time 5658359207 ps
CPU time 6.31 seconds
Started Aug 08 07:46:59 PM PDT 24
Finished Aug 08 07:47:05 PM PDT 24
Peak memory 220528 kb
Host smart-77dab618-8f5c-4e69-b3e3-41b86ab00bef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1648067633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1648067633
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1800931933
Short name T231
Test name
Test status
Simulation time 62351562848 ps
CPU time 635.46 seconds
Started Aug 08 07:47:04 PM PDT 24
Finished Aug 08 07:57:40 PM PDT 24
Peak memory 290604 kb
Host smart-6735d33f-63c7-474f-98fb-db403a9da480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800931933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1800931933
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3890525259
Short name T541
Test name
Test status
Simulation time 620855499 ps
CPU time 1.21 seconds
Started Aug 08 07:46:59 PM PDT 24
Finished Aug 08 07:47:00 PM PDT 24
Peak memory 208152 kb
Host smart-ef64bf67-a33b-4366-abe8-4e0149624d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890525259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3890525259
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1542898697
Short name T495
Test name
Test status
Simulation time 34099427 ps
CPU time 1.12 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:08 PM PDT 24
Peak memory 207992 kb
Host smart-4733cae4-509f-4bb8-a995-bea6f3bd1050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542898697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1542898697
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3335460439
Short name T63
Test name
Test status
Simulation time 69540631 ps
CPU time 0.87 seconds
Started Aug 08 07:46:55 PM PDT 24
Finished Aug 08 07:46:56 PM PDT 24
Peak memory 206332 kb
Host smart-c1f50614-0505-4d1b-b438-a657714c8ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335460439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3335460439
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.957602649
Short name T280
Test name
Test status
Simulation time 844248591 ps
CPU time 4.23 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:11 PM PDT 24
Peak memory 224928 kb
Host smart-0d30f90d-43da-40e2-bcc2-dcf492638356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957602649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.957602649
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2698279256
Short name T550
Test name
Test status
Simulation time 12816893 ps
CPU time 0.72 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:47:09 PM PDT 24
Peak memory 206136 kb
Host smart-67f5aa4f-0fcf-4123-b855-2e9eda5e0072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698279256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2698279256
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4120692995
Short name T190
Test name
Test status
Simulation time 145396177 ps
CPU time 5.36 seconds
Started Aug 08 07:47:04 PM PDT 24
Finished Aug 08 07:47:09 PM PDT 24
Peak memory 224868 kb
Host smart-246ef2c8-9239-41f8-8b53-f83d0666f921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120692995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4120692995
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3539577691
Short name T947
Test name
Test status
Simulation time 34089441 ps
CPU time 0.74 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:08 PM PDT 24
Peak memory 205972 kb
Host smart-bf83493c-3357-43a9-8dea-924ac646e5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539577691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3539577691
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1389759472
Short name T568
Test name
Test status
Simulation time 105549508 ps
CPU time 0.77 seconds
Started Aug 08 07:47:11 PM PDT 24
Finished Aug 08 07:47:12 PM PDT 24
Peak memory 216164 kb
Host smart-14c29227-ae14-40ff-af20-906c320569d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389759472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1389759472
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2497446119
Short name T716
Test name
Test status
Simulation time 4190349502 ps
CPU time 77.7 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:48:27 PM PDT 24
Peak memory 251928 kb
Host smart-45df046d-c304-4eae-8da9-56fdf8c3ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497446119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2497446119
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.177460611
Short name T37
Test name
Test status
Simulation time 30402504492 ps
CPU time 87.15 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:48:32 PM PDT 24
Peak memory 274256 kb
Host smart-1f93b466-f3a2-44e7-b281-e900f3ece676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177460611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.177460611
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1923921510
Short name T351
Test name
Test status
Simulation time 4712580663 ps
CPU time 19.28 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:26 PM PDT 24
Peak memory 225036 kb
Host smart-1ffbad32-3025-4636-8f13-1d5facddcc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923921510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1923921510
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1434222921
Short name T265
Test name
Test status
Simulation time 910267231 ps
CPU time 6.21 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:13 PM PDT 24
Peak memory 224952 kb
Host smart-d64dd2c4-4da5-40d2-98c3-9b3206c2f9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434222921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1434222921
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3299776167
Short name T383
Test name
Test status
Simulation time 152680013 ps
CPU time 2.22 seconds
Started Aug 08 07:46:58 PM PDT 24
Finished Aug 08 07:47:00 PM PDT 24
Peak memory 223508 kb
Host smart-f059a20e-fc53-41a1-92c6-3f228eeafbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299776167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3299776167
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.632118429
Short name T509
Test name
Test status
Simulation time 2911729145 ps
CPU time 5.97 seconds
Started Aug 08 07:47:04 PM PDT 24
Finished Aug 08 07:47:10 PM PDT 24
Peak memory 233204 kb
Host smart-f6d75169-479f-4487-a0ee-4cf3dca4e4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632118429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.632118429
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.652091080
Short name T174
Test name
Test status
Simulation time 308193069 ps
CPU time 3.87 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:10 PM PDT 24
Peak memory 224920 kb
Host smart-f6fbb6ce-5177-427b-8585-7276ddac1d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652091080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.652091080
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.646455998
Short name T381
Test name
Test status
Simulation time 6250228772 ps
CPU time 19.14 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:26 PM PDT 24
Peak memory 219900 kb
Host smart-0fd07e39-9425-408e-819c-716cc027cad6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=646455998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.646455998
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.709290553
Short name T709
Test name
Test status
Simulation time 2428044530 ps
CPU time 25.45 seconds
Started Aug 08 07:47:01 PM PDT 24
Finished Aug 08 07:47:26 PM PDT 24
Peak memory 216828 kb
Host smart-fb1cf2ff-4b58-488f-bd0a-0a9e2f7bbd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709290553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.709290553
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2593640224
Short name T995
Test name
Test status
Simulation time 4497621227 ps
CPU time 8.78 seconds
Started Aug 08 07:47:01 PM PDT 24
Finished Aug 08 07:47:10 PM PDT 24
Peak memory 216816 kb
Host smart-682592df-a004-40e8-b410-b37b6ac83e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593640224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2593640224
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2970480249
Short name T546
Test name
Test status
Simulation time 23148567 ps
CPU time 1.02 seconds
Started Aug 08 07:46:56 PM PDT 24
Finished Aug 08 07:46:57 PM PDT 24
Peak memory 208464 kb
Host smart-81e65b26-da56-4271-8851-694fea3afb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970480249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2970480249
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1385549790
Short name T345
Test name
Test status
Simulation time 64431894 ps
CPU time 0.75 seconds
Started Aug 08 07:46:58 PM PDT 24
Finished Aug 08 07:46:59 PM PDT 24
Peak memory 206396 kb
Host smart-a94ccc1c-2685-43b7-890a-946cf3fffa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385549790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1385549790
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.483176142
Short name T314
Test name
Test status
Simulation time 631825693 ps
CPU time 2.28 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 224560 kb
Host smart-7b1b4366-a44a-4ea8-b03c-2425c45b3344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483176142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.483176142
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3978043696
Short name T834
Test name
Test status
Simulation time 39681751 ps
CPU time 0.69 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:47:10 PM PDT 24
Peak memory 205896 kb
Host smart-a70050aa-1d81-4255-bbc5-6487ab392fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978043696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3978043696
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3567738916
Short name T562
Test name
Test status
Simulation time 101286779 ps
CPU time 2.53 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:10 PM PDT 24
Peak memory 232884 kb
Host smart-70008332-3516-4ca1-a357-803834018ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567738916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3567738916
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3181212219
Short name T488
Test name
Test status
Simulation time 46562437 ps
CPU time 0.77 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:08 PM PDT 24
Peak memory 206256 kb
Host smart-90a709ff-dd32-4c07-aaf7-5aa278be38d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181212219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3181212219
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1139897023
Short name T784
Test name
Test status
Simulation time 100820263566 ps
CPU time 204.62 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:50:33 PM PDT 24
Peak memory 257828 kb
Host smart-10b6b755-52ec-47f5-838e-9df675549609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139897023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1139897023
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4048955503
Short name T275
Test name
Test status
Simulation time 1543846166 ps
CPU time 24.88 seconds
Started Aug 08 07:47:11 PM PDT 24
Finished Aug 08 07:47:36 PM PDT 24
Peak memory 250036 kb
Host smart-86040843-6c0a-4c84-9993-d973007dfcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048955503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4048955503
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2272243690
Short name T823
Test name
Test status
Simulation time 32879760892 ps
CPU time 315.59 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:52:22 PM PDT 24
Peak memory 253860 kb
Host smart-50c63fca-e216-4dff-a245-d600c45e1483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272243690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2272243690
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3695896275
Short name T579
Test name
Test status
Simulation time 241372376 ps
CPU time 5.15 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:10 PM PDT 24
Peak memory 224960 kb
Host smart-dbcbf241-83a6-42b2-a414-4406dbde6fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695896275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3695896275
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2064131485
Short name T755
Test name
Test status
Simulation time 2358595073 ps
CPU time 42.97 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:47:52 PM PDT 24
Peak memory 250928 kb
Host smart-bbc7da25-f4cd-49e8-8e41-e72d6226a505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064131485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2064131485
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1656554592
Short name T255
Test name
Test status
Simulation time 5724652309 ps
CPU time 23.32 seconds
Started Aug 08 07:47:11 PM PDT 24
Finished Aug 08 07:47:34 PM PDT 24
Peak memory 225176 kb
Host smart-00514ab1-32dc-4b5f-ac74-e79571144160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656554592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1656554592
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3096836474
Short name T883
Test name
Test status
Simulation time 2914103489 ps
CPU time 25.34 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:32 PM PDT 24
Peak memory 233212 kb
Host smart-dda84cba-8851-4d11-a78b-cf8fcd789763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096836474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3096836474
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3391668728
Short name T671
Test name
Test status
Simulation time 2274917397 ps
CPU time 9.11 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:16 PM PDT 24
Peak memory 241308 kb
Host smart-d6631c5a-d766-4415-a7d0-3d7b6767724a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391668728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3391668728
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3575736703
Short name T400
Test name
Test status
Simulation time 774030674 ps
CPU time 4.23 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:09 PM PDT 24
Peak memory 224936 kb
Host smart-0a0a2811-4897-4aac-b6b5-87a1c67e3e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575736703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3575736703
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2720268995
Short name T573
Test name
Test status
Simulation time 2541775091 ps
CPU time 7.87 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:14 PM PDT 24
Peak memory 222488 kb
Host smart-a807725a-299d-46ef-9fb5-85e3da913c9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2720268995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2720268995
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3920141099
Short name T598
Test name
Test status
Simulation time 37227185736 ps
CPU time 49.51 seconds
Started Aug 08 07:47:11 PM PDT 24
Finished Aug 08 07:48:01 PM PDT 24
Peak memory 216696 kb
Host smart-2e9daf00-d1f3-43f5-a823-4f08c5205473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920141099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3920141099
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.654352701
Short name T585
Test name
Test status
Simulation time 133058846 ps
CPU time 1.18 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 207408 kb
Host smart-6dc05365-8f0d-47d0-893d-a105d82cdc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654352701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.654352701
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.995217837
Short name T439
Test name
Test status
Simulation time 104776406 ps
CPU time 1.73 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:47:11 PM PDT 24
Peak memory 216668 kb
Host smart-f30d28e3-ad8a-4cfa-a0ba-359c75138f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995217837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.995217837
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.132956216
Short name T998
Test name
Test status
Simulation time 429718009 ps
CPU time 0.79 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 206400 kb
Host smart-9256e6e8-c840-4757-8c61-1995cbb1da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132956216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.132956216
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1083382312
Short name T637
Test name
Test status
Simulation time 6824100375 ps
CPU time 10.84 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:15 PM PDT 24
Peak memory 225024 kb
Host smart-c5061e92-578c-40b6-ab6e-e2a299d811dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083382312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1083382312
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3081086763
Short name T332
Test name
Test status
Simulation time 37029242 ps
CPU time 0.67 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:06 PM PDT 24
Peak memory 205852 kb
Host smart-7b2db6d0-a0fc-448c-b23d-ba5e16263824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081086763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3081086763
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.305087488
Short name T522
Test name
Test status
Simulation time 1699374361 ps
CPU time 12.14 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:47:21 PM PDT 24
Peak memory 224888 kb
Host smart-581a0e93-5555-41cc-816f-bcd355cc7f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305087488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.305087488
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2035712954
Short name T571
Test name
Test status
Simulation time 65203960 ps
CPU time 0.81 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:47:10 PM PDT 24
Peak memory 207048 kb
Host smart-01d2ea28-05ca-4af0-b287-1089cb037e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035712954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2035712954
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3868744928
Short name T208
Test name
Test status
Simulation time 74554507608 ps
CPU time 509.7 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:55:39 PM PDT 24
Peak memory 265980 kb
Host smart-8bf7d395-4b29-4bf1-85b4-0a5b788026c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868744928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3868744928
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1754420479
Short name T2
Test name
Test status
Simulation time 713388607961 ps
CPU time 501.88 seconds
Started Aug 08 07:47:12 PM PDT 24
Finished Aug 08 07:55:34 PM PDT 24
Peak memory 252216 kb
Host smart-b4b2a39f-7665-4901-852a-4f3fd9ef048f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754420479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1754420479
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.167503873
Short name T228
Test name
Test status
Simulation time 121545159882 ps
CPU time 458.97 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:54:47 PM PDT 24
Peak memory 272920 kb
Host smart-99e3cd07-90f1-4fc0-83ce-14030e892cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167503873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.167503873
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4127975411
Short name T157
Test name
Test status
Simulation time 2600160237 ps
CPU time 11.13 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:47:19 PM PDT 24
Peak memory 224960 kb
Host smart-605fd818-d076-4b14-a027-36aa720756c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127975411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4127975411
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3311070392
Short name T161
Test name
Test status
Simulation time 15702588402 ps
CPU time 23.48 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:31 PM PDT 24
Peak memory 241452 kb
Host smart-51aab7dc-f465-45ed-a858-00c8a6ce0ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311070392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3311070392
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2154353031
Short name T945
Test name
Test status
Simulation time 3342856599 ps
CPU time 8.65 seconds
Started Aug 08 07:47:11 PM PDT 24
Finished Aug 08 07:47:20 PM PDT 24
Peak memory 233188 kb
Host smart-4097a2de-54d7-419f-9ce5-68ea623da8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154353031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2154353031
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1395341464
Short name T930
Test name
Test status
Simulation time 4239143050 ps
CPU time 5.76 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:47:14 PM PDT 24
Peak memory 224936 kb
Host smart-e62d5197-cc0f-44df-a182-095436abea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395341464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1395341464
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.886829792
Short name T563
Test name
Test status
Simulation time 1630447924 ps
CPU time 12.99 seconds
Started Aug 08 07:47:12 PM PDT 24
Finished Aug 08 07:47:25 PM PDT 24
Peak memory 220608 kb
Host smart-a4559b52-4440-4d36-953d-bbc26e551102
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=886829792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.886829792
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1488572945
Short name T756
Test name
Test status
Simulation time 12009410650 ps
CPU time 92.67 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:48:40 PM PDT 24
Peak memory 249580 kb
Host smart-284bc70b-ab53-4969-bcc0-6138ca2c8693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488572945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1488572945
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2797774688
Short name T491
Test name
Test status
Simulation time 2524818505 ps
CPU time 4.42 seconds
Started Aug 08 07:47:11 PM PDT 24
Finished Aug 08 07:47:16 PM PDT 24
Peak memory 216764 kb
Host smart-e64913cb-b084-4a83-b429-551f77efd87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797774688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2797774688
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2298005839
Short name T401
Test name
Test status
Simulation time 6729457946 ps
CPU time 22.02 seconds
Started Aug 08 07:47:10 PM PDT 24
Finished Aug 08 07:47:32 PM PDT 24
Peak memory 216904 kb
Host smart-913e5096-376c-4cd5-b81b-82068bfa1a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298005839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2298005839
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3330140118
Short name T829
Test name
Test status
Simulation time 486042267 ps
CPU time 3.86 seconds
Started Aug 08 07:47:11 PM PDT 24
Finished Aug 08 07:47:15 PM PDT 24
Peak memory 216704 kb
Host smart-72ceb498-1f4f-4f63-a8d1-022bf5707e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330140118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3330140118
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1843218219
Short name T617
Test name
Test status
Simulation time 88675485 ps
CPU time 0.92 seconds
Started Aug 08 07:47:05 PM PDT 24
Finished Aug 08 07:47:06 PM PDT 24
Peak memory 206368 kb
Host smart-79029938-0363-472b-b14e-a38b1a26d22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843218219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1843218219
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3976956919
Short name T704
Test name
Test status
Simulation time 368616973 ps
CPU time 3.42 seconds
Started Aug 08 07:47:04 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 224908 kb
Host smart-b64a6c23-9425-4a8e-8468-b6a82a093827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976956919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3976956919
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3240471433
Short name T363
Test name
Test status
Simulation time 39968667 ps
CPU time 0.79 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:46:05 PM PDT 24
Peak memory 205308 kb
Host smart-e71352fe-e2f0-401c-a54d-8a07d95dde64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240471433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
240471433
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2886773478
Short name T248
Test name
Test status
Simulation time 4207565176 ps
CPU time 6.07 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:09 PM PDT 24
Peak memory 233224 kb
Host smart-b1f4afbd-fc9c-4709-b4e6-1522926156c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886773478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2886773478
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2264320428
Short name T724
Test name
Test status
Simulation time 38067055 ps
CPU time 0.74 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:46:06 PM PDT 24
Peak memory 206300 kb
Host smart-151bb4f9-8b58-476f-baa4-95e0dd33436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264320428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2264320428
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.985198083
Short name T581
Test name
Test status
Simulation time 20183809 ps
CPU time 0.76 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:04 PM PDT 24
Peak memory 216160 kb
Host smart-869f5bee-51b4-4315-8821-e564a28c590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985198083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.985198083
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3466357435
Short name T268
Test name
Test status
Simulation time 15078790142 ps
CPU time 130.36 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:48:13 PM PDT 24
Peak memory 250604 kb
Host smart-7ea2fe6b-76e4-4a2e-a2c4-2e17ad963603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466357435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3466357435
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1601674417
Short name T212
Test name
Test status
Simulation time 283497963951 ps
CPU time 397.47 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:52:43 PM PDT 24
Peak memory 257424 kb
Host smart-a52f0407-2d9f-47fc-a5b2-8274a9ad79b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601674417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1601674417
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1303530899
Short name T955
Test name
Test status
Simulation time 603098546 ps
CPU time 7.18 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:46:12 PM PDT 24
Peak memory 233124 kb
Host smart-1160a14e-e3f0-410f-87ac-d4700458d946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303530899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1303530899
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.4047963642
Short name T246
Test name
Test status
Simulation time 30050230346 ps
CPU time 229.12 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:49:54 PM PDT 24
Peak memory 257780 kb
Host smart-538dd43a-c6f2-4f16-b685-5e6fe9f9b65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047963642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.4047963642
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1906435586
Short name T158
Test name
Test status
Simulation time 229066669 ps
CPU time 6.47 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:10 PM PDT 24
Peak memory 233076 kb
Host smart-142d4346-70bd-4a27-8bad-b54f132873af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906435586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1906435586
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3089763570
Short name T330
Test name
Test status
Simulation time 1308788023 ps
CPU time 10.67 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:13 PM PDT 24
Peak memory 224928 kb
Host smart-a4a5a2d0-2022-4ec2-b4a8-9f6012d4aa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089763570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3089763570
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.495497867
Short name T1003
Test name
Test status
Simulation time 69277881 ps
CPU time 2.57 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:05 PM PDT 24
Peak memory 233168 kb
Host smart-19b0b09d-9bba-40ea-8a47-82e1bcd0f885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495497867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
495497867
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2048677432
Short name T901
Test name
Test status
Simulation time 4505795482 ps
CPU time 13.82 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:17 PM PDT 24
Peak memory 225004 kb
Host smart-679d0936-e4b9-448b-9eca-9f3cc2140585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048677432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2048677432
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2666265771
Short name T132
Test name
Test status
Simulation time 91445583 ps
CPU time 4.25 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:07 PM PDT 24
Peak memory 223452 kb
Host smart-c442cdb3-f434-487a-9bd5-50410a08a5bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2666265771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2666265771
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.271248978
Short name T55
Test name
Test status
Simulation time 160401473 ps
CPU time 1.21 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:46:06 PM PDT 24
Peak memory 236892 kb
Host smart-c2929689-ef53-4c05-9147-dc5f08e3904e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271248978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.271248978
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1420519281
Short name T803
Test name
Test status
Simulation time 23430955226 ps
CPU time 202.58 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:49:25 PM PDT 24
Peak memory 235308 kb
Host smart-2f4087e3-98ba-4eea-8cdf-5224ae688170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420519281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1420519281
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3168280233
Short name T357
Test name
Test status
Simulation time 22045382807 ps
CPU time 59 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:47:04 PM PDT 24
Peak memory 221256 kb
Host smart-37cd5d9d-752c-4174-9b8b-4ec5324cd3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168280233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3168280233
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1543814084
Short name T23
Test name
Test status
Simulation time 2394097138 ps
CPU time 6.86 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:10 PM PDT 24
Peak memory 216636 kb
Host smart-eb00ada4-0dc7-4503-9a8e-004bb0f11ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543814084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1543814084
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1778898377
Short name T917
Test name
Test status
Simulation time 1282642755 ps
CPU time 4.19 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:46:09 PM PDT 24
Peak memory 216708 kb
Host smart-66c5deb6-4c19-4186-938a-14bcfdb7aff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778898377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1778898377
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2946944170
Short name T71
Test name
Test status
Simulation time 28368500 ps
CPU time 0.74 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:04 PM PDT 24
Peak memory 206360 kb
Host smart-d498b569-0c1f-4882-b8c4-3751b6425190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946944170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2946944170
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1740527232
Short name T861
Test name
Test status
Simulation time 6931439582 ps
CPU time 22.23 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:46:26 PM PDT 24
Peak memory 233212 kb
Host smart-8ccb7cd9-1408-42f8-96b7-353a389cabf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740527232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1740527232
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1335946468
Short name T392
Test name
Test status
Simulation time 37782590 ps
CPU time 0.69 seconds
Started Aug 08 07:47:13 PM PDT 24
Finished Aug 08 07:47:14 PM PDT 24
Peak memory 205860 kb
Host smart-3cb751cc-c5c2-4192-91fc-b47b60b6fb1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335946468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1335946468
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3047912503
Short name T791
Test name
Test status
Simulation time 984053241 ps
CPU time 4.35 seconds
Started Aug 08 07:47:15 PM PDT 24
Finished Aug 08 07:47:20 PM PDT 24
Peak memory 224920 kb
Host smart-6dc9ea0d-4000-46ba-8268-9e8de373fb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047912503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3047912503
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1612369098
Short name T462
Test name
Test status
Simulation time 19421494 ps
CPU time 0.77 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:08 PM PDT 24
Peak memory 207016 kb
Host smart-6c607979-42b2-4051-bebc-585049954e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612369098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1612369098
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1125013005
Short name T655
Test name
Test status
Simulation time 20979636392 ps
CPU time 95.16 seconds
Started Aug 08 07:47:13 PM PDT 24
Finished Aug 08 07:48:48 PM PDT 24
Peak memory 250616 kb
Host smart-ec411123-a9ae-4119-a19e-0025ebe22380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125013005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1125013005
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1493148577
Short name T111
Test name
Test status
Simulation time 23771603610 ps
CPU time 96.51 seconds
Started Aug 08 07:47:18 PM PDT 24
Finished Aug 08 07:48:55 PM PDT 24
Peak memory 252752 kb
Host smart-eaa868ab-141e-43fc-ae93-92a82bf258ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493148577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1493148577
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.852561875
Short name T914
Test name
Test status
Simulation time 29177223117 ps
CPU time 261.65 seconds
Started Aug 08 07:47:18 PM PDT 24
Finished Aug 08 07:51:40 PM PDT 24
Peak memory 268548 kb
Host smart-e4aa0620-5560-472c-bfb8-c2faa37a5345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852561875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.852561875
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.4134707120
Short name T881
Test name
Test status
Simulation time 221300013 ps
CPU time 3.24 seconds
Started Aug 08 07:47:13 PM PDT 24
Finished Aug 08 07:47:16 PM PDT 24
Peak memory 219324 kb
Host smart-7e305187-2417-45eb-b174-fda294f7dd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134707120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4134707120
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1984473941
Short name T78
Test name
Test status
Simulation time 31648619590 ps
CPU time 142.06 seconds
Started Aug 08 07:47:18 PM PDT 24
Finished Aug 08 07:49:40 PM PDT 24
Peak memory 252128 kb
Host smart-91f0de3f-6806-442e-ade8-4ffd444f36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984473941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1984473941
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2994281738
Short name T856
Test name
Test status
Simulation time 1169123067 ps
CPU time 7.72 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:47:17 PM PDT 24
Peak memory 224884 kb
Host smart-ab439852-3db2-451a-ad12-c1c46cdce312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994281738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2994281738
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3900104996
Short name T425
Test name
Test status
Simulation time 4747295423 ps
CPU time 46.51 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:47:55 PM PDT 24
Peak memory 233184 kb
Host smart-49b27b1e-c751-4003-9ace-da432d18b6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900104996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3900104996
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.543118175
Short name T815
Test name
Test status
Simulation time 295986710 ps
CPU time 3.83 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:47:13 PM PDT 24
Peak memory 224836 kb
Host smart-482d2b01-d6a2-43fc-a8d2-9de8d2ac5708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543118175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.543118175
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2948339412
Short name T920
Test name
Test status
Simulation time 4257931757 ps
CPU time 7.65 seconds
Started Aug 08 07:47:08 PM PDT 24
Finished Aug 08 07:47:16 PM PDT 24
Peak memory 233264 kb
Host smart-5e0abfd3-f1d5-4e97-a7ec-79e433a79c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948339412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2948339412
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.232589777
Short name T358
Test name
Test status
Simulation time 630227947 ps
CPU time 6.36 seconds
Started Aug 08 07:47:16 PM PDT 24
Finished Aug 08 07:47:23 PM PDT 24
Peak memory 219220 kb
Host smart-7d0773d9-335b-4f40-9efc-ed93aa414c21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=232589777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.232589777
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2035965008
Short name T513
Test name
Test status
Simulation time 2677821429 ps
CPU time 28.64 seconds
Started Aug 08 07:47:14 PM PDT 24
Finished Aug 08 07:47:43 PM PDT 24
Peak memory 224952 kb
Host smart-69ec8703-5065-4eaf-815d-e9cd9f58f7e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035965008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2035965008
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3397554791
Short name T480
Test name
Test status
Simulation time 9734816353 ps
CPU time 50.41 seconds
Started Aug 08 07:47:09 PM PDT 24
Finished Aug 08 07:48:00 PM PDT 24
Peak memory 216732 kb
Host smart-b61e8444-b5c1-43e0-8d86-becbcc1cf866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397554791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3397554791
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4240680125
Short name T572
Test name
Test status
Simulation time 664408711 ps
CPU time 5.15 seconds
Started Aug 08 07:47:07 PM PDT 24
Finished Aug 08 07:47:12 PM PDT 24
Peak memory 216688 kb
Host smart-dbf494bf-262f-4008-a0d4-ea064f6f5b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240680125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4240680125
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.184925374
Short name T307
Test name
Test status
Simulation time 59478075 ps
CPU time 1.47 seconds
Started Aug 08 07:47:06 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 216764 kb
Host smart-0d175d42-643a-469d-9aab-bfabd060ce36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184925374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.184925374
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1269943967
Short name T481
Test name
Test status
Simulation time 37209359 ps
CPU time 0.82 seconds
Started Aug 08 07:47:11 PM PDT 24
Finished Aug 08 07:47:12 PM PDT 24
Peak memory 206592 kb
Host smart-0624a3b4-f804-4dbd-a6b5-2b633a9e0783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269943967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1269943967
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.68362810
Short name T535
Test name
Test status
Simulation time 10549458072 ps
CPU time 21.98 seconds
Started Aug 08 07:47:15 PM PDT 24
Finished Aug 08 07:47:37 PM PDT 24
Peak memory 225004 kb
Host smart-76bd31cf-d4ff-46c2-9dea-71dceb69a4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68362810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.68362810
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4251647724
Short name T687
Test name
Test status
Simulation time 11620150 ps
CPU time 0.7 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:28 PM PDT 24
Peak memory 205896 kb
Host smart-a9791f42-0f3b-444e-9066-b557780815eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251647724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4251647724
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.246201760
Short name T446
Test name
Test status
Simulation time 1496761005 ps
CPU time 4.17 seconds
Started Aug 08 07:47:16 PM PDT 24
Finished Aug 08 07:47:20 PM PDT 24
Peak memory 233116 kb
Host smart-13e26853-d07b-48f1-8dde-089ca6d10ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246201760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.246201760
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2353205077
Short name T587
Test name
Test status
Simulation time 98315681 ps
CPU time 0.76 seconds
Started Aug 08 07:47:15 PM PDT 24
Finished Aug 08 07:47:15 PM PDT 24
Peak memory 207012 kb
Host smart-fc3e8e4a-6c1d-4454-8554-390c674c6b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353205077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2353205077
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.467247432
Short name T936
Test name
Test status
Simulation time 9138119017 ps
CPU time 30.75 seconds
Started Aug 08 07:47:16 PM PDT 24
Finished Aug 08 07:47:47 PM PDT 24
Peak memory 249588 kb
Host smart-7f0829f8-cfe2-4a4e-9917-1743cf2ec251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467247432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.467247432
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2150098887
Short name T555
Test name
Test status
Simulation time 10384445956 ps
CPU time 29.31 seconds
Started Aug 08 07:47:25 PM PDT 24
Finished Aug 08 07:47:54 PM PDT 24
Peak memory 225056 kb
Host smart-aa191dfc-ab05-43f8-babf-3b6ca971e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150098887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2150098887
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2338594789
Short name T447
Test name
Test status
Simulation time 19310869330 ps
CPU time 62.51 seconds
Started Aug 08 07:47:26 PM PDT 24
Finished Aug 08 07:48:29 PM PDT 24
Peak memory 246504 kb
Host smart-8145e892-053b-44db-9f78-7fa38b5a343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338594789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2338594789
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2214663340
Short name T892
Test name
Test status
Simulation time 1024807049 ps
CPU time 5.12 seconds
Started Aug 08 07:47:15 PM PDT 24
Finished Aug 08 07:47:20 PM PDT 24
Peak memory 224988 kb
Host smart-c6c12021-8fde-4b51-91e2-cbadea0b7855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214663340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2214663340
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.750122099
Short name T475
Test name
Test status
Simulation time 1341613469 ps
CPU time 15.87 seconds
Started Aug 08 07:47:15 PM PDT 24
Finished Aug 08 07:47:31 PM PDT 24
Peak memory 249516 kb
Host smart-51c8f467-9fd6-4cf3-9534-6fafcb0dc1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750122099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.750122099
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1827456406
Short name T334
Test name
Test status
Simulation time 2816150216 ps
CPU time 23.11 seconds
Started Aug 08 07:47:15 PM PDT 24
Finished Aug 08 07:47:38 PM PDT 24
Peak memory 233184 kb
Host smart-1ad23f78-8112-4f1d-8082-15cfdf1dc4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827456406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1827456406
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2375109203
Short name T197
Test name
Test status
Simulation time 6686476527 ps
CPU time 47.69 seconds
Started Aug 08 07:47:16 PM PDT 24
Finished Aug 08 07:48:04 PM PDT 24
Peak memory 233148 kb
Host smart-a690300e-90d1-4eb9-aba5-8569bc4d3099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375109203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2375109203
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3117382156
Short name T825
Test name
Test status
Simulation time 5092261896 ps
CPU time 17.72 seconds
Started Aug 08 07:47:15 PM PDT 24
Finished Aug 08 07:47:32 PM PDT 24
Peak memory 233204 kb
Host smart-70a91fee-6513-48b6-b0c3-9c658d57e62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117382156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3117382156
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.834298695
Short name T278
Test name
Test status
Simulation time 164863658 ps
CPU time 2.91 seconds
Started Aug 08 07:47:15 PM PDT 24
Finished Aug 08 07:47:18 PM PDT 24
Peak memory 233164 kb
Host smart-03c4e1f5-db98-4a23-94a6-ffcc405bbc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834298695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.834298695
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.4149798357
Short name T800
Test name
Test status
Simulation time 1353499519 ps
CPU time 19.12 seconds
Started Aug 08 07:47:16 PM PDT 24
Finished Aug 08 07:47:35 PM PDT 24
Peak memory 220664 kb
Host smart-4f49630c-09d0-459e-99ea-e67767d518b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4149798357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.4149798357
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2368019971
Short name T934
Test name
Test status
Simulation time 1193501452 ps
CPU time 4.8 seconds
Started Aug 08 07:47:15 PM PDT 24
Finished Aug 08 07:47:19 PM PDT 24
Peak memory 219076 kb
Host smart-917247ca-167b-4356-be9f-0065f9146107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368019971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2368019971
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.339135796
Short name T404
Test name
Test status
Simulation time 9469973332 ps
CPU time 11.78 seconds
Started Aug 08 07:47:14 PM PDT 24
Finished Aug 08 07:47:25 PM PDT 24
Peak memory 216756 kb
Host smart-268b56de-d3d1-4fd9-99f5-beb26d1d760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339135796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.339135796
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2367730298
Short name T559
Test name
Test status
Simulation time 354822405 ps
CPU time 2.09 seconds
Started Aug 08 07:47:14 PM PDT 24
Finished Aug 08 07:47:16 PM PDT 24
Peak memory 216612 kb
Host smart-d4d7ea8b-8ddc-412b-a4cf-d54a628c03bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367730298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2367730298
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.936834319
Short name T326
Test name
Test status
Simulation time 37792610 ps
CPU time 0.79 seconds
Started Aug 08 07:47:18 PM PDT 24
Finished Aug 08 07:47:19 PM PDT 24
Peak memory 206332 kb
Host smart-3809009b-b3f2-4806-9eeb-17c6b0445924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936834319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.936834319
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4147405951
Short name T707
Test name
Test status
Simulation time 1017339852 ps
CPU time 5.1 seconds
Started Aug 08 07:47:16 PM PDT 24
Finished Aug 08 07:47:21 PM PDT 24
Peak memory 235032 kb
Host smart-b4012d86-0727-476f-8c79-34d23a107564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147405951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4147405951
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2452529449
Short name T521
Test name
Test status
Simulation time 22281428 ps
CPU time 0.74 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:28 PM PDT 24
Peak memory 205316 kb
Host smart-d272d21c-bf32-4bca-92d7-b0abece9c7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452529449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2452529449
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1641761545
Short name T615
Test name
Test status
Simulation time 152365668 ps
CPU time 3.79 seconds
Started Aug 08 07:47:24 PM PDT 24
Finished Aug 08 07:47:28 PM PDT 24
Peak memory 233148 kb
Host smart-f2eb4098-0681-48a8-bcc5-d65f6b30b888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641761545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1641761545
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3056304430
Short name T658
Test name
Test status
Simulation time 18234690 ps
CPU time 0.75 seconds
Started Aug 08 07:47:24 PM PDT 24
Finished Aug 08 07:47:25 PM PDT 24
Peak memory 206920 kb
Host smart-507e5bf8-adec-44d5-a80c-f48f7b8e911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056304430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3056304430
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.538692261
Short name T576
Test name
Test status
Simulation time 13820479934 ps
CPU time 103.98 seconds
Started Aug 08 07:47:29 PM PDT 24
Finished Aug 08 07:49:13 PM PDT 24
Peak memory 249680 kb
Host smart-a53aa5c3-5bd3-4056-97ce-a966868c7ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538692261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.538692261
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3603776137
Short name T903
Test name
Test status
Simulation time 5970966453 ps
CPU time 26.83 seconds
Started Aug 08 07:47:31 PM PDT 24
Finished Aug 08 07:47:58 PM PDT 24
Peak memory 225068 kb
Host smart-7da8dbdb-5583-4981-b60c-e714ebd5c166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603776137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3603776137
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.85663570
Short name T178
Test name
Test status
Simulation time 84144653914 ps
CPU time 661.23 seconds
Started Aug 08 07:47:28 PM PDT 24
Finished Aug 08 07:58:30 PM PDT 24
Peak memory 267044 kb
Host smart-bbdcbcbd-2457-4083-923c-1c1375487995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85663570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.85663570
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2443555591
Short name T297
Test name
Test status
Simulation time 10599480940 ps
CPU time 51.74 seconds
Started Aug 08 07:47:26 PM PDT 24
Finished Aug 08 07:48:18 PM PDT 24
Peak memory 254364 kb
Host smart-4bfd7a34-ca40-4e2a-bb48-b65a6ac5615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443555591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2443555591
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2843918823
Short name T872
Test name
Test status
Simulation time 5677306481 ps
CPU time 33.58 seconds
Started Aug 08 07:47:23 PM PDT 24
Finished Aug 08 07:47:57 PM PDT 24
Peak memory 224936 kb
Host smart-ab7e5dc2-de14-41a9-ab12-b1843664ed17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843918823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2843918823
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3765298332
Short name T640
Test name
Test status
Simulation time 2416737943 ps
CPU time 23.72 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:51 PM PDT 24
Peak memory 231852 kb
Host smart-fe91fdea-b284-4465-82c0-d4a81c81bfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765298332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3765298332
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2017637589
Short name T269
Test name
Test status
Simulation time 14408422897 ps
CPU time 26.09 seconds
Started Aug 08 07:47:24 PM PDT 24
Finished Aug 08 07:47:50 PM PDT 24
Peak memory 234356 kb
Host smart-831be3bf-fa47-47f1-aea3-375fef4b3cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017637589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2017637589
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.967050689
Short name T64
Test name
Test status
Simulation time 576715358 ps
CPU time 5.52 seconds
Started Aug 08 07:47:25 PM PDT 24
Finished Aug 08 07:47:31 PM PDT 24
Peak memory 233092 kb
Host smart-d383c91d-a0ca-4e54-8e7d-e2f89980a9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967050689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.967050689
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1455628873
Short name T744
Test name
Test status
Simulation time 1228119214 ps
CPU time 5.02 seconds
Started Aug 08 07:47:25 PM PDT 24
Finished Aug 08 07:47:30 PM PDT 24
Peak memory 233160 kb
Host smart-837a6e9b-ae3b-4d29-91d0-b0f17f34a22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455628873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1455628873
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2674470678
Short name T353
Test name
Test status
Simulation time 2973298244 ps
CPU time 9.39 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:37 PM PDT 24
Peak memory 219828 kb
Host smart-73a6fbb6-cf5c-4b33-bb6e-63dd3c20bea9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2674470678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2674470678
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.939842132
Short name T155
Test name
Test status
Simulation time 7169689358 ps
CPU time 142.06 seconds
Started Aug 08 07:47:26 PM PDT 24
Finished Aug 08 07:49:48 PM PDT 24
Peak memory 273532 kb
Host smart-3cd2210f-46ef-41ef-b297-da057372076e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939842132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.939842132
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1050493927
Short name T887
Test name
Test status
Simulation time 48109718883 ps
CPU time 54.63 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:48:22 PM PDT 24
Peak memory 215292 kb
Host smart-398002ca-cb2d-489c-8b8b-326db1a60d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050493927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1050493927
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3034433385
Short name T470
Test name
Test status
Simulation time 69377909110 ps
CPU time 20.9 seconds
Started Aug 08 07:47:28 PM PDT 24
Finished Aug 08 07:47:49 PM PDT 24
Peak memory 216756 kb
Host smart-9ca5258e-2053-4273-b86e-4774e184d2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034433385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3034433385
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.77801693
Short name T896
Test name
Test status
Simulation time 266892480 ps
CPU time 1.16 seconds
Started Aug 08 07:47:29 PM PDT 24
Finished Aug 08 07:47:30 PM PDT 24
Peak memory 208228 kb
Host smart-e147da20-1301-4e80-9c8c-368b318b4d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77801693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.77801693
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3524061581
Short name T380
Test name
Test status
Simulation time 30596973 ps
CPU time 0.73 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:27 PM PDT 24
Peak memory 206336 kb
Host smart-c705f8a1-6f18-4ae0-be33-97677b9f23a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524061581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3524061581
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3703800450
Short name T625
Test name
Test status
Simulation time 104694954 ps
CPU time 3.3 seconds
Started Aug 08 07:47:26 PM PDT 24
Finished Aug 08 07:47:30 PM PDT 24
Peak memory 224952 kb
Host smart-eb57b64a-ac5c-4517-a73f-c3f0e2f1688e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703800450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3703800450
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3783847987
Short name T385
Test name
Test status
Simulation time 72999174 ps
CPU time 0.72 seconds
Started Aug 08 07:47:30 PM PDT 24
Finished Aug 08 07:47:31 PM PDT 24
Peak memory 205844 kb
Host smart-9e4a66f4-b4c3-4654-8d96-ca283d610611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783847987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3783847987
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2678107031
Short name T583
Test name
Test status
Simulation time 254043480 ps
CPU time 4.26 seconds
Started Aug 08 07:47:29 PM PDT 24
Finished Aug 08 07:47:33 PM PDT 24
Peak memory 233036 kb
Host smart-b9b6f42d-96c7-4d3e-b658-b83e55a575e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678107031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2678107031
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.118028675
Short name T923
Test name
Test status
Simulation time 20791855 ps
CPU time 0.76 seconds
Started Aug 08 07:47:24 PM PDT 24
Finished Aug 08 07:47:25 PM PDT 24
Peak memory 206940 kb
Host smart-470cd6db-6c93-4a8a-a105-92a2441ed68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118028675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.118028675
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1998448279
Short name T519
Test name
Test status
Simulation time 32726468890 ps
CPU time 73.68 seconds
Started Aug 08 07:47:29 PM PDT 24
Finished Aug 08 07:48:43 PM PDT 24
Peak memory 252688 kb
Host smart-aa1802c5-b2c3-4a6c-a174-019e2ec24a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998448279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1998448279
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.719884351
Short name T253
Test name
Test status
Simulation time 72017864805 ps
CPU time 106.53 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:49:14 PM PDT 24
Peak memory 256316 kb
Host smart-315ca8d5-d644-4393-85d4-3e05b08d0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719884351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.719884351
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1780003319
Short name T379
Test name
Test status
Simulation time 10983260856 ps
CPU time 53.26 seconds
Started Aug 08 07:47:24 PM PDT 24
Finished Aug 08 07:48:17 PM PDT 24
Peak memory 225032 kb
Host smart-dd407e05-533a-4344-9c05-17bb47e652bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780003319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1780003319
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1154920373
Short name T826
Test name
Test status
Simulation time 138087333 ps
CPU time 5.18 seconds
Started Aug 08 07:47:24 PM PDT 24
Finished Aug 08 07:47:29 PM PDT 24
Peak memory 224964 kb
Host smart-4911283c-961a-45f6-87de-5cd4ef159e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154920373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1154920373
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1176703152
Short name T219
Test name
Test status
Simulation time 14290956766 ps
CPU time 29.53 seconds
Started Aug 08 07:47:29 PM PDT 24
Finished Aug 08 07:47:58 PM PDT 24
Peak memory 239180 kb
Host smart-8063980b-827d-46da-ba05-b19e0958ac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176703152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1176703152
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2715069680
Short name T431
Test name
Test status
Simulation time 1889279065 ps
CPU time 5.56 seconds
Started Aug 08 07:47:29 PM PDT 24
Finished Aug 08 07:47:35 PM PDT 24
Peak memory 224816 kb
Host smart-0ce74ab5-1b74-49dd-b99a-55b909b460c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715069680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2715069680
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3766126529
Short name T537
Test name
Test status
Simulation time 1146662448 ps
CPU time 20.75 seconds
Started Aug 08 07:47:26 PM PDT 24
Finished Aug 08 07:47:47 PM PDT 24
Peak memory 240912 kb
Host smart-4826ec6a-d87d-4436-9440-b2be88123926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766126529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3766126529
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1654190921
Short name T853
Test name
Test status
Simulation time 1993648280 ps
CPU time 16.27 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:44 PM PDT 24
Peak memory 224920 kb
Host smart-866d2d65-9bc4-4947-963e-36f022032640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654190921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1654190921
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4082892098
Short name T809
Test name
Test status
Simulation time 52765186 ps
CPU time 2.72 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:30 PM PDT 24
Peak memory 233064 kb
Host smart-b43e1781-e144-4717-93e1-f94756b3e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082892098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4082892098
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.298001991
Short name T514
Test name
Test status
Simulation time 1434650920 ps
CPU time 12.58 seconds
Started Aug 08 07:47:25 PM PDT 24
Finished Aug 08 07:47:37 PM PDT 24
Peak memory 219816 kb
Host smart-b2328bcd-7340-4276-a357-b16f2f264042
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=298001991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.298001991
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.263709038
Short name T372
Test name
Test status
Simulation time 148376141 ps
CPU time 1.25 seconds
Started Aug 08 07:47:28 PM PDT 24
Finished Aug 08 07:47:29 PM PDT 24
Peak memory 207536 kb
Host smart-45e261f3-bf87-484b-bdb6-dccb60df9112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263709038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.263709038
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.908640731
Short name T312
Test name
Test status
Simulation time 1175393207 ps
CPU time 16.97 seconds
Started Aug 08 07:47:26 PM PDT 24
Finished Aug 08 07:47:43 PM PDT 24
Peak memory 216944 kb
Host smart-eb93b45d-af8e-4bee-9de9-a21a2ccd98ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908640731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.908640731
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2580813088
Short name T387
Test name
Test status
Simulation time 746581959 ps
CPU time 5.59 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:33 PM PDT 24
Peak memory 216688 kb
Host smart-14d4e606-a1fd-4957-afc9-6f0436b61812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580813088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2580813088
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3072743265
Short name T659
Test name
Test status
Simulation time 212190856 ps
CPU time 3.39 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:31 PM PDT 24
Peak memory 216680 kb
Host smart-39933c35-507b-4c9d-ad54-72c26296f18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072743265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3072743265
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3332820991
Short name T479
Test name
Test status
Simulation time 57888189 ps
CPU time 0.88 seconds
Started Aug 08 07:47:26 PM PDT 24
Finished Aug 08 07:47:27 PM PDT 24
Peak memory 206328 kb
Host smart-7b6fa952-8568-4b1c-86af-96a9d9feb084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332820991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3332820991
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2643061693
Short name T135
Test name
Test status
Simulation time 287616026 ps
CPU time 4.8 seconds
Started Aug 08 07:47:25 PM PDT 24
Finished Aug 08 07:47:30 PM PDT 24
Peak memory 224820 kb
Host smart-ae9c2205-532a-48ca-8fd3-eb6e994c5895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643061693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2643061693
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3870703764
Short name T652
Test name
Test status
Simulation time 79988181 ps
CPU time 0.73 seconds
Started Aug 08 07:47:33 PM PDT 24
Finished Aug 08 07:47:34 PM PDT 24
Peak memory 205272 kb
Host smart-182df332-eea6-4ade-a119-c1cb356e10e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870703764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3870703764
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3598269764
Short name T845
Test name
Test status
Simulation time 217703159 ps
CPU time 2.51 seconds
Started Aug 08 07:47:36 PM PDT 24
Finished Aug 08 07:47:38 PM PDT 24
Peak memory 224924 kb
Host smart-7e26fd50-9878-47a0-ada2-224113999bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598269764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3598269764
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3257472027
Short name T1000
Test name
Test status
Simulation time 21503161 ps
CPU time 0.85 seconds
Started Aug 08 07:47:27 PM PDT 24
Finished Aug 08 07:47:28 PM PDT 24
Peak memory 207316 kb
Host smart-3d59abd7-90d1-4a87-9129-47ebd0318aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257472027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3257472027
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1501815367
Short name T218
Test name
Test status
Simulation time 4279141420 ps
CPU time 46.85 seconds
Started Aug 08 07:47:35 PM PDT 24
Finished Aug 08 07:48:22 PM PDT 24
Peak memory 249644 kb
Host smart-7612440d-1017-4ba6-bd3f-d6ca66c0144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501815367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1501815367
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1723781657
Short name T603
Test name
Test status
Simulation time 29089798652 ps
CPU time 48.47 seconds
Started Aug 08 07:47:35 PM PDT 24
Finished Aug 08 07:48:23 PM PDT 24
Peak memory 249600 kb
Host smart-e8c190c7-b5c2-4d58-845b-ce57c6756abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723781657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1723781657
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.176855025
Short name T494
Test name
Test status
Simulation time 4216034772 ps
CPU time 14.04 seconds
Started Aug 08 07:47:46 PM PDT 24
Finished Aug 08 07:48:00 PM PDT 24
Peak memory 238480 kb
Host smart-bdeb2a99-cf3b-4994-8db8-54b0dc4c1fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176855025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.176855025
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3595083982
Short name T409
Test name
Test status
Simulation time 10469308402 ps
CPU time 75.01 seconds
Started Aug 08 07:47:34 PM PDT 24
Finished Aug 08 07:48:49 PM PDT 24
Peak memory 257780 kb
Host smart-f78b02de-87e9-45d1-bbda-279e9a9ca0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595083982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3595083982
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.899425537
Short name T614
Test name
Test status
Simulation time 28758943 ps
CPU time 2.1 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:47:46 PM PDT 24
Peak memory 223632 kb
Host smart-ac935f36-8484-4068-993b-5a4e85ee9558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899425537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.899425537
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3240729707
Short name T548
Test name
Test status
Simulation time 135342771 ps
CPU time 2.6 seconds
Started Aug 08 07:47:33 PM PDT 24
Finished Aug 08 07:47:36 PM PDT 24
Peak memory 233124 kb
Host smart-d6af0cfc-dea2-4817-943d-801a43bf03f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240729707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3240729707
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1236403821
Short name T580
Test name
Test status
Simulation time 52845518307 ps
CPU time 14.23 seconds
Started Aug 08 07:47:34 PM PDT 24
Finished Aug 08 07:47:48 PM PDT 24
Peak memory 233188 kb
Host smart-96d651c1-de83-4aa5-91e5-2c20a5f7ee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236403821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1236403821
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.78248833
Short name T900
Test name
Test status
Simulation time 115582254 ps
CPU time 4.4 seconds
Started Aug 08 07:47:39 PM PDT 24
Finished Aug 08 07:47:43 PM PDT 24
Peak memory 223060 kb
Host smart-911398c0-6cb9-4535-8abd-631de7dfa95a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78248833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direc
t.78248833
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4099689202
Short name T214
Test name
Test status
Simulation time 14904534644 ps
CPU time 269.9 seconds
Started Aug 08 07:47:39 PM PDT 24
Finished Aug 08 07:52:09 PM PDT 24
Peak memory 273492 kb
Host smart-e1c280e1-0596-4803-9bcc-7b2ae6889db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099689202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4099689202
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3983957842
Short name T948
Test name
Test status
Simulation time 7136326060 ps
CPU time 27.79 seconds
Started Aug 08 07:47:33 PM PDT 24
Finished Aug 08 07:48:01 PM PDT 24
Peak memory 216748 kb
Host smart-ceb9a8c8-9135-466a-864b-d6d2e57ba3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983957842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3983957842
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3477105434
Short name T840
Test name
Test status
Simulation time 2262219905 ps
CPU time 2.27 seconds
Started Aug 08 07:47:26 PM PDT 24
Finished Aug 08 07:47:28 PM PDT 24
Peak memory 208384 kb
Host smart-515021e4-88e8-4a73-873b-b28fadc6012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477105434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3477105434
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3156355958
Short name T877
Test name
Test status
Simulation time 102462385 ps
CPU time 1.5 seconds
Started Aug 08 07:47:36 PM PDT 24
Finished Aug 08 07:47:38 PM PDT 24
Peak memory 216684 kb
Host smart-682dff19-e2ba-4327-a20d-4eace2550327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156355958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3156355958
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.683813646
Short name T980
Test name
Test status
Simulation time 112671085 ps
CPU time 0.78 seconds
Started Aug 08 07:47:36 PM PDT 24
Finished Aug 08 07:47:36 PM PDT 24
Peak memory 206420 kb
Host smart-3f37a91f-488c-4d47-aa4a-5b679f93e048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683813646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.683813646
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3430326107
Short name T283
Test name
Test status
Simulation time 562781046 ps
CPU time 4.49 seconds
Started Aug 08 07:47:34 PM PDT 24
Finished Aug 08 07:47:39 PM PDT 24
Peak memory 224904 kb
Host smart-8e107ffe-4c41-4e1a-8f9a-4ac74741dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430326107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3430326107
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.498372916
Short name T736
Test name
Test status
Simulation time 13202265 ps
CPU time 0.73 seconds
Started Aug 08 07:47:36 PM PDT 24
Finished Aug 08 07:47:36 PM PDT 24
Peak memory 205924 kb
Host smart-c50ca60b-6b93-4c09-8dfe-3d13433d5932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498372916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.498372916
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3828024944
Short name T1007
Test name
Test status
Simulation time 378881013 ps
CPU time 3.19 seconds
Started Aug 08 07:47:34 PM PDT 24
Finished Aug 08 07:47:37 PM PDT 24
Peak memory 233084 kb
Host smart-bc54623a-3e32-4b9e-a908-0190456f118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828024944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3828024944
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3109110030
Short name T7
Test name
Test status
Simulation time 15234225 ps
CPU time 0.76 seconds
Started Aug 08 07:47:33 PM PDT 24
Finished Aug 08 07:47:34 PM PDT 24
Peak memory 206292 kb
Host smart-67904e47-cdcc-4e04-a3e8-70bfa72bfc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109110030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3109110030
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1486463534
Short name T271
Test name
Test status
Simulation time 8806600839 ps
CPU time 74.75 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:48:59 PM PDT 24
Peak memory 257836 kb
Host smart-84c5ac9e-81a8-4232-bef4-8117ff2657cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486463534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1486463534
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.207568744
Short name T217
Test name
Test status
Simulation time 13433744348 ps
CPU time 113.78 seconds
Started Aug 08 07:47:33 PM PDT 24
Finished Aug 08 07:49:27 PM PDT 24
Peak memory 254600 kb
Host smart-8ef9cffd-83e8-427e-a677-235dff2b4aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207568744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.207568744
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2232318807
Short name T27
Test name
Test status
Simulation time 62600477668 ps
CPU time 170.56 seconds
Started Aug 08 07:47:36 PM PDT 24
Finished Aug 08 07:50:26 PM PDT 24
Peak memory 253192 kb
Host smart-10be97e9-f58a-4ed6-938f-76faa7f4eb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232318807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2232318807
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.383850931
Short name T848
Test name
Test status
Simulation time 442394540 ps
CPU time 5.75 seconds
Started Aug 08 07:47:32 PM PDT 24
Finished Aug 08 07:47:38 PM PDT 24
Peak memory 233164 kb
Host smart-33b1cff5-348b-48ea-b079-bf047c426f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383850931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.383850931
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2643411048
Short name T60
Test name
Test status
Simulation time 12564278536 ps
CPU time 117.32 seconds
Started Aug 08 07:47:34 PM PDT 24
Finished Aug 08 07:49:32 PM PDT 24
Peak memory 257272 kb
Host smart-010b6804-0ada-4293-9fae-45e91e0c0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643411048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2643411048
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3901720984
Short name T976
Test name
Test status
Simulation time 30326139 ps
CPU time 2.4 seconds
Started Aug 08 07:47:35 PM PDT 24
Finished Aug 08 07:47:37 PM PDT 24
Peak memory 232840 kb
Host smart-4b4129af-631e-4c24-b382-45aa70fa5e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901720984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3901720984
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.105500012
Short name T518
Test name
Test status
Simulation time 94847278 ps
CPU time 2.14 seconds
Started Aug 08 07:47:35 PM PDT 24
Finished Aug 08 07:47:37 PM PDT 24
Peak memory 224860 kb
Host smart-3cde502a-8d3a-4402-b333-20f81bb2ce93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105500012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.105500012
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3797598134
Short name T913
Test name
Test status
Simulation time 1817345588 ps
CPU time 4.36 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:47:50 PM PDT 24
Peak memory 224956 kb
Host smart-5ee4d282-98de-481a-b93b-1074b3564288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797598134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3797598134
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.659516737
Short name T324
Test name
Test status
Simulation time 8382689402 ps
CPU time 14.54 seconds
Started Aug 08 07:47:36 PM PDT 24
Finished Aug 08 07:47:51 PM PDT 24
Peak memory 233160 kb
Host smart-08e731c3-dae8-4022-b7d2-53e899dd7862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659516737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.659516737
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.718607840
Short name T593
Test name
Test status
Simulation time 840262412 ps
CPU time 5.19 seconds
Started Aug 08 07:47:40 PM PDT 24
Finished Aug 08 07:47:46 PM PDT 24
Peak memory 223708 kb
Host smart-679f231f-1c57-48e9-96af-504e180c61e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=718607840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.718607840
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3098868606
Short name T630
Test name
Test status
Simulation time 22452577014 ps
CPU time 97.65 seconds
Started Aug 08 07:47:36 PM PDT 24
Finished Aug 08 07:49:13 PM PDT 24
Peak memory 254360 kb
Host smart-f8129703-4afc-45fc-be5e-a50be5032472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098868606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3098868606
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2575011213
Short name T300
Test name
Test status
Simulation time 9787076327 ps
CPU time 24.98 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:48:10 PM PDT 24
Peak memory 216728 kb
Host smart-8c1ae458-9ed1-4190-8b49-04eb91f1bb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575011213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2575011213
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3268590066
Short name T310
Test name
Test status
Simulation time 10245099269 ps
CPU time 6.79 seconds
Started Aug 08 07:47:34 PM PDT 24
Finished Aug 08 07:47:40 PM PDT 24
Peak memory 217860 kb
Host smart-6e5e49d8-b2c0-4ff7-84c3-1b1cb25d7b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268590066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3268590066
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1996322123
Short name T336
Test name
Test status
Simulation time 93665522 ps
CPU time 1.61 seconds
Started Aug 08 07:47:35 PM PDT 24
Finished Aug 08 07:47:37 PM PDT 24
Peak memory 216716 kb
Host smart-6d5d5946-e387-45e1-9b7c-bdfb86af3222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996322123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1996322123
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4262431169
Short name T679
Test name
Test status
Simulation time 288065694 ps
CPU time 0.94 seconds
Started Aug 08 07:47:36 PM PDT 24
Finished Aug 08 07:47:37 PM PDT 24
Peak memory 206392 kb
Host smart-4618c257-750a-4b2f-a562-1ac5c4f92f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262431169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4262431169
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2069539803
Short name T575
Test name
Test status
Simulation time 22790414006 ps
CPU time 21.85 seconds
Started Aug 08 07:47:39 PM PDT 24
Finished Aug 08 07:48:01 PM PDT 24
Peak memory 225032 kb
Host smart-27336e64-5b97-40ab-897e-c84ad8a71d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069539803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2069539803
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1384843357
Short name T407
Test name
Test status
Simulation time 105730765 ps
CPU time 0.73 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:47:45 PM PDT 24
Peak memory 205888 kb
Host smart-22eeaf5c-13a9-46de-9d36-692f38cf7c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384843357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1384843357
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.289926250
Short name T642
Test name
Test status
Simulation time 2043114767 ps
CPU time 8.27 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:47:53 PM PDT 24
Peak memory 224944 kb
Host smart-e15d33a7-bb4b-4729-967f-d724c7ba2724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289926250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.289926250
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1519074297
Short name T536
Test name
Test status
Simulation time 76200520 ps
CPU time 0.8 seconds
Started Aug 08 07:47:35 PM PDT 24
Finished Aug 08 07:47:36 PM PDT 24
Peak memory 207000 kb
Host smart-1a809e39-7c07-410a-97e8-1eb0f9a595b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519074297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1519074297
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.363248395
Short name T1006
Test name
Test status
Simulation time 24964394187 ps
CPU time 177.63 seconds
Started Aug 08 07:47:42 PM PDT 24
Finished Aug 08 07:50:39 PM PDT 24
Peak memory 250792 kb
Host smart-d7eb5821-357d-4cf6-beec-865ac91323fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363248395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.363248395
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1033833661
Short name T274
Test name
Test status
Simulation time 18362077010 ps
CPU time 80.38 seconds
Started Aug 08 07:47:43 PM PDT 24
Finished Aug 08 07:49:03 PM PDT 24
Peak memory 256852 kb
Host smart-5b6696c2-2670-4782-b458-4edfab919ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033833661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1033833661
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1417384368
Short name T748
Test name
Test status
Simulation time 559998183 ps
CPU time 10.93 seconds
Started Aug 08 07:47:46 PM PDT 24
Finished Aug 08 07:47:57 PM PDT 24
Peak memory 224908 kb
Host smart-d2d78581-5fdb-44e2-b7f3-1c4cf15d6048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417384368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1417384368
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.4189246837
Short name T952
Test name
Test status
Simulation time 7548421782 ps
CPU time 22.91 seconds
Started Aug 08 07:47:42 PM PDT 24
Finished Aug 08 07:48:05 PM PDT 24
Peak memory 241368 kb
Host smart-0e52d21a-bbd8-4909-97ee-ab8e24cc134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189246837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.4189246837
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3442372162
Short name T841
Test name
Test status
Simulation time 1304243443 ps
CPU time 4.84 seconds
Started Aug 08 07:47:40 PM PDT 24
Finished Aug 08 07:47:45 PM PDT 24
Peak memory 233208 kb
Host smart-c5389734-adba-4c74-b2e1-55afca94950d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442372162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3442372162
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3905227165
Short name T958
Test name
Test status
Simulation time 1123258935 ps
CPU time 20.9 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:48:06 PM PDT 24
Peak memory 224928 kb
Host smart-355988b7-694c-433e-89ae-31bcab67dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905227165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3905227165
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3948054914
Short name T820
Test name
Test status
Simulation time 7427743296 ps
CPU time 20.76 seconds
Started Aug 08 07:47:37 PM PDT 24
Finished Aug 08 07:47:58 PM PDT 24
Peak memory 233216 kb
Host smart-6513555c-3837-48aa-a459-c78e42ec33c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948054914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3948054914
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1295769456
Short name T968
Test name
Test status
Simulation time 407306566 ps
CPU time 2.3 seconds
Started Aug 08 07:47:46 PM PDT 24
Finished Aug 08 07:47:48 PM PDT 24
Peak memory 224872 kb
Host smart-39faebcf-c3f8-4b1e-bf89-7a0d7cfa5ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295769456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1295769456
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2602208650
Short name T133
Test name
Test status
Simulation time 118689635 ps
CPU time 3.23 seconds
Started Aug 08 07:47:43 PM PDT 24
Finished Aug 08 07:47:47 PM PDT 24
Peak memory 219228 kb
Host smart-a5211f22-b85d-4e74-bb0f-1c4ba24c297b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2602208650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2602208650
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2390940922
Short name T990
Test name
Test status
Simulation time 30153961355 ps
CPU time 305.34 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:52:49 PM PDT 24
Peak memory 267028 kb
Host smart-c8b0cc52-bee3-4769-adfb-b127eb445bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390940922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2390940922
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.797270660
Short name T812
Test name
Test status
Simulation time 1253114663 ps
CPU time 9.27 seconds
Started Aug 08 07:47:35 PM PDT 24
Finished Aug 08 07:47:44 PM PDT 24
Peak memory 216728 kb
Host smart-42f39e8f-5aea-47b5-8087-d763cf305bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797270660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.797270660
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1056162389
Short name T994
Test name
Test status
Simulation time 4341184148 ps
CPU time 8.38 seconds
Started Aug 08 07:47:46 PM PDT 24
Finished Aug 08 07:47:54 PM PDT 24
Peak memory 216792 kb
Host smart-e3626bce-6617-42af-95aa-df9ec47978b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056162389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1056162389
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.966638813
Short name T692
Test name
Test status
Simulation time 121980221 ps
CPU time 1 seconds
Started Aug 08 07:47:37 PM PDT 24
Finished Aug 08 07:47:38 PM PDT 24
Peak memory 208028 kb
Host smart-2c5d88e2-c61a-4933-874c-307a8162668b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966638813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.966638813
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1220985360
Short name T319
Test name
Test status
Simulation time 12756533 ps
CPU time 0.7 seconds
Started Aug 08 07:47:35 PM PDT 24
Finished Aug 08 07:47:36 PM PDT 24
Peak memory 205952 kb
Host smart-9ddcf489-9d2b-4530-a60d-dc7ce8eba96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220985360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1220985360
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2819072149
Short name T804
Test name
Test status
Simulation time 332230036 ps
CPU time 2.35 seconds
Started Aug 08 07:47:55 PM PDT 24
Finished Aug 08 07:47:57 PM PDT 24
Peak memory 225016 kb
Host smart-9ea6cd38-0544-4304-b32e-08e3d0a8efcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819072149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2819072149
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2263527702
Short name T916
Test name
Test status
Simulation time 27990797 ps
CPU time 0.73 seconds
Started Aug 08 07:47:43 PM PDT 24
Finished Aug 08 07:47:44 PM PDT 24
Peak memory 205872 kb
Host smart-97b77982-2ee7-4f11-89b4-38f83cc43ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263527702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2263527702
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1920507037
Short name T868
Test name
Test status
Simulation time 291152127 ps
CPU time 4.72 seconds
Started Aug 08 07:47:55 PM PDT 24
Finished Aug 08 07:48:00 PM PDT 24
Peak memory 224948 kb
Host smart-6aba2657-25f2-4193-b871-9c12c72a9b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920507037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1920507037
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3786436542
Short name T348
Test name
Test status
Simulation time 22435519 ps
CPU time 0.82 seconds
Started Aug 08 07:47:43 PM PDT 24
Finished Aug 08 07:47:44 PM PDT 24
Peak memory 206984 kb
Host smart-d5c037db-cc95-42e6-bb7f-97501a0c22c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786436542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3786436542
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.4156855974
Short name T234
Test name
Test status
Simulation time 28551640987 ps
CPU time 181.72 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:50:47 PM PDT 24
Peak memory 265952 kb
Host smart-e72d0ac9-2243-4321-95eb-da89f16d0689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156855974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4156855974
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2163145800
Short name T515
Test name
Test status
Simulation time 1064076789 ps
CPU time 16.89 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:48:01 PM PDT 24
Peak memory 224904 kb
Host smart-6ddcb242-f0d8-474b-9ed0-1e731d562877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163145800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2163145800
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1409136734
Short name T485
Test name
Test status
Simulation time 3224637908 ps
CPU time 58.96 seconds
Started Aug 08 07:47:43 PM PDT 24
Finished Aug 08 07:48:42 PM PDT 24
Peak memory 252292 kb
Host smart-7a7d859a-fd58-4075-85be-6ed71b45fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409136734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1409136734
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2358321657
Short name T296
Test name
Test status
Simulation time 1700919171 ps
CPU time 15.87 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:48:01 PM PDT 24
Peak memory 224892 kb
Host smart-37ef8150-6a5d-4b99-8e31-24595e5cbbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358321657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2358321657
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4096042122
Short name T79
Test name
Test status
Simulation time 48911638518 ps
CPU time 108.9 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:49:33 PM PDT 24
Peak memory 253136 kb
Host smart-0c0824a2-962d-45db-acfe-7e15ac4e92fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096042122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4096042122
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2179815325
Short name T600
Test name
Test status
Simulation time 1996228248 ps
CPU time 11.24 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:47:56 PM PDT 24
Peak memory 233204 kb
Host smart-c704dd1a-fe28-4021-8fe8-bbdb48930e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179815325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2179815325
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.817765088
Short name T638
Test name
Test status
Simulation time 1140891968 ps
CPU time 12.79 seconds
Started Aug 08 07:47:42 PM PDT 24
Finished Aug 08 07:47:55 PM PDT 24
Peak memory 233188 kb
Host smart-8f7791c2-0e24-4ceb-98ab-a0a5480760bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817765088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.817765088
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1510769744
Short name T693
Test name
Test status
Simulation time 9150988313 ps
CPU time 8.44 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:47:52 PM PDT 24
Peak memory 225016 kb
Host smart-8b8191aa-4455-40e5-8ecc-b50b557377ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510769744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1510769744
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.64641016
Short name T539
Test name
Test status
Simulation time 1503817023 ps
CPU time 4.72 seconds
Started Aug 08 07:47:43 PM PDT 24
Finished Aug 08 07:47:48 PM PDT 24
Peak memory 233136 kb
Host smart-ea49a99a-5978-4d7c-9a1f-e9527b5a76f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64641016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.64641016
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3045221982
Short name T771
Test name
Test status
Simulation time 1502730622 ps
CPU time 18.36 seconds
Started Aug 08 07:47:55 PM PDT 24
Finished Aug 08 07:48:13 PM PDT 24
Peak memory 222556 kb
Host smart-f90eaf4c-3c93-4f61-a004-76f185514b4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3045221982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3045221982
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4207028610
Short name T908
Test name
Test status
Simulation time 91599486524 ps
CPU time 144.53 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:50:09 PM PDT 24
Peak memory 254112 kb
Host smart-a6ef6147-2f6f-46dc-9559-3256d7ee5622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207028610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4207028610
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2751224416
Short name T635
Test name
Test status
Simulation time 463460193 ps
CPU time 3.25 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:47:47 PM PDT 24
Peak memory 217004 kb
Host smart-e6c47a62-0a79-474b-be11-e17cfd6c7910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751224416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2751224416
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.336430312
Short name T813
Test name
Test status
Simulation time 8785138555 ps
CPU time 21.84 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:48:07 PM PDT 24
Peak memory 216824 kb
Host smart-7d551bc9-b492-414f-8a7a-61a34433f8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336430312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.336430312
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.17099060
Short name T24
Test name
Test status
Simulation time 332200305 ps
CPU time 2.75 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:47:47 PM PDT 24
Peak memory 216716 kb
Host smart-47d2a753-de91-43e8-82fa-3fb7307aba37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17099060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.17099060
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4165719055
Short name T677
Test name
Test status
Simulation time 36846364 ps
CPU time 0.69 seconds
Started Aug 08 07:47:43 PM PDT 24
Finished Aug 08 07:47:43 PM PDT 24
Peak memory 206020 kb
Host smart-ef8055ca-7687-420e-a558-9b94f68b4461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165719055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4165719055
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2228160260
Short name T735
Test name
Test status
Simulation time 1181108088 ps
CPU time 5.36 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:47:51 PM PDT 24
Peak memory 224960 kb
Host smart-670e5247-d50c-4301-8a9b-e067bf883c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228160260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2228160260
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3460216716
Short name T567
Test name
Test status
Simulation time 25634383 ps
CPU time 0.71 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:47:54 PM PDT 24
Peak memory 205920 kb
Host smart-0eef5cb6-41de-41fd-893e-1066c2135fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460216716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3460216716
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2435324878
Short name T371
Test name
Test status
Simulation time 50273684 ps
CPU time 2.67 seconds
Started Aug 08 07:47:51 PM PDT 24
Finished Aug 08 07:47:54 PM PDT 24
Peak memory 233128 kb
Host smart-cdfe0699-b0c7-483c-b739-0b5d98154333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435324878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2435324878
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.769054928
Short name T507
Test name
Test status
Simulation time 60893208 ps
CPU time 0.78 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:47:46 PM PDT 24
Peak memory 207280 kb
Host smart-685fa7c5-ac5f-40ee-879a-7f4ead98b423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769054928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.769054928
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1155480050
Short name T36
Test name
Test status
Simulation time 10916048234 ps
CPU time 76.54 seconds
Started Aug 08 07:47:56 PM PDT 24
Finished Aug 08 07:49:12 PM PDT 24
Peak memory 249612 kb
Host smart-30ea15d2-3c97-4982-97ef-344686b5f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155480050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1155480050
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.766520706
Short name T866
Test name
Test status
Simulation time 33159165108 ps
CPU time 106.87 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:49:41 PM PDT 24
Peak memory 251616 kb
Host smart-29133e69-6948-4ddb-a15f-27ade30b6825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766520706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.766520706
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2573228915
Short name T725
Test name
Test status
Simulation time 101264500886 ps
CPU time 75.11 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:49:09 PM PDT 24
Peak memory 249660 kb
Host smart-7076f0e0-14f9-438e-988a-044c712296f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573228915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2573228915
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1605079113
Short name T366
Test name
Test status
Simulation time 86363923 ps
CPU time 2.77 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:47:55 PM PDT 24
Peak memory 224940 kb
Host smart-b55dbc3b-437b-4d1a-bdb6-814d3cdabad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605079113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1605079113
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2082537291
Short name T118
Test name
Test status
Simulation time 10715913 ps
CPU time 0.78 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:47:53 PM PDT 24
Peak memory 216132 kb
Host smart-e59190a2-75ed-40c5-8f6b-acc8f892b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082537291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2082537291
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.328488394
Short name T273
Test name
Test status
Simulation time 369776870 ps
CPU time 3.1 seconds
Started Aug 08 07:47:43 PM PDT 24
Finished Aug 08 07:47:46 PM PDT 24
Peak memory 219384 kb
Host smart-af8ef0ba-4c97-4d5e-aaee-c65bdd74ea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328488394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.328488394
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3364183349
Short name T188
Test name
Test status
Simulation time 62072911133 ps
CPU time 54.94 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:48:48 PM PDT 24
Peak memory 225016 kb
Host smart-5e378bf3-0f6b-4488-8b1a-18b360ecf77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364183349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3364183349
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1664304164
Short name T999
Test name
Test status
Simulation time 1122154472 ps
CPU time 3.44 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:47:49 PM PDT 24
Peak memory 233176 kb
Host smart-faff15f1-f959-453c-b87c-c4471b1cdce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664304164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1664304164
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1135354591
Short name T595
Test name
Test status
Simulation time 678317734 ps
CPU time 6.07 seconds
Started Aug 08 07:47:42 PM PDT 24
Finished Aug 08 07:47:48 PM PDT 24
Peak memory 233196 kb
Host smart-9a05734c-a195-47c3-8e53-c476154318ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135354591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1135354591
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2102925604
Short name T880
Test name
Test status
Simulation time 923140804 ps
CPU time 6.29 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:47:58 PM PDT 24
Peak memory 220800 kb
Host smart-a570591a-eeeb-4db3-912c-15bc159bafd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2102925604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2102925604
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1045970618
Short name T979
Test name
Test status
Simulation time 147426918064 ps
CPU time 294.09 seconds
Started Aug 08 07:47:51 PM PDT 24
Finished Aug 08 07:52:45 PM PDT 24
Peak memory 253512 kb
Host smart-ebaa148b-320d-479e-bb39-79872b8c9143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045970618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1045970618
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3910975683
Short name T993
Test name
Test status
Simulation time 1096966310 ps
CPU time 13.26 seconds
Started Aug 08 07:47:44 PM PDT 24
Finished Aug 08 07:47:57 PM PDT 24
Peak memory 216652 kb
Host smart-576fe892-6c94-4a96-9b95-486617815fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910975683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3910975683
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4026944940
Short name T927
Test name
Test status
Simulation time 2514370151 ps
CPU time 5.27 seconds
Started Aug 08 07:47:45 PM PDT 24
Finished Aug 08 07:47:51 PM PDT 24
Peak memory 216724 kb
Host smart-921b40e1-09f5-4d47-a083-02597ab24334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026944940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4026944940
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3602401437
Short name T982
Test name
Test status
Simulation time 38266474 ps
CPU time 1.44 seconds
Started Aug 08 07:47:42 PM PDT 24
Finished Aug 08 07:47:44 PM PDT 24
Peak memory 216744 kb
Host smart-2fe94110-2a38-4ce7-8ae1-449a51d79832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602401437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3602401437
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1472226176
Short name T331
Test name
Test status
Simulation time 141325936 ps
CPU time 0.77 seconds
Started Aug 08 07:47:55 PM PDT 24
Finished Aug 08 07:47:56 PM PDT 24
Peak memory 206420 kb
Host smart-d53a426f-dbe7-4d5a-91bb-8a4d0113ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472226176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1472226176
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.22463399
Short name T389
Test name
Test status
Simulation time 897237272 ps
CPU time 4.33 seconds
Started Aug 08 07:47:50 PM PDT 24
Finished Aug 08 07:47:54 PM PDT 24
Peak memory 224912 kb
Host smart-ff18bb33-fc60-4067-b643-86654f61bbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22463399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.22463399
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4234930687
Short name T599
Test name
Test status
Simulation time 30533169 ps
CPU time 0.74 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:47:55 PM PDT 24
Peak memory 205312 kb
Host smart-4b08f622-8273-4e75-92fd-4550e7ef099f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234930687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4234930687
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3135593840
Short name T538
Test name
Test status
Simulation time 1326100656 ps
CPU time 6.72 seconds
Started Aug 08 07:47:51 PM PDT 24
Finished Aug 08 07:47:57 PM PDT 24
Peak memory 224996 kb
Host smart-0082bf0b-1c22-4077-beea-e684ebdd951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135593840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3135593840
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2374158747
Short name T699
Test name
Test status
Simulation time 13042653 ps
CPU time 0.74 seconds
Started Aug 08 07:47:51 PM PDT 24
Finished Aug 08 07:47:52 PM PDT 24
Peak memory 206248 kb
Host smart-4b79f5f3-2e1f-4c00-9f36-06f5ce7ddfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374158747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2374158747
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1299174159
Short name T882
Test name
Test status
Simulation time 5658179404 ps
CPU time 40.6 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:48:35 PM PDT 24
Peak memory 250756 kb
Host smart-58c57b97-cf8f-4aa5-a07c-703117b0848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299174159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1299174159
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1999641889
Short name T432
Test name
Test status
Simulation time 33419038117 ps
CPU time 320.65 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:53:14 PM PDT 24
Peak memory 249652 kb
Host smart-8bab8ea3-eb7c-4c5b-8b23-ccf54b020b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999641889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1999641889
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1818631668
Short name T65
Test name
Test status
Simulation time 178664788 ps
CPU time 2.59 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:47:55 PM PDT 24
Peak memory 233156 kb
Host smart-751780b4-0594-40e0-b0fe-dbd5dc9b05af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818631668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1818631668
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1634655576
Short name T851
Test name
Test status
Simulation time 3552624892 ps
CPU time 50.83 seconds
Started Aug 08 07:47:56 PM PDT 24
Finished Aug 08 07:48:47 PM PDT 24
Peak memory 249820 kb
Host smart-baae2f8d-2417-4a61-b3b3-8e1dae1ce206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634655576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1634655576
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2357779711
Short name T452
Test name
Test status
Simulation time 168742507 ps
CPU time 5.05 seconds
Started Aug 08 07:47:51 PM PDT 24
Finished Aug 08 07:47:56 PM PDT 24
Peak memory 224900 kb
Host smart-9c9d5db5-5f3a-4608-a3cb-69ba643bb739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357779711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2357779711
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1305830450
Short name T647
Test name
Test status
Simulation time 4844470542 ps
CPU time 23.29 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:48:15 PM PDT 24
Peak memory 233208 kb
Host smart-954910d8-56d8-4025-b12d-a4fab391fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305830450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1305830450
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1126314313
Short name T154
Test name
Test status
Simulation time 169106928 ps
CPU time 3.56 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:47:58 PM PDT 24
Peak memory 225016 kb
Host smart-4f2f912b-368b-409f-add4-60a1ebbda721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126314313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1126314313
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1226657339
Short name T650
Test name
Test status
Simulation time 4780409494 ps
CPU time 9.59 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:48:03 PM PDT 24
Peak memory 241068 kb
Host smart-7179c277-7ec6-4c9d-9460-f6ce1db33cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226657339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1226657339
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2615874436
Short name T850
Test name
Test status
Simulation time 516364770 ps
CPU time 8.08 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:48:00 PM PDT 24
Peak memory 223600 kb
Host smart-4cf31eb7-a123-488b-a5dc-c126799552f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2615874436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2615874436
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.713710120
Short name T21
Test name
Test status
Simulation time 10014995954 ps
CPU time 102.47 seconds
Started Aug 08 07:47:56 PM PDT 24
Finished Aug 08 07:49:38 PM PDT 24
Peak memory 249660 kb
Host smart-72272be7-1447-44ef-8212-449493769168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713710120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.713710120
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3540532737
Short name T570
Test name
Test status
Simulation time 10353682708 ps
CPU time 12.41 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:48:05 PM PDT 24
Peak memory 220312 kb
Host smart-a2046099-8849-45c4-a4ae-09f1bb00de86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540532737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3540532737
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.922512480
Short name T323
Test name
Test status
Simulation time 1308451688 ps
CPU time 3.89 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:47:56 PM PDT 24
Peak memory 216724 kb
Host smart-d58601ff-af26-4ae9-aacb-4c42c6bb4ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922512480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.922512480
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.769037787
Short name T729
Test name
Test status
Simulation time 545303374 ps
CPU time 8.56 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:48:02 PM PDT 24
Peak memory 216732 kb
Host smart-d3135add-fbe6-4eed-b81c-0fbe098d22b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769037787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.769037787
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3883798690
Short name T956
Test name
Test status
Simulation time 810879146 ps
CPU time 1.01 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:47:55 PM PDT 24
Peak memory 206380 kb
Host smart-2ba0aec6-81bd-4afd-a680-91745d4fa277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883798690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3883798690
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3584312295
Short name T473
Test name
Test status
Simulation time 3830562454 ps
CPU time 7.91 seconds
Started Aug 08 07:47:56 PM PDT 24
Finished Aug 08 07:48:04 PM PDT 24
Peak memory 233272 kb
Host smart-0eb31ab1-fbd5-4d19-a521-4088adf1b243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584312295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3584312295
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1136564510
Short name T811
Test name
Test status
Simulation time 15836745 ps
CPU time 0.74 seconds
Started Aug 08 07:46:15 PM PDT 24
Finished Aug 08 07:46:16 PM PDT 24
Peak memory 206388 kb
Host smart-033bc567-f8e0-4aa7-a2f0-1f66dcdfc76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136564510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
136564510
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3730222635
Short name T949
Test name
Test status
Simulation time 1169395961 ps
CPU time 9.37 seconds
Started Aug 08 07:46:12 PM PDT 24
Finished Aug 08 07:46:22 PM PDT 24
Peak memory 224940 kb
Host smart-5f99c6d7-2f67-41dc-b73c-f714755b1ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730222635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3730222635
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2000405957
Short name T910
Test name
Test status
Simulation time 41403526 ps
CPU time 0.77 seconds
Started Aug 08 07:46:12 PM PDT 24
Finished Aug 08 07:46:13 PM PDT 24
Peak memory 206008 kb
Host smart-639298c1-b780-4481-8d31-987c9b77e40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000405957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2000405957
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3917729491
Short name T16
Test name
Test status
Simulation time 1126835491 ps
CPU time 15.75 seconds
Started Aug 08 07:46:14 PM PDT 24
Finished Aug 08 07:46:29 PM PDT 24
Peak memory 234692 kb
Host smart-02d2ed9f-e504-46c1-952d-2211b44cc799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917729491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3917729491
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2505808958
Short name T394
Test name
Test status
Simulation time 2637536896 ps
CPU time 53.61 seconds
Started Aug 08 07:46:13 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 251224 kb
Host smart-4ec66751-4302-4984-aca5-a73e1b9636e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505808958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2505808958
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3688039240
Short name T290
Test name
Test status
Simulation time 1754977998 ps
CPU time 27.88 seconds
Started Aug 08 07:46:16 PM PDT 24
Finished Aug 08 07:46:44 PM PDT 24
Peak memory 233148 kb
Host smart-c213bbe1-733e-480a-a2cd-3cdef0207a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688039240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3688039240
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2821856993
Short name T706
Test name
Test status
Simulation time 55880166462 ps
CPU time 109.83 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:48:10 PM PDT 24
Peak memory 251228 kb
Host smart-5a5e9644-fb41-47a7-86ce-12e9bb238718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821856993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2821856993
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.497077414
Short name T467
Test name
Test status
Simulation time 3776006334 ps
CPU time 16.94 seconds
Started Aug 08 07:46:17 PM PDT 24
Finished Aug 08 07:46:34 PM PDT 24
Peak memory 233252 kb
Host smart-6d47b50c-e643-4408-85f3-6ab05fdb8a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497077414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.497077414
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4123622413
Short name T852
Test name
Test status
Simulation time 1118830210 ps
CPU time 9.75 seconds
Started Aug 08 07:46:15 PM PDT 24
Finished Aug 08 07:46:25 PM PDT 24
Peak memory 233124 kb
Host smart-f5e8a36a-5552-4987-8f3d-13df6c75b1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123622413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4123622413
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2694784476
Short name T944
Test name
Test status
Simulation time 1362563548 ps
CPU time 5.9 seconds
Started Aug 08 07:46:19 PM PDT 24
Finished Aug 08 07:46:25 PM PDT 24
Peak memory 233144 kb
Host smart-81cd0da5-6910-43db-a4e0-a7caca9c0bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694784476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2694784476
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3318394813
Short name T259
Test name
Test status
Simulation time 2530292264 ps
CPU time 4.02 seconds
Started Aug 08 07:46:19 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 233180 kb
Host smart-ad6a11ef-c2f1-4494-ba02-d378096b61d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318394813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3318394813
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1978011654
Short name T978
Test name
Test status
Simulation time 804674531 ps
CPU time 9.42 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:29 PM PDT 24
Peak memory 222004 kb
Host smart-8b511065-6d3b-4f72-8ec7-354d5d9a5353
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1978011654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1978011654
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2421395041
Short name T57
Test name
Test status
Simulation time 283618916 ps
CPU time 1.26 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:22 PM PDT 24
Peak memory 236424 kb
Host smart-392fd478-3848-496d-8a4c-e58c66cf04d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421395041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2421395041
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.181413327
Short name T19
Test name
Test status
Simulation time 2253913028 ps
CPU time 32.31 seconds
Started Aug 08 07:46:12 PM PDT 24
Finished Aug 08 07:46:44 PM PDT 24
Peak memory 249668 kb
Host smart-85d26903-8b39-48f2-9435-99b4a716b7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181413327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.181413327
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.882696838
Short name T391
Test name
Test status
Simulation time 651410658 ps
CPU time 5.79 seconds
Started Aug 08 07:46:12 PM PDT 24
Finished Aug 08 07:46:18 PM PDT 24
Peak memory 218588 kb
Host smart-6d1f987d-6661-4a94-af03-87b0bf000f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882696838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.882696838
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.753329102
Short name T937
Test name
Test status
Simulation time 8175292738 ps
CPU time 7.01 seconds
Started Aug 08 07:46:17 PM PDT 24
Finished Aug 08 07:46:24 PM PDT 24
Peak memory 216772 kb
Host smart-68165297-286d-4da2-aa21-2a8a46c84ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753329102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.753329102
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1911063808
Short name T474
Test name
Test status
Simulation time 72914010 ps
CPU time 1.54 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:22 PM PDT 24
Peak memory 216596 kb
Host smart-8ed8e022-000a-49d7-8be2-72d6bf537a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911063808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1911063808
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2934612474
Short name T448
Test name
Test status
Simulation time 184808830 ps
CPU time 0.79 seconds
Started Aug 08 07:46:12 PM PDT 24
Finished Aug 08 07:46:13 PM PDT 24
Peak memory 206324 kb
Host smart-089435d6-d73f-4575-ae8b-582c7bea4b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934612474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2934612474
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1483869418
Short name T798
Test name
Test status
Simulation time 294776160 ps
CPU time 2.76 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 241356 kb
Host smart-79d73318-4e37-4bc2-8ddb-b4afbb539dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483869418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1483869418
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.31039374
Short name T586
Test name
Test status
Simulation time 11940534 ps
CPU time 0.72 seconds
Started Aug 08 07:47:55 PM PDT 24
Finished Aug 08 07:47:56 PM PDT 24
Peak memory 205284 kb
Host smart-010ee796-53cd-4ef4-adb4-0cdca69d8ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31039374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.31039374
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3435635399
Short name T528
Test name
Test status
Simulation time 53862809 ps
CPU time 2.58 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:47:55 PM PDT 24
Peak memory 232860 kb
Host smart-510231ba-9199-47dc-9bea-fd049ecd8cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435635399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3435635399
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2477462085
Short name T318
Test name
Test status
Simulation time 21544910 ps
CPU time 0.8 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:47:55 PM PDT 24
Peak memory 205636 kb
Host smart-777af029-1f3e-4f9d-9d55-7842b4ca0407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477462085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2477462085
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.974053609
Short name T781
Test name
Test status
Simulation time 9146278593 ps
CPU time 59.07 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:48:52 PM PDT 24
Peak memory 251256 kb
Host smart-9c4c174a-b6ba-4f5c-a6d9-be8c8001c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974053609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.974053609
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.4216333245
Short name T847
Test name
Test status
Simulation time 42197786310 ps
CPU time 280.5 seconds
Started Aug 08 07:47:56 PM PDT 24
Finished Aug 08 07:52:37 PM PDT 24
Peak memory 273624 kb
Host smart-4a1e8bfa-d843-4d9b-9141-a2f9d822f77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216333245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.4216333245
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3041348428
Short name T963
Test name
Test status
Simulation time 2571551493 ps
CPU time 12.1 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:48:05 PM PDT 24
Peak memory 233156 kb
Host smart-dc5fd7c6-c6ab-45a2-a5c1-2ac02fcfc14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041348428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3041348428
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1454135238
Short name T287
Test name
Test status
Simulation time 403350215808 ps
CPU time 257.05 seconds
Started Aug 08 07:47:56 PM PDT 24
Finished Aug 08 07:52:13 PM PDT 24
Peak memory 252372 kb
Host smart-a40dfa9c-5661-4f58-9e3f-8996ba1c5e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454135238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1454135238
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2783286076
Short name T195
Test name
Test status
Simulation time 22215384450 ps
CPU time 15.68 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:48:08 PM PDT 24
Peak memory 219524 kb
Host smart-218bf954-6a57-4281-9edf-3e22c1f2c865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783286076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2783286076
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4102741205
Short name T954
Test name
Test status
Simulation time 8702810207 ps
CPU time 26.05 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:48:18 PM PDT 24
Peak memory 236152 kb
Host smart-53cc7bf7-f8fc-4ce8-8324-0b493e1f06d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102741205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4102741205
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.521850006
Short name T223
Test name
Test status
Simulation time 401971141 ps
CPU time 2.76 seconds
Started Aug 08 07:47:51 PM PDT 24
Finished Aug 08 07:47:54 PM PDT 24
Peak memory 224964 kb
Host smart-14689831-a672-4723-ab39-5c8537f40f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521850006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.521850006
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4254311993
Short name T30
Test name
Test status
Simulation time 10868961487 ps
CPU time 17.92 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:48:11 PM PDT 24
Peak memory 236104 kb
Host smart-3cdf5ad3-2532-4c69-9e59-a544bfe59aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254311993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4254311993
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2137355896
Short name T830
Test name
Test status
Simulation time 1182979733 ps
CPU time 14.93 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:48:09 PM PDT 24
Peak memory 219508 kb
Host smart-d10d847f-78cf-43ad-968f-6c598fbf210d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2137355896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2137355896
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4206836470
Short name T145
Test name
Test status
Simulation time 374100639533 ps
CPU time 738.97 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 08:00:14 PM PDT 24
Peak memory 265260 kb
Host smart-e14ea452-3298-4a30-8867-fa1db92e6362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206836470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4206836470
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2951401352
Short name T632
Test name
Test status
Simulation time 3261606011 ps
CPU time 22.36 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:48:14 PM PDT 24
Peak memory 216732 kb
Host smart-c5f5bf67-aee3-40a0-94ba-da5b546a56da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951401352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2951401352
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.960923527
Short name T717
Test name
Test status
Simulation time 2142341240 ps
CPU time 3.91 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:47:58 PM PDT 24
Peak memory 216732 kb
Host smart-a84cde7a-3b83-47c5-a6b3-35148cca8f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960923527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.960923527
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4141807745
Short name T584
Test name
Test status
Simulation time 139309379 ps
CPU time 1.04 seconds
Started Aug 08 07:47:57 PM PDT 24
Finished Aug 08 07:47:58 PM PDT 24
Peak memory 207396 kb
Host smart-541ba865-410c-40e4-96c8-4b8e4a813df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141807745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4141807745
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.439364033
Short name T619
Test name
Test status
Simulation time 108677487 ps
CPU time 0.76 seconds
Started Aug 08 07:47:53 PM PDT 24
Finished Aug 08 07:47:54 PM PDT 24
Peak memory 206300 kb
Host smart-93e1ca98-04e9-48aa-a728-741de87723e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439364033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.439364033
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4196082466
Short name T970
Test name
Test status
Simulation time 2074960616 ps
CPU time 13.97 seconds
Started Aug 08 07:47:54 PM PDT 24
Finished Aug 08 07:48:08 PM PDT 24
Peak memory 233172 kb
Host smart-bebbda96-71d2-48aa-bef3-ac0b96176408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196082466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4196082466
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2541945384
Short name T723
Test name
Test status
Simulation time 40618140 ps
CPU time 0.7 seconds
Started Aug 08 07:48:01 PM PDT 24
Finished Aug 08 07:48:02 PM PDT 24
Peak memory 205280 kb
Host smart-82a1afda-69cf-4d04-b3d1-f40f234e737d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541945384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2541945384
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1157818874
Short name T869
Test name
Test status
Simulation time 1226533617 ps
CPU time 9.99 seconds
Started Aug 08 07:48:01 PM PDT 24
Finished Aug 08 07:48:11 PM PDT 24
Peak memory 224984 kb
Host smart-dd99dbd8-d4b2-4d03-bea9-419bec2aaddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157818874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1157818874
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2297956555
Short name T986
Test name
Test status
Simulation time 46948511 ps
CPU time 0.74 seconds
Started Aug 08 07:47:55 PM PDT 24
Finished Aug 08 07:47:56 PM PDT 24
Peak memory 206296 kb
Host smart-7c9a5f6b-ffc9-4695-8006-cbf162952daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297956555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2297956555
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.456443423
Short name T262
Test name
Test status
Simulation time 9516023699 ps
CPU time 68.34 seconds
Started Aug 08 07:48:02 PM PDT 24
Finished Aug 08 07:49:11 PM PDT 24
Peak memory 249584 kb
Host smart-b8c79ab9-b590-4d9c-bae6-77f680f62e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456443423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.456443423
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.503994293
Short name T961
Test name
Test status
Simulation time 21044986067 ps
CPU time 185.32 seconds
Started Aug 08 07:48:00 PM PDT 24
Finished Aug 08 07:51:05 PM PDT 24
Peak memory 256896 kb
Host smart-f50468b8-29c9-40c9-86d6-3aa2c0ee91bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503994293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.503994293
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3534752926
Short name T492
Test name
Test status
Simulation time 11411629767 ps
CPU time 78.24 seconds
Started Aug 08 07:48:00 PM PDT 24
Finished Aug 08 07:49:18 PM PDT 24
Peak memory 261148 kb
Host smart-6661d38c-ca37-4a2e-a083-221aae3cdd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534752926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3534752926
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1160401201
Short name T293
Test name
Test status
Simulation time 2921832202 ps
CPU time 39.64 seconds
Started Aug 08 07:48:03 PM PDT 24
Finished Aug 08 07:48:43 PM PDT 24
Peak memory 233528 kb
Host smart-8c19e45a-77bf-4762-a318-9189713ab586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160401201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1160401201
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.810420626
Short name T444
Test name
Test status
Simulation time 17519986968 ps
CPU time 128.28 seconds
Started Aug 08 07:48:00 PM PDT 24
Finished Aug 08 07:50:08 PM PDT 24
Peak memory 267032 kb
Host smart-c4ed8ee1-02c0-4fb2-8fe9-f0ac1b812d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810420626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.810420626
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1106250784
Short name T272
Test name
Test status
Simulation time 416084660 ps
CPU time 3.59 seconds
Started Aug 08 07:48:01 PM PDT 24
Finished Aug 08 07:48:04 PM PDT 24
Peak memory 228924 kb
Host smart-57ae1aee-1f1f-4a25-a122-14a1e9e0bf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106250784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1106250784
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4267544391
Short name T751
Test name
Test status
Simulation time 58953791092 ps
CPU time 81.23 seconds
Started Aug 08 07:48:01 PM PDT 24
Finished Aug 08 07:49:23 PM PDT 24
Peak memory 250032 kb
Host smart-5e39c8a2-a01d-49b2-8a8a-c6df592fd66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267544391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4267544391
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3687652762
Short name T691
Test name
Test status
Simulation time 1092571656 ps
CPU time 2.62 seconds
Started Aug 08 07:48:03 PM PDT 24
Finished Aug 08 07:48:06 PM PDT 24
Peak memory 224872 kb
Host smart-02ba3194-a38d-4fd4-bc15-5fdcb6167f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687652762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3687652762
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1625970552
Short name T565
Test name
Test status
Simulation time 8766257863 ps
CPU time 23.18 seconds
Started Aug 08 07:48:02 PM PDT 24
Finished Aug 08 07:48:25 PM PDT 24
Peak memory 233188 kb
Host smart-70e67435-f6e9-4400-b9c2-33e8b1b17c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625970552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1625970552
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3902505370
Short name T941
Test name
Test status
Simulation time 3595191000 ps
CPU time 9.61 seconds
Started Aug 08 07:48:01 PM PDT 24
Finished Aug 08 07:48:11 PM PDT 24
Peak memory 223676 kb
Host smart-0a6c0463-6587-49c7-8b9f-659aa50c4c12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3902505370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3902505370
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4151464420
Short name T545
Test name
Test status
Simulation time 200279828 ps
CPU time 2.97 seconds
Started Aug 08 07:47:51 PM PDT 24
Finished Aug 08 07:47:54 PM PDT 24
Peak memory 216628 kb
Host smart-48863cce-f02a-4abe-ae06-df84d6d5c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151464420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4151464420
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.131783352
Short name T801
Test name
Test status
Simulation time 4816522313 ps
CPU time 14.43 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:48:06 PM PDT 24
Peak memory 216648 kb
Host smart-1dded772-6d91-46f5-acad-2db9bf970f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131783352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.131783352
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2170362682
Short name T347
Test name
Test status
Simulation time 336351326 ps
CPU time 4.01 seconds
Started Aug 08 07:48:01 PM PDT 24
Finished Aug 08 07:48:05 PM PDT 24
Peak memory 216688 kb
Host smart-2317bb9b-79df-453b-8ac4-db60626b13ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170362682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2170362682
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4150871147
Short name T490
Test name
Test status
Simulation time 132924294 ps
CPU time 0.81 seconds
Started Aug 08 07:47:52 PM PDT 24
Finished Aug 08 07:47:53 PM PDT 24
Peak memory 206588 kb
Host smart-4175710d-be77-43ab-8e11-feb3e79bcd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150871147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4150871147
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.773629284
Short name T764
Test name
Test status
Simulation time 16961058375 ps
CPU time 56.24 seconds
Started Aug 08 07:48:11 PM PDT 24
Finished Aug 08 07:49:08 PM PDT 24
Peak memory 237676 kb
Host smart-f38dd27c-9c3e-4faa-8fc6-6e4c9bcc9242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773629284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.773629284
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3185817500
Short name T41
Test name
Test status
Simulation time 13411938 ps
CPU time 0.76 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:48:10 PM PDT 24
Peak memory 205908 kb
Host smart-c0d90e88-a9f0-45aa-ad37-fb8112a0380f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185817500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3185817500
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.683375442
Short name T731
Test name
Test status
Simulation time 295026540 ps
CPU time 3.74 seconds
Started Aug 08 07:48:00 PM PDT 24
Finished Aug 08 07:48:04 PM PDT 24
Peak memory 224876 kb
Host smart-4009a815-e6b1-4d88-9e07-c72c45cdc9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683375442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.683375442
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3256735419
Short name T942
Test name
Test status
Simulation time 40858272 ps
CPU time 0.73 seconds
Started Aug 08 07:48:03 PM PDT 24
Finished Aug 08 07:48:03 PM PDT 24
Peak memory 206296 kb
Host smart-8e3a0bf1-7d53-433e-9818-6fbae26b5d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256735419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3256735419
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1377571619
Short name T906
Test name
Test status
Simulation time 5840549348 ps
CPU time 30.22 seconds
Started Aug 08 07:48:12 PM PDT 24
Finished Aug 08 07:48:42 PM PDT 24
Peak memory 249740 kb
Host smart-18757e80-126e-4098-9c33-3126feb7ded0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377571619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1377571619
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2720540541
Short name T726
Test name
Test status
Simulation time 6498228183 ps
CPU time 98.16 seconds
Started Aug 08 07:48:01 PM PDT 24
Finished Aug 08 07:49:39 PM PDT 24
Peak memory 249620 kb
Host smart-bcedc976-1b78-43ea-a69f-950555c29054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720540541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2720540541
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1614059841
Short name T909
Test name
Test status
Simulation time 95576550323 ps
CPU time 123.7 seconds
Started Aug 08 07:48:07 PM PDT 24
Finished Aug 08 07:50:11 PM PDT 24
Peak memory 249556 kb
Host smart-829e061c-c0be-4d6a-b472-350e8993a295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614059841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1614059841
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2440699438
Short name T295
Test name
Test status
Simulation time 8035220924 ps
CPU time 34.07 seconds
Started Aug 08 07:48:03 PM PDT 24
Finished Aug 08 07:48:38 PM PDT 24
Peak memory 234228 kb
Host smart-2edb4602-654b-4958-b1ca-94868fdfd8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440699438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2440699438
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.391967543
Short name T227
Test name
Test status
Simulation time 124127042710 ps
CPU time 139.45 seconds
Started Aug 08 07:48:02 PM PDT 24
Finished Aug 08 07:50:22 PM PDT 24
Peak memory 249628 kb
Host smart-c15daa9e-fade-426e-9114-e45b7db549b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391967543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.391967543
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3812764062
Short name T633
Test name
Test status
Simulation time 900769627 ps
CPU time 3.84 seconds
Started Aug 08 07:48:03 PM PDT 24
Finished Aug 08 07:48:07 PM PDT 24
Peak memory 224816 kb
Host smart-0722a1dc-7dfd-4176-887c-a31c8492e636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812764062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3812764062
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1277736793
Short name T443
Test name
Test status
Simulation time 970960098 ps
CPU time 20.85 seconds
Started Aug 08 07:48:11 PM PDT 24
Finished Aug 08 07:48:32 PM PDT 24
Peak memory 240204 kb
Host smart-c58d1946-f2c7-41cd-bb2b-20f2985d2d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277736793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1277736793
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1316544521
Short name T532
Test name
Test status
Simulation time 25101731029 ps
CPU time 17.09 seconds
Started Aug 08 07:48:03 PM PDT 24
Finished Aug 08 07:48:20 PM PDT 24
Peak memory 224952 kb
Host smart-020c8608-8e57-4ff8-a7cf-50c3aba773a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316544521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1316544521
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2473806585
Short name T761
Test name
Test status
Simulation time 121691899 ps
CPU time 2.7 seconds
Started Aug 08 07:48:11 PM PDT 24
Finished Aug 08 07:48:14 PM PDT 24
Peak memory 233148 kb
Host smart-2fb3eaa0-6db8-4e55-a177-cced2bfd2d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473806585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2473806585
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.355519944
Short name T508
Test name
Test status
Simulation time 3458366895 ps
CPU time 10.4 seconds
Started Aug 08 07:48:03 PM PDT 24
Finished Aug 08 07:48:13 PM PDT 24
Peak memory 219360 kb
Host smart-39678070-5cf9-4ea2-8491-38d3162ed1ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355519944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.355519944
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1999982927
Short name T342
Test name
Test status
Simulation time 8701598786 ps
CPU time 15.75 seconds
Started Aug 08 07:48:00 PM PDT 24
Finished Aug 08 07:48:16 PM PDT 24
Peak memory 216912 kb
Host smart-95a3b8fe-c382-4bdf-b7ee-a036d74e254f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999982927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1999982927
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3071949156
Short name T352
Test name
Test status
Simulation time 6994955885 ps
CPU time 21.07 seconds
Started Aug 08 07:48:00 PM PDT 24
Finished Aug 08 07:48:21 PM PDT 24
Peak memory 216656 kb
Host smart-128df5b3-e7bf-4d34-95a0-8235be1a26f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071949156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3071949156
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2558699417
Short name T621
Test name
Test status
Simulation time 165535657 ps
CPU time 2.49 seconds
Started Aug 08 07:48:03 PM PDT 24
Finished Aug 08 07:48:05 PM PDT 24
Peak memory 216660 kb
Host smart-355822e2-1bcf-4778-93e3-8f1cbbf164cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558699417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2558699417
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1433126470
Short name T449
Test name
Test status
Simulation time 33667985 ps
CPU time 0.67 seconds
Started Aug 08 07:48:00 PM PDT 24
Finished Aug 08 07:48:01 PM PDT 24
Peak memory 206024 kb
Host smart-28a4afd0-8e8a-4034-bcea-52f711940c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433126470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1433126470
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.312196598
Short name T766
Test name
Test status
Simulation time 556131019 ps
CPU time 3.65 seconds
Started Aug 08 07:48:02 PM PDT 24
Finished Aug 08 07:48:06 PM PDT 24
Peak memory 233056 kb
Host smart-0a793796-474d-421d-a6c4-24eed9da196a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312196598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.312196598
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.879372289
Short name T346
Test name
Test status
Simulation time 18412048 ps
CPU time 0.7 seconds
Started Aug 08 07:48:13 PM PDT 24
Finished Aug 08 07:48:13 PM PDT 24
Peak memory 205896 kb
Host smart-7dacdf25-17f7-4fd1-9e6b-0a45bf1d1584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879372289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.879372289
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3474585249
Short name T648
Test name
Test status
Simulation time 432442407 ps
CPU time 2.45 seconds
Started Aug 08 07:48:13 PM PDT 24
Finished Aug 08 07:48:16 PM PDT 24
Peak memory 224892 kb
Host smart-ef59ac39-213a-44d5-babf-d4c66f7180a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474585249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3474585249
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.570507089
Short name T112
Test name
Test status
Simulation time 24385949 ps
CPU time 0.8 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:48:10 PM PDT 24
Peak memory 207024 kb
Host smart-fa73d5ae-ab85-4c62-b729-4bf7694cfab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570507089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.570507089
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2950857812
Short name T749
Test name
Test status
Simulation time 4697442906 ps
CPU time 48.05 seconds
Started Aug 08 07:48:11 PM PDT 24
Finished Aug 08 07:48:59 PM PDT 24
Peak memory 251660 kb
Host smart-195740d9-8fd9-4714-a3c7-8fe700c9961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950857812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2950857812
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4051441750
Short name T939
Test name
Test status
Simulation time 25757622526 ps
CPU time 153.44 seconds
Started Aug 08 07:48:10 PM PDT 24
Finished Aug 08 07:50:44 PM PDT 24
Peak memory 249596 kb
Host smart-4776db60-41ec-419c-8211-49bf2b2e1efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051441750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4051441750
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3952078658
Short name T859
Test name
Test status
Simulation time 9066121107 ps
CPU time 77.77 seconds
Started Aug 08 07:48:13 PM PDT 24
Finished Aug 08 07:49:31 PM PDT 24
Peak memory 254784 kb
Host smart-f315e38b-159c-47da-85cb-933da40904b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952078658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3952078658
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1452917540
Short name T566
Test name
Test status
Simulation time 17888504684 ps
CPU time 15.27 seconds
Started Aug 08 07:48:10 PM PDT 24
Finished Aug 08 07:48:25 PM PDT 24
Peak memory 233240 kb
Host smart-4a0fa016-d2f3-4350-a4e5-cd2fc85ee872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452917540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1452917540
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.988857441
Short name T730
Test name
Test status
Simulation time 192879734 ps
CPU time 0.97 seconds
Started Aug 08 07:48:14 PM PDT 24
Finished Aug 08 07:48:15 PM PDT 24
Peak memory 216436 kb
Host smart-bd1915c8-d9d5-43e0-a776-4b9e924f4663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988857441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.988857441
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3749748238
Short name T645
Test name
Test status
Simulation time 390762483 ps
CPU time 2.28 seconds
Started Aug 08 07:48:08 PM PDT 24
Finished Aug 08 07:48:10 PM PDT 24
Peak memory 232740 kb
Host smart-5d36afd6-0d2f-433b-bfe1-2b15770ce6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749748238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3749748238
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1215457346
Short name T810
Test name
Test status
Simulation time 18066529484 ps
CPU time 58.53 seconds
Started Aug 08 07:48:10 PM PDT 24
Finished Aug 08 07:49:08 PM PDT 24
Peak memory 253084 kb
Host smart-2b9c7228-db4f-4429-be5c-607e6376563e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215457346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1215457346
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3769323540
Short name T577
Test name
Test status
Simulation time 107027656 ps
CPU time 2.15 seconds
Started Aug 08 07:48:13 PM PDT 24
Finished Aug 08 07:48:15 PM PDT 24
Peak memory 224868 kb
Host smart-ff0c38fd-e18d-45a4-abab-984c526681f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769323540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3769323540
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1153142923
Short name T922
Test name
Test status
Simulation time 2146236482 ps
CPU time 9.97 seconds
Started Aug 08 07:48:14 PM PDT 24
Finished Aug 08 07:48:24 PM PDT 24
Peak memory 233196 kb
Host smart-247d6b7e-4f0f-4b20-a1e8-67ddb853e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153142923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1153142923
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1666041134
Short name T349
Test name
Test status
Simulation time 4478823142 ps
CPU time 6.02 seconds
Started Aug 08 07:48:10 PM PDT 24
Finished Aug 08 07:48:16 PM PDT 24
Peak memory 220880 kb
Host smart-323ca2b5-6724-4bf1-a740-eb2bea11473c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1666041134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1666041134
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2193235277
Short name T873
Test name
Test status
Simulation time 225683943 ps
CPU time 1.1 seconds
Started Aug 08 07:48:10 PM PDT 24
Finished Aug 08 07:48:11 PM PDT 24
Peak memory 207584 kb
Host smart-37779fd1-38e0-4983-8f3c-7f2f51adb6e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193235277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2193235277
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1044283091
Short name T960
Test name
Test status
Simulation time 355335285 ps
CPU time 5.87 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:48:15 PM PDT 24
Peak memory 216616 kb
Host smart-efaad746-3891-4eda-ae17-8a839d9020ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044283091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1044283091
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2465018994
Short name T817
Test name
Test status
Simulation time 8169052680 ps
CPU time 11.14 seconds
Started Aug 08 07:48:10 PM PDT 24
Finished Aug 08 07:48:21 PM PDT 24
Peak memory 216664 kb
Host smart-d30e20e8-4ca4-470c-8d97-07385c7a26ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465018994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2465018994
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2581990028
Short name T843
Test name
Test status
Simulation time 84745392 ps
CPU time 3.74 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:48:13 PM PDT 24
Peak memory 216740 kb
Host smart-71b5c2ac-9643-4df7-a7e0-be234f5e2a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581990028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2581990028
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2487671967
Short name T43
Test name
Test status
Simulation time 10750022 ps
CPU time 0.71 seconds
Started Aug 08 07:48:10 PM PDT 24
Finished Aug 08 07:48:11 PM PDT 24
Peak memory 206008 kb
Host smart-675f8b0c-614b-470e-bd00-802070e8e408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487671967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2487671967
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.53222423
Short name T977
Test name
Test status
Simulation time 4207114917 ps
CPU time 15.36 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:48:25 PM PDT 24
Peak memory 233216 kb
Host smart-993c0f8e-cf19-4840-9672-1901e6b5cfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53222423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.53222423
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1325927462
Short name T712
Test name
Test status
Simulation time 21518941 ps
CPU time 0.72 seconds
Started Aug 08 07:48:21 PM PDT 24
Finished Aug 08 07:48:22 PM PDT 24
Peak memory 205492 kb
Host smart-6e416d3b-f9e4-4412-b909-9cb0e06da8ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325927462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1325927462
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1202124821
Short name T76
Test name
Test status
Simulation time 61293386 ps
CPU time 2.66 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:48:12 PM PDT 24
Peak memory 233200 kb
Host smart-0e5f2efc-7221-4b65-9ef7-7fee213bb30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202124821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1202124821
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1885620232
Short name T454
Test name
Test status
Simulation time 18279300 ps
CPU time 0.78 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:48:10 PM PDT 24
Peak memory 207024 kb
Host smart-a0ca32f6-0269-455b-8017-450392a8ce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885620232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1885620232
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.111118617
Short name T649
Test name
Test status
Simulation time 3020385041 ps
CPU time 53.54 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:49:03 PM PDT 24
Peak memory 249944 kb
Host smart-c6af65d3-c46f-412d-8422-5a21cb1a960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111118617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.111118617
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3810823045
Short name T309
Test name
Test status
Simulation time 4358989645 ps
CPU time 109.32 seconds
Started Aug 08 07:48:12 PM PDT 24
Finished Aug 08 07:50:01 PM PDT 24
Peak memory 251096 kb
Host smart-dcc20ab0-37b9-4543-9985-60b3f83e5bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810823045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3810823045
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4011133858
Short name T150
Test name
Test status
Simulation time 32945855889 ps
CPU time 110.84 seconds
Started Aug 08 07:48:20 PM PDT 24
Finished Aug 08 07:50:11 PM PDT 24
Peak memory 254224 kb
Host smart-6eb384d9-8225-4118-8491-2f8d96907195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011133858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4011133858
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1723278960
Short name T612
Test name
Test status
Simulation time 241565674 ps
CPU time 3.42 seconds
Started Aug 08 07:48:12 PM PDT 24
Finished Aug 08 07:48:16 PM PDT 24
Peak memory 224988 kb
Host smart-2fe6d6b5-cc70-4c26-b6ab-7905546467e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723278960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1723278960
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1051802973
Short name T919
Test name
Test status
Simulation time 7651873262 ps
CPU time 28.43 seconds
Started Aug 08 07:48:12 PM PDT 24
Finished Aug 08 07:48:41 PM PDT 24
Peak memory 241396 kb
Host smart-597e8eac-7c7b-4dcc-b865-0274fc4ba37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051802973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1051802973
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.401516178
Short name T964
Test name
Test status
Simulation time 109575041 ps
CPU time 3.13 seconds
Started Aug 08 07:48:14 PM PDT 24
Finished Aug 08 07:48:17 PM PDT 24
Peak memory 220284 kb
Host smart-5c589b0c-35db-41af-aacc-0a73b93c8653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401516178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.401516178
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.169435535
Short name T11
Test name
Test status
Simulation time 4406099047 ps
CPU time 36.24 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:48:45 PM PDT 24
Peak memory 233160 kb
Host smart-8a36db2d-dfad-4ec0-b55b-0e4202153ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169435535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.169435535
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.893308422
Short name T458
Test name
Test status
Simulation time 133684409 ps
CPU time 2.22 seconds
Started Aug 08 07:48:09 PM PDT 24
Finished Aug 08 07:48:12 PM PDT 24
Peak memory 224792 kb
Host smart-72778c77-f8f4-4d80-aa3e-862cf43bc262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893308422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.893308422
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3475168838
Short name T997
Test name
Test status
Simulation time 98739432 ps
CPU time 2.61 seconds
Started Aug 08 07:48:12 PM PDT 24
Finished Aug 08 07:48:14 PM PDT 24
Peak memory 233168 kb
Host smart-a5099b53-1485-48e4-a945-2f45b15adec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475168838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3475168838
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4219248301
Short name T127
Test name
Test status
Simulation time 6413352931 ps
CPU time 14.81 seconds
Started Aug 08 07:48:07 PM PDT 24
Finished Aug 08 07:48:22 PM PDT 24
Peak memory 220636 kb
Host smart-0dbcfdde-f095-418b-bf86-6c7f553cabac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4219248301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4219248301
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2527290963
Short name T204
Test name
Test status
Simulation time 164643575342 ps
CPU time 732.88 seconds
Started Aug 08 07:48:21 PM PDT 24
Finished Aug 08 08:00:34 PM PDT 24
Peak memory 273032 kb
Host smart-9dad8d90-6e8e-428f-bf63-5a6963af25d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527290963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2527290963
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1176199028
Short name T382
Test name
Test status
Simulation time 777458221 ps
CPU time 5.24 seconds
Started Aug 08 07:48:08 PM PDT 24
Finished Aug 08 07:48:14 PM PDT 24
Peak memory 216604 kb
Host smart-875488b3-9e63-491f-9a7e-b0d27857423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176199028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1176199028
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.353582401
Short name T428
Test name
Test status
Simulation time 2020143470 ps
CPU time 6.31 seconds
Started Aug 08 07:48:11 PM PDT 24
Finished Aug 08 07:48:18 PM PDT 24
Peak memory 216688 kb
Host smart-6c2b5b50-6896-49a5-9fc3-1d57ec626aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353582401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.353582401
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1027588966
Short name T321
Test name
Test status
Simulation time 98155601 ps
CPU time 1.2 seconds
Started Aug 08 07:48:13 PM PDT 24
Finished Aug 08 07:48:14 PM PDT 24
Peak memory 216692 kb
Host smart-197d74d1-a5f5-46ab-aedf-847969183a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027588966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1027588966
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2686300778
Short name T773
Test name
Test status
Simulation time 86252591 ps
CPU time 0.76 seconds
Started Aug 08 07:48:08 PM PDT 24
Finished Aug 08 07:48:09 PM PDT 24
Peak memory 206316 kb
Host smart-6bf466b5-9f86-49b5-85ea-868b610437c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686300778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2686300778
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2176113025
Short name T664
Test name
Test status
Simulation time 24685787382 ps
CPU time 20.99 seconds
Started Aug 08 07:48:08 PM PDT 24
Finished Aug 08 07:48:29 PM PDT 24
Peak memory 225016 kb
Host smart-3a7afcfc-4072-4afe-bcd4-41bd05d191eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176113025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2176113025
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3827890621
Short name T484
Test name
Test status
Simulation time 57139774 ps
CPU time 0.69 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:20 PM PDT 24
Peak memory 205836 kb
Host smart-59534be5-9dc8-4880-a515-3d43a72e57a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827890621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3827890621
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1510487973
Short name T549
Test name
Test status
Simulation time 877719856 ps
CPU time 10.8 seconds
Started Aug 08 07:48:18 PM PDT 24
Finished Aug 08 07:48:29 PM PDT 24
Peak memory 224884 kb
Host smart-077887f6-62d7-46e2-b990-3f82c1801116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510487973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1510487973
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2201713466
Short name T838
Test name
Test status
Simulation time 18736916 ps
CPU time 0.79 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:20 PM PDT 24
Peak memory 207048 kb
Host smart-cb76a225-6505-4150-a2a0-8bbc5df55c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201713466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2201713466
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2453481137
Short name T711
Test name
Test status
Simulation time 12368371618 ps
CPU time 94.4 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:49:53 PM PDT 24
Peak memory 254872 kb
Host smart-58013939-65b2-4f64-907c-2c8552fe2735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453481137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2453481137
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3600616932
Short name T72
Test name
Test status
Simulation time 66980245032 ps
CPU time 54.17 seconds
Started Aug 08 07:48:20 PM PDT 24
Finished Aug 08 07:49:14 PM PDT 24
Peak memory 225052 kb
Host smart-c9064e6b-8303-4ebf-a2a9-f1151e4aa197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600616932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3600616932
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3770421580
Short name T210
Test name
Test status
Simulation time 3289884756 ps
CPU time 62.61 seconds
Started Aug 08 07:48:20 PM PDT 24
Finished Aug 08 07:49:22 PM PDT 24
Peak memory 252720 kb
Host smart-c290903a-608d-46ba-88f1-0c8d0225ab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770421580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3770421580
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2435831084
Short name T938
Test name
Test status
Simulation time 1799890543 ps
CPU time 10.17 seconds
Started Aug 08 07:48:22 PM PDT 24
Finished Aug 08 07:48:32 PM PDT 24
Peak memory 240284 kb
Host smart-180ec461-7373-4dfa-b73b-a9e04852e20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435831084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2435831084
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4192913774
Short name T354
Test name
Test status
Simulation time 1929492554 ps
CPU time 15.35 seconds
Started Aug 08 07:48:25 PM PDT 24
Finished Aug 08 07:48:41 PM PDT 24
Peak memory 224976 kb
Host smart-d7b067b7-0072-4ea0-9982-9ea8a65d85e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192913774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4192913774
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3466564395
Short name T831
Test name
Test status
Simulation time 1755960605 ps
CPU time 7.49 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:27 PM PDT 24
Peak memory 219276 kb
Host smart-93f96473-6e23-4940-b4ef-a6875744e10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466564395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3466564395
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2830891954
Short name T282
Test name
Test status
Simulation time 3806113945 ps
CPU time 36.55 seconds
Started Aug 08 07:48:20 PM PDT 24
Finished Aug 08 07:48:57 PM PDT 24
Peak memory 236292 kb
Host smart-63de0b7e-83ab-440a-96d5-8e4c2d3d4f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830891954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2830891954
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.915948392
Short name T286
Test name
Test status
Simulation time 7386553970 ps
CPU time 22.03 seconds
Started Aug 08 07:48:21 PM PDT 24
Finished Aug 08 07:48:43 PM PDT 24
Peak memory 233136 kb
Host smart-d28b1a11-e845-4718-ad03-05eed50c4449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915948392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.915948392
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1801021939
Short name T905
Test name
Test status
Simulation time 10073370177 ps
CPU time 18.41 seconds
Started Aug 08 07:48:20 PM PDT 24
Finished Aug 08 07:48:39 PM PDT 24
Peak memory 224908 kb
Host smart-ad101ee5-5775-4c03-82d0-f9ef3eccf056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801021939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1801021939
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3712470727
Short name T779
Test name
Test status
Simulation time 969557634 ps
CPU time 4.84 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:24 PM PDT 24
Peak memory 223528 kb
Host smart-72e10e4a-2275-4899-96b0-e7904d3cc81f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3712470727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3712470727
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3042479090
Short name T822
Test name
Test status
Simulation time 54750677851 ps
CPU time 137.5 seconds
Started Aug 08 07:48:20 PM PDT 24
Finished Aug 08 07:50:38 PM PDT 24
Peak memory 253708 kb
Host smart-bdbc6270-51b2-48ac-9cce-cd4079134ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042479090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3042479090
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3885874271
Short name T888
Test name
Test status
Simulation time 2292378100 ps
CPU time 11.68 seconds
Started Aug 08 07:48:20 PM PDT 24
Finished Aug 08 07:48:32 PM PDT 24
Peak memory 216764 kb
Host smart-bc8e45d9-409a-4f2c-8d21-01d9feeb4656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885874271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3885874271
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1515876381
Short name T355
Test name
Test status
Simulation time 936283129 ps
CPU time 1.81 seconds
Started Aug 08 07:48:21 PM PDT 24
Finished Aug 08 07:48:23 PM PDT 24
Peak memory 208296 kb
Host smart-cb208ea0-3843-4f3a-aab6-295be5c81953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515876381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1515876381
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2351275789
Short name T524
Test name
Test status
Simulation time 14829519 ps
CPU time 0.75 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:19 PM PDT 24
Peak memory 206392 kb
Host smart-cf7ac348-0ff0-4883-9834-2c22aaf4c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351275789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2351275789
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4198833456
Short name T898
Test name
Test status
Simulation time 48097991 ps
CPU time 0.81 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:20 PM PDT 24
Peak memory 206424 kb
Host smart-5781c7d7-79a9-4047-86f7-0e66b2359cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198833456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4198833456
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1451671828
Short name T557
Test name
Test status
Simulation time 127279545 ps
CPU time 2.56 seconds
Started Aug 08 07:48:20 PM PDT 24
Finished Aug 08 07:48:23 PM PDT 24
Peak memory 232896 kb
Host smart-735d93a2-10ff-4b5b-b113-25ea9c6ea5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451671828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1451671828
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1291070112
Short name T411
Test name
Test status
Simulation time 13747051 ps
CPU time 0.78 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:29 PM PDT 24
Peak memory 205280 kb
Host smart-de7f7fba-d516-4334-8c13-9edf7a3956bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291070112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1291070112
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2894385356
Short name T879
Test name
Test status
Simulation time 2693205869 ps
CPU time 8.88 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:28 PM PDT 24
Peak memory 224980 kb
Host smart-de17cc70-7062-4111-8984-07167a5b743e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894385356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2894385356
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3044200039
Short name T578
Test name
Test status
Simulation time 15892183 ps
CPU time 0.77 seconds
Started Aug 08 07:48:21 PM PDT 24
Finished Aug 08 07:48:22 PM PDT 24
Peak memory 207088 kb
Host smart-91586f46-6898-48c7-b3a9-d50319b2a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044200039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3044200039
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3737133112
Short name T114
Test name
Test status
Simulation time 10847871499 ps
CPU time 62.02 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:49:31 PM PDT 24
Peak memory 256036 kb
Host smart-90b3852c-40dc-451f-8f14-48121fdca988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737133112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3737133112
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1408388810
Short name T486
Test name
Test status
Simulation time 8758853173 ps
CPU time 69.51 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:49:38 PM PDT 24
Peak memory 237772 kb
Host smart-0dc76bf5-43f4-4517-9fe5-a589a7a620f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408388810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1408388810
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.918623907
Short name T743
Test name
Test status
Simulation time 20767783686 ps
CPU time 136.49 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:50:45 PM PDT 24
Peak memory 270272 kb
Host smart-ea1f0ec6-8f69-4f44-a788-7c6801370771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918623907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.918623907
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2830642861
Short name T130
Test name
Test status
Simulation time 9203842364 ps
CPU time 37.33 seconds
Started Aug 08 07:48:18 PM PDT 24
Finished Aug 08 07:48:56 PM PDT 24
Peak memory 236360 kb
Host smart-48bb9347-ebb4-42f3-8cd0-fe39981e8a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830642861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2830642861
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.359687536
Short name T245
Test name
Test status
Simulation time 5724712120 ps
CPU time 63.81 seconds
Started Aug 08 07:48:25 PM PDT 24
Finished Aug 08 07:49:29 PM PDT 24
Peak memory 256964 kb
Host smart-016d6527-2c70-482c-8ffa-ae850aa215c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359687536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.359687536
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2799910197
Short name T327
Test name
Test status
Simulation time 568644187 ps
CPU time 6.3 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:25 PM PDT 24
Peak memory 229952 kb
Host smart-0073823d-8233-4ee7-8168-214ae0f0d0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799910197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2799910197
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1078114733
Short name T527
Test name
Test status
Simulation time 945117021 ps
CPU time 9.69 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:29 PM PDT 24
Peak memory 236792 kb
Host smart-0a2fe238-0a4a-4fca-9a2c-1c08702439de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078114733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1078114733
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1747914873
Short name T943
Test name
Test status
Simulation time 433754892 ps
CPU time 6.73 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:26 PM PDT 24
Peak memory 233136 kb
Host smart-1a1e71c6-6db6-41cf-a5a3-ac7c7ac09a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747914873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1747914873
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1494485354
Short name T673
Test name
Test status
Simulation time 5466893193 ps
CPU time 11.83 seconds
Started Aug 08 07:48:20 PM PDT 24
Finished Aug 08 07:48:32 PM PDT 24
Peak memory 224960 kb
Host smart-4f34cef8-4abc-47f4-8c10-facf624c0187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494485354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1494485354
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1533641778
Short name T129
Test name
Test status
Simulation time 2287266469 ps
CPU time 9.67 seconds
Started Aug 08 07:48:32 PM PDT 24
Finished Aug 08 07:48:42 PM PDT 24
Peak memory 221168 kb
Host smart-220a8279-1b79-42e0-bf85-f65fd6a4efa0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1533641778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1533641778
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.69263357
Short name T144
Test name
Test status
Simulation time 140805810774 ps
CPU time 249.35 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:52:39 PM PDT 24
Peak memory 261644 kb
Host smart-d3289e9f-9694-40c3-b1f8-ee681f6559b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69263357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress
_all.69263357
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2612865263
Short name T547
Test name
Test status
Simulation time 14282905 ps
CPU time 0.77 seconds
Started Aug 08 07:48:21 PM PDT 24
Finished Aug 08 07:48:22 PM PDT 24
Peak memory 206428 kb
Host smart-de6ae1d7-68e6-4ae9-a8c5-8c1897118104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612865263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2612865263
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1444488424
Short name T376
Test name
Test status
Simulation time 5708231573 ps
CPU time 19.05 seconds
Started Aug 08 07:48:18 PM PDT 24
Finished Aug 08 07:48:37 PM PDT 24
Peak memory 216716 kb
Host smart-01a88dd4-2715-4fc5-b89e-40692acc37a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444488424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1444488424
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3114627376
Short name T373
Test name
Test status
Simulation time 29345993 ps
CPU time 0.99 seconds
Started Aug 08 07:48:19 PM PDT 24
Finished Aug 08 07:48:20 PM PDT 24
Peak memory 207736 kb
Host smart-f297efa0-a1f0-444c-89c5-34c154ef5e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114627376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3114627376
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3623905470
Short name T758
Test name
Test status
Simulation time 76988819 ps
CPU time 0.96 seconds
Started Aug 08 07:48:21 PM PDT 24
Finished Aug 08 07:48:22 PM PDT 24
Peak memory 206416 kb
Host smart-6a3df55e-d82c-4528-882c-7c0a003ce770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623905470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3623905470
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2429108430
Short name T666
Test name
Test status
Simulation time 879017667 ps
CPU time 4.07 seconds
Started Aug 08 07:48:25 PM PDT 24
Finished Aug 08 07:48:30 PM PDT 24
Peak memory 233136 kb
Host smart-7ea81f28-c499-4f7a-b31c-52ede3ce3ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429108430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2429108430
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2421003480
Short name T356
Test name
Test status
Simulation time 16131987 ps
CPU time 0.74 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:48:30 PM PDT 24
Peak memory 205828 kb
Host smart-5e46f54c-7336-4132-8651-c778ee509103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421003480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2421003480
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3867735603
Short name T975
Test name
Test status
Simulation time 1449188047 ps
CPU time 5.92 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:48:35 PM PDT 24
Peak memory 224956 kb
Host smart-8fff5c0a-6fb9-40fa-9519-e9a3d91927f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867735603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3867735603
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1394808837
Short name T745
Test name
Test status
Simulation time 50526040 ps
CPU time 0.78 seconds
Started Aug 08 07:48:27 PM PDT 24
Finished Aug 08 07:48:28 PM PDT 24
Peak memory 207004 kb
Host smart-2590179d-9e03-4dd9-b1e9-9ed9a5085c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394808837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1394808837
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.840586446
Short name T317
Test name
Test status
Simulation time 336504666 ps
CPU time 5.82 seconds
Started Aug 08 07:48:27 PM PDT 24
Finished Aug 08 07:48:32 PM PDT 24
Peak memory 224956 kb
Host smart-71a9a2aa-e286-4e8b-89cf-19adcbe7bbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840586446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.840586446
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.688018453
Short name T230
Test name
Test status
Simulation time 20812229223 ps
CPU time 279.59 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:53:09 PM PDT 24
Peak memory 265968 kb
Host smart-dd7b1583-1549-4a25-8845-cee6c5da596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688018453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.688018453
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.149282158
Short name T8
Test name
Test status
Simulation time 3815287519 ps
CPU time 20.74 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:48:49 PM PDT 24
Peak memory 224860 kb
Host smart-3a7fefdc-49c5-4e5e-be90-e963732ab2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149282158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.149282158
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.929881597
Short name T370
Test name
Test status
Simulation time 1514819694 ps
CPU time 11.74 seconds
Started Aug 08 07:48:27 PM PDT 24
Finished Aug 08 07:48:39 PM PDT 24
Peak memory 233124 kb
Host smart-f1a253c3-bce3-4f2c-9feb-0567def8c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929881597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.929881597
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3215048055
Short name T544
Test name
Test status
Simulation time 111594981578 ps
CPU time 206.38 seconds
Started Aug 08 07:48:30 PM PDT 24
Finished Aug 08 07:51:57 PM PDT 24
Peak memory 256616 kb
Host smart-f43ba068-6fc9-4268-9427-88f33ba24580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215048055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3215048055
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2752963795
Short name T180
Test name
Test status
Simulation time 1294403681 ps
CPU time 12.77 seconds
Started Aug 08 07:48:30 PM PDT 24
Finished Aug 08 07:48:43 PM PDT 24
Peak memory 233148 kb
Host smart-d6c119cf-4e26-4e6a-8c5e-da1bbd985e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752963795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2752963795
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3369352896
Short name T289
Test name
Test status
Simulation time 1411558908 ps
CPU time 13.96 seconds
Started Aug 08 07:48:32 PM PDT 24
Finished Aug 08 07:48:46 PM PDT 24
Peak memory 235380 kb
Host smart-c3a342f9-d3ef-4f42-8fbb-3d823c2a1e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369352896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3369352896
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.824444649
Short name T5
Test name
Test status
Simulation time 122872837 ps
CPU time 2.54 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:31 PM PDT 24
Peak memory 232860 kb
Host smart-cc976e4f-656e-428a-ba45-22e2e3545ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824444649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.824444649
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.685919187
Short name T832
Test name
Test status
Simulation time 1845597658 ps
CPU time 2.68 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:31 PM PDT 24
Peak memory 224892 kb
Host smart-a45ad957-ebf5-40dc-b83d-c83b0ed99234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685919187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.685919187
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.892488283
Short name T12
Test name
Test status
Simulation time 571766398 ps
CPU time 7.86 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:36 PM PDT 24
Peak memory 224192 kb
Host smart-96b79f25-cbfa-4c73-98ca-4ebe3360f1f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=892488283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.892488283
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.712316263
Short name T767
Test name
Test status
Simulation time 154752767 ps
CPU time 0.98 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:48:30 PM PDT 24
Peak memory 207928 kb
Host smart-e2b39772-5ecf-4957-938b-e28015da8188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712316263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.712316263
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2086575115
Short name T375
Test name
Test status
Simulation time 4569049645 ps
CPU time 18.63 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:47 PM PDT 24
Peak memory 217092 kb
Host smart-dac9aaf7-8978-46c5-bd2e-ded5ae97509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086575115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2086575115
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3090827879
Short name T775
Test name
Test status
Simulation time 39920392 ps
CPU time 0.75 seconds
Started Aug 08 07:48:31 PM PDT 24
Finished Aug 08 07:48:32 PM PDT 24
Peak memory 206136 kb
Host smart-539c9211-439c-4b6e-8006-62611a59b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090827879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3090827879
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.4137726719
Short name T618
Test name
Test status
Simulation time 610551926 ps
CPU time 5.51 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:34 PM PDT 24
Peak memory 216768 kb
Host smart-21776a67-9cf7-4f80-9444-02472cc9853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137726719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4137726719
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2469009732
Short name T46
Test name
Test status
Simulation time 53592625 ps
CPU time 0.7 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:28 PM PDT 24
Peak memory 206328 kb
Host smart-a64fd501-148b-4760-a997-f60bd03f0a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469009732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2469009732
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.649300328
Short name T67
Test name
Test status
Simulation time 4570730090 ps
CPU time 15.02 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:43 PM PDT 24
Peak memory 224932 kb
Host smart-19d2b02d-36b9-4be7-a75f-40856fbb3cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649300328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.649300328
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3598112911
Short name T322
Test name
Test status
Simulation time 85321669 ps
CPU time 0.72 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:48:38 PM PDT 24
Peak memory 205840 kb
Host smart-163a6f16-806e-40b3-9993-90e57d3bebcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598112911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3598112911
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3970449231
Short name T74
Test name
Test status
Simulation time 481536339 ps
CPU time 7.26 seconds
Started Aug 08 07:48:35 PM PDT 24
Finished Aug 08 07:48:42 PM PDT 24
Peak memory 233164 kb
Host smart-669f1dc3-de94-4e53-8c51-9a8bb35d6f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970449231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3970449231
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2241651475
Short name T377
Test name
Test status
Simulation time 20457122 ps
CPU time 0.76 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:29 PM PDT 24
Peak memory 207356 kb
Host smart-2b973805-b54e-4ca4-898c-d77915e5fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241651475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2241651475
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1606096362
Short name T207
Test name
Test status
Simulation time 1997990082 ps
CPU time 23.14 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:49:02 PM PDT 24
Peak memory 223888 kb
Host smart-0fbfd7f3-7d52-41fb-969d-b66ed5fef9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606096362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1606096362
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.987441022
Short name T889
Test name
Test status
Simulation time 196427858440 ps
CPU time 149.81 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:51:07 PM PDT 24
Peak memory 251664 kb
Host smart-9a2966d7-b2c9-49ff-8a06-91a0ceeb47eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987441022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.987441022
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3522162133
Short name T374
Test name
Test status
Simulation time 645336307 ps
CPU time 9.74 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:48:47 PM PDT 24
Peak memory 225012 kb
Host smart-345f5296-7a49-48eb-8ab7-37d726254bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522162133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3522162133
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1359758792
Short name T28
Test name
Test status
Simulation time 9828737275 ps
CPU time 43.14 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:49:19 PM PDT 24
Peak memory 250524 kb
Host smart-0c777b49-85f8-4b77-876a-986fa0f1779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359758792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1359758792
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2715727117
Short name T397
Test name
Test status
Simulation time 33243527 ps
CPU time 2.28 seconds
Started Aug 08 07:48:30 PM PDT 24
Finished Aug 08 07:48:32 PM PDT 24
Peak memory 232828 kb
Host smart-cf08a423-ba30-4a57-92df-d509d0bc4856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715727117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2715727117
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1624827222
Short name T405
Test name
Test status
Simulation time 8821952894 ps
CPU time 93.53 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:50:03 PM PDT 24
Peak memory 250272 kb
Host smart-9a76a7d8-3140-4217-84e5-59a1f7171b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624827222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1624827222
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.665664496
Short name T875
Test name
Test status
Simulation time 219592980 ps
CPU time 3.51 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:48:32 PM PDT 24
Peak memory 233164 kb
Host smart-c0d2a6fa-36e0-4738-bb93-4666653006e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665664496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.665664496
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1746669810
Short name T410
Test name
Test status
Simulation time 6081638873 ps
CPU time 20.54 seconds
Started Aug 08 07:48:31 PM PDT 24
Finished Aug 08 07:48:52 PM PDT 24
Peak memory 241236 kb
Host smart-256fce34-480f-4e0e-848a-28963c4abd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746669810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1746669810
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.424508587
Short name T926
Test name
Test status
Simulation time 98275963 ps
CPU time 4.5 seconds
Started Aug 08 07:48:40 PM PDT 24
Finished Aug 08 07:48:45 PM PDT 24
Peak memory 223552 kb
Host smart-974b6680-9224-48c9-a797-e1ea39b46c3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=424508587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.424508587
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2566763090
Short name T22
Test name
Test status
Simulation time 8617970447 ps
CPU time 158.21 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:51:14 PM PDT 24
Peak memory 273200 kb
Host smart-877ba089-9592-4ab6-ba81-0c3605066aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566763090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2566763090
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1055949496
Short name T302
Test name
Test status
Simulation time 9666323778 ps
CPU time 51.43 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:49:20 PM PDT 24
Peak memory 216764 kb
Host smart-bce4240d-1789-40c1-8b71-305c202d6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055949496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1055949496
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3601011292
Short name T796
Test name
Test status
Simulation time 9033502244 ps
CPU time 11.19 seconds
Started Aug 08 07:48:28 PM PDT 24
Finished Aug 08 07:48:40 PM PDT 24
Peak memory 216716 kb
Host smart-93bddc0f-80ac-48cc-b072-c8cf53468759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601011292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3601011292
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3630760558
Short name T828
Test name
Test status
Simulation time 178010141 ps
CPU time 1.75 seconds
Started Aug 08 07:48:30 PM PDT 24
Finished Aug 08 07:48:31 PM PDT 24
Peak memory 216752 kb
Host smart-bf08468d-cd61-47d1-8bf2-24fd5e4b113e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630760558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3630760558
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3283535827
Short name T368
Test name
Test status
Simulation time 102516079 ps
CPU time 0.89 seconds
Started Aug 08 07:48:29 PM PDT 24
Finished Aug 08 07:48:30 PM PDT 24
Peak memory 207396 kb
Host smart-d63fd035-1888-4e89-a581-933a5a2d1840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283535827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3283535827
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.809215521
Short name T463
Test name
Test status
Simulation time 597488023 ps
CPU time 2.44 seconds
Started Aug 08 07:48:39 PM PDT 24
Finished Aug 08 07:48:42 PM PDT 24
Peak memory 224144 kb
Host smart-c8901d8e-38c2-4eef-827b-16341949ac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809215521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.809215521
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2833265797
Short name T769
Test name
Test status
Simulation time 14322478 ps
CPU time 0.74 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:48:37 PM PDT 24
Peak memory 206288 kb
Host smart-bd2ae079-c97c-4dce-a4b3-96154fe272c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833265797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2833265797
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3017110247
Short name T13
Test name
Test status
Simulation time 742548797 ps
CPU time 6.49 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:48:43 PM PDT 24
Peak memory 224860 kb
Host smart-19e47746-5aa8-4788-844e-20b7fb205d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017110247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3017110247
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3667209690
Short name T441
Test name
Test status
Simulation time 17395356 ps
CPU time 0.76 seconds
Started Aug 08 07:48:39 PM PDT 24
Finished Aug 08 07:48:40 PM PDT 24
Peak memory 206364 kb
Host smart-a3885ea8-bb76-4b31-aff9-ae132aec5917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667209690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3667209690
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.321082334
Short name T456
Test name
Test status
Simulation time 146065233907 ps
CPU time 59.41 seconds
Started Aug 08 07:48:43 PM PDT 24
Finished Aug 08 07:49:43 PM PDT 24
Peak memory 249592 kb
Host smart-829f79c2-7917-4b1c-a414-cb94e619f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321082334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.321082334
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3358241634
Short name T172
Test name
Test status
Simulation time 39562788928 ps
CPU time 314.35 seconds
Started Aug 08 07:48:41 PM PDT 24
Finished Aug 08 07:53:56 PM PDT 24
Peak memory 266092 kb
Host smart-ba676310-d4f6-416f-968c-c58db9b7e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358241634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3358241634
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2640033003
Short name T506
Test name
Test status
Simulation time 6200484897 ps
CPU time 84.95 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:50:02 PM PDT 24
Peak memory 252076 kb
Host smart-9d650311-aa31-458d-beb0-4a66fe56aed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640033003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2640033003
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3633764080
Short name T445
Test name
Test status
Simulation time 4097632265 ps
CPU time 41.44 seconds
Started Aug 08 07:48:43 PM PDT 24
Finished Aug 08 07:49:25 PM PDT 24
Peak memory 249588 kb
Host smart-d95803ac-536d-4f5a-b775-50065b3057e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633764080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3633764080
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2528167823
Short name T588
Test name
Test status
Simulation time 34506148303 ps
CPU time 77.36 seconds
Started Aug 08 07:48:39 PM PDT 24
Finished Aug 08 07:49:56 PM PDT 24
Peak memory 249788 kb
Host smart-19408fd2-0117-483a-8719-a31d59ae1871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528167823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2528167823
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2713729734
Short name T408
Test name
Test status
Simulation time 261770788 ps
CPU time 3.87 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:48:41 PM PDT 24
Peak memory 224932 kb
Host smart-8c701da4-5fa9-4622-ad25-6f45c0ba78ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713729734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2713729734
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3825267104
Short name T119
Test name
Test status
Simulation time 3196477340 ps
CPU time 11.25 seconds
Started Aug 08 07:48:41 PM PDT 24
Finished Aug 08 07:48:52 PM PDT 24
Peak memory 241040 kb
Host smart-cf410f69-9bd2-4c67-960f-9e3260ba843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825267104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3825267104
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3145130363
Short name T191
Test name
Test status
Simulation time 10375127672 ps
CPU time 19.85 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:48:56 PM PDT 24
Peak memory 233092 kb
Host smart-3ef53e15-7b39-4306-939d-fda93e6c263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145130363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3145130363
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2585192185
Short name T531
Test name
Test status
Simulation time 24048190181 ps
CPU time 14.7 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:48:51 PM PDT 24
Peak memory 257092 kb
Host smart-4e9f17da-06c5-4d7b-bbbc-89805ed66135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585192185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2585192185
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3343886559
Short name T778
Test name
Test status
Simulation time 2457025625 ps
CPU time 11.59 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:48:49 PM PDT 24
Peak memory 219556 kb
Host smart-31bf2957-10de-46fc-8046-8ec0cc32e557
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3343886559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3343886559
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3473675689
Short name T303
Test name
Test status
Simulation time 16516010377 ps
CPU time 34.31 seconds
Started Aug 08 07:48:35 PM PDT 24
Finished Aug 08 07:49:10 PM PDT 24
Peak memory 216664 kb
Host smart-e895fd9c-c3bd-4ab1-9b13-d25535b453c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473675689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3473675689
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2708863478
Short name T556
Test name
Test status
Simulation time 351409972 ps
CPU time 1.46 seconds
Started Aug 08 07:48:39 PM PDT 24
Finished Aug 08 07:48:40 PM PDT 24
Peak memory 208212 kb
Host smart-6d87e98d-eb42-4e16-b8ce-19c30c581d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708863478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2708863478
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.79936004
Short name T416
Test name
Test status
Simulation time 26699166 ps
CPU time 0.87 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:48:39 PM PDT 24
Peak memory 206424 kb
Host smart-c9ed17cc-8b50-422a-a65b-b100a58ad2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79936004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.79936004
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1516864284
Short name T516
Test name
Test status
Simulation time 344921417 ps
CPU time 0.96 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:48:37 PM PDT 24
Peak memory 207364 kb
Host smart-4078a6c3-9513-466a-80f8-64074ed152da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516864284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1516864284
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3008198885
Short name T279
Test name
Test status
Simulation time 3446768317 ps
CPU time 6.9 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:48:44 PM PDT 24
Peak memory 224976 kb
Host smart-d6d65c6c-09fd-48eb-a22a-a801105ed269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008198885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3008198885
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1648584826
Short name T984
Test name
Test status
Simulation time 34896531 ps
CPU time 0.71 seconds
Started Aug 08 07:46:19 PM PDT 24
Finished Aug 08 07:46:20 PM PDT 24
Peak memory 206216 kb
Host smart-93c0b773-41f9-4a43-b022-49fb60942b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648584826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
648584826
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.918706604
Short name T667
Test name
Test status
Simulation time 431238728 ps
CPU time 2.84 seconds
Started Aug 08 07:46:17 PM PDT 24
Finished Aug 08 07:46:20 PM PDT 24
Peak memory 233204 kb
Host smart-16240e29-ff57-4ec5-9322-17798204c879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918706604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.918706604
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3592723076
Short name T403
Test name
Test status
Simulation time 50529032 ps
CPU time 0.74 seconds
Started Aug 08 07:46:19 PM PDT 24
Finished Aug 08 07:46:20 PM PDT 24
Peak memory 207032 kb
Host smart-98ac38c5-94bb-47f3-9ff7-d212bd0b1d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592723076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3592723076
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.885196527
Short name T413
Test name
Test status
Simulation time 1922071465 ps
CPU time 9.83 seconds
Started Aug 08 07:46:13 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 237804 kb
Host smart-c0be6f53-4686-4b31-ad57-5331fa9c480a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885196527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.885196527
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3592920416
Short name T685
Test name
Test status
Simulation time 11926338573 ps
CPU time 101.24 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:48:01 PM PDT 24
Peak memory 240404 kb
Host smart-ba5d867f-3a89-4508-ab33-e32810f37576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592920416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3592920416
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2656402387
Short name T236
Test name
Test status
Simulation time 20395139282 ps
CPU time 125.91 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:48:26 PM PDT 24
Peak memory 271384 kb
Host smart-260b9739-0f3a-429c-91e4-0bc58d86cb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656402387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2656402387
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4007001701
Short name T6
Test name
Test status
Simulation time 1922351646 ps
CPU time 29.9 seconds
Started Aug 08 07:46:15 PM PDT 24
Finished Aug 08 07:46:45 PM PDT 24
Peak memory 233104 kb
Host smart-8998eddc-35ea-4c6b-b57b-8ec3dd4dd514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007001701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4007001701
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3557753342
Short name T734
Test name
Test status
Simulation time 5112634305 ps
CPU time 38.07 seconds
Started Aug 08 07:46:14 PM PDT 24
Finished Aug 08 07:46:52 PM PDT 24
Peak memory 250624 kb
Host smart-e9d5d337-c33a-475b-be0d-66c4dc4c5a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557753342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3557753342
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1180771787
Short name T835
Test name
Test status
Simulation time 210426245 ps
CPU time 5.88 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:26 PM PDT 24
Peak memory 233104 kb
Host smart-bed16358-4850-4554-8a3b-3953e10a3ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180771787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1180771787
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2670851100
Short name T162
Test name
Test status
Simulation time 6628339712 ps
CPU time 45.09 seconds
Started Aug 08 07:46:11 PM PDT 24
Finished Aug 08 07:46:56 PM PDT 24
Peak memory 233208 kb
Host smart-fc7f5741-a48c-48c1-82b8-503ec5e375ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670851100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2670851100
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3088156117
Short name T824
Test name
Test status
Simulation time 10447393342 ps
CPU time 17.09 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:37 PM PDT 24
Peak memory 240060 kb
Host smart-81b87e13-6110-4595-bc74-880eddbb8697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088156117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3088156117
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3142568741
Short name T551
Test name
Test status
Simulation time 1426197710 ps
CPU time 3.54 seconds
Started Aug 08 07:46:15 PM PDT 24
Finished Aug 08 07:46:19 PM PDT 24
Peak memory 233076 kb
Host smart-86ab001f-7cee-4fcc-a524-a050c54a6284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142568741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3142568741
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.258545021
Short name T983
Test name
Test status
Simulation time 1147546083 ps
CPU time 11.09 seconds
Started Aug 08 07:46:18 PM PDT 24
Finished Aug 08 07:46:29 PM PDT 24
Peak memory 220500 kb
Host smart-4bbafa2e-fd50-439b-baab-f5b10fa9c459
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=258545021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.258545021
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2787589169
Short name T58
Test name
Test status
Simulation time 115316149 ps
CPU time 1 seconds
Started Aug 08 07:46:16 PM PDT 24
Finished Aug 08 07:46:17 PM PDT 24
Peak memory 236920 kb
Host smart-8d0a877e-b63f-4cbf-a1ae-7518eb8d0b1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787589169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2787589169
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.235944419
Short name T694
Test name
Test status
Simulation time 1492798158 ps
CPU time 22.69 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:43 PM PDT 24
Peak memory 220056 kb
Host smart-b901e2f0-6aff-4c0b-9ffa-be8e957a58c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235944419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.235944419
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2961588346
Short name T626
Test name
Test status
Simulation time 15844413458 ps
CPU time 21.47 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:42 PM PDT 24
Peak memory 216700 kb
Host smart-c4c70db7-d908-4620-a38a-a7e33a4d2f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961588346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2961588346
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4099251207
Short name T344
Test name
Test status
Simulation time 124430177 ps
CPU time 1.32 seconds
Started Aug 08 07:46:19 PM PDT 24
Finished Aug 08 07:46:21 PM PDT 24
Peak memory 216708 kb
Host smart-3295063b-089c-4948-8ace-57c02fc33313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099251207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4099251207
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3451437459
Short name T741
Test name
Test status
Simulation time 22241697 ps
CPU time 0.73 seconds
Started Aug 08 07:46:12 PM PDT 24
Finished Aug 08 07:46:13 PM PDT 24
Peak memory 206320 kb
Host smart-bfda1bf8-d014-4af1-9a6d-16ae5b516269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451437459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3451437459
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1898486295
Short name T663
Test name
Test status
Simulation time 690990406 ps
CPU time 4.43 seconds
Started Aug 08 07:46:18 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 225024 kb
Host smart-32cea067-f18d-4c05-9653-9b8559ad1888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898486295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1898486295
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1875261513
Short name T48
Test name
Test status
Simulation time 16361666 ps
CPU time 0.69 seconds
Started Aug 08 07:48:39 PM PDT 24
Finished Aug 08 07:48:39 PM PDT 24
Peak memory 205284 kb
Host smart-aedc53c2-6bf8-4b01-b4a0-b3e2fce208df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875261513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1875261513
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1938470304
Short name T629
Test name
Test status
Simulation time 1629263194 ps
CPU time 17.65 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:48:55 PM PDT 24
Peak memory 233148 kb
Host smart-63ccb0cc-bc90-404a-9bd7-7359cb7de494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938470304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1938470304
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1829802288
Short name T313
Test name
Test status
Simulation time 40737032 ps
CPU time 0.78 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:48:39 PM PDT 24
Peak memory 206292 kb
Host smart-84583535-135b-456a-9a8d-f7df6f85a758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829802288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1829802288
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1281787921
Short name T117
Test name
Test status
Simulation time 42520284382 ps
CPU time 56.38 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:49:33 PM PDT 24
Peak memory 251204 kb
Host smart-970cb82d-389b-41d8-b9db-425982727b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281787921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1281787921
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3018480375
Short name T304
Test name
Test status
Simulation time 5334214160 ps
CPU time 110.27 seconds
Started Aug 08 07:48:41 PM PDT 24
Finished Aug 08 07:50:31 PM PDT 24
Peak memory 250740 kb
Host smart-e8cc3c73-ffc0-4f3d-9fb6-647e7b90f836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018480375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3018480375
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4090245097
Short name T198
Test name
Test status
Simulation time 34960261184 ps
CPU time 206.48 seconds
Started Aug 08 07:48:41 PM PDT 24
Finished Aug 08 07:52:08 PM PDT 24
Peak memory 265308 kb
Host smart-af4e0d24-2a55-41c3-995c-660059ee873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090245097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4090245097
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2679576875
Short name T292
Test name
Test status
Simulation time 760485488 ps
CPU time 6.45 seconds
Started Aug 08 07:48:39 PM PDT 24
Finished Aug 08 07:48:45 PM PDT 24
Peak memory 241400 kb
Host smart-8892d6e4-4ba8-4c5f-9bb2-db7b75aba446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679576875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2679576875
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1917138312
Short name T951
Test name
Test status
Simulation time 13514490612 ps
CPU time 101.44 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:50:17 PM PDT 24
Peak memory 241424 kb
Host smart-487dcdba-e385-4f23-957a-9891e78bff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917138312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1917138312
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4005521310
Short name T277
Test name
Test status
Simulation time 203210696 ps
CPU time 3.22 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:48:39 PM PDT 24
Peak memory 233080 kb
Host smart-0a13c98a-1c4a-4369-bcf9-c3527cf60c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005521310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4005521310
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1114183014
Short name T864
Test name
Test status
Simulation time 1018771089 ps
CPU time 5.68 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:48:44 PM PDT 24
Peak memory 224860 kb
Host smart-4ae3649a-c3e5-4132-8fc1-59c0be076a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114183014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1114183014
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1303542484
Short name T695
Test name
Test status
Simulation time 1472129789 ps
CPU time 4.18 seconds
Started Aug 08 07:48:43 PM PDT 24
Finished Aug 08 07:48:47 PM PDT 24
Peak memory 233128 kb
Host smart-56af322f-977a-40b4-84ad-58218b26031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303542484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1303542484
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3420238112
Short name T183
Test name
Test status
Simulation time 14533500072 ps
CPU time 12.64 seconds
Started Aug 08 07:48:39 PM PDT 24
Finished Aug 08 07:48:51 PM PDT 24
Peak memory 233204 kb
Host smart-33e02606-b86e-4601-a8a4-a4a73ee1b386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420238112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3420238112
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.98601795
Short name T498
Test name
Test status
Simulation time 653807165 ps
CPU time 4.03 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:48:41 PM PDT 24
Peak memory 220884 kb
Host smart-159ee34c-d022-42ba-933a-1f24bbaeafe1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=98601795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direc
t.98601795
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2859920932
Short name T40
Test name
Test status
Simulation time 426060440761 ps
CPU time 580.88 seconds
Started Aug 08 07:48:41 PM PDT 24
Finished Aug 08 07:58:22 PM PDT 24
Peak memory 271848 kb
Host smart-ee7ef941-51cc-4318-822f-89f2d0320bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859920932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2859920932
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.711883417
Short name T904
Test name
Test status
Simulation time 2379943321 ps
CPU time 13 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:48:51 PM PDT 24
Peak memory 216672 kb
Host smart-4652e0db-3069-45f0-8c9e-38a8fe17cf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711883417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.711883417
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.361663216
Short name T950
Test name
Test status
Simulation time 39970470 ps
CPU time 0.72 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:48:37 PM PDT 24
Peak memory 206144 kb
Host smart-42078e41-ccb6-43f2-8abf-0b5efe511394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361663216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.361663216
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2341899589
Short name T525
Test name
Test status
Simulation time 14772033 ps
CPU time 0.81 seconds
Started Aug 08 07:48:36 PM PDT 24
Finished Aug 08 07:48:37 PM PDT 24
Peak memory 207132 kb
Host smart-cde66317-2188-4983-9370-7e87f3af5589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341899589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2341899589
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1805914835
Short name T613
Test name
Test status
Simulation time 534878741 ps
CPU time 1.03 seconds
Started Aug 08 07:48:39 PM PDT 24
Finished Aug 08 07:48:40 PM PDT 24
Peak memory 206912 kb
Host smart-83b56dd2-1159-4d40-847f-d49186ed802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805914835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1805914835
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2233289766
Short name T116
Test name
Test status
Simulation time 8142070986 ps
CPU time 9.96 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:48:48 PM PDT 24
Peak memory 225004 kb
Host smart-2fb4723b-8a21-43c7-9fa9-1a1418a0a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233289766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2233289766
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1269495684
Short name T450
Test name
Test status
Simulation time 20456291 ps
CPU time 0.77 seconds
Started Aug 08 07:48:49 PM PDT 24
Finished Aug 08 07:48:50 PM PDT 24
Peak memory 205780 kb
Host smart-1ed7af97-4f90-4b39-8bfd-8df964222007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269495684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1269495684
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3184435444
Short name T476
Test name
Test status
Simulation time 353640097 ps
CPU time 4.84 seconds
Started Aug 08 07:48:46 PM PDT 24
Finished Aug 08 07:48:51 PM PDT 24
Peak memory 233088 kb
Host smart-946aebf4-b9c7-4dfa-8684-6b40b7d03aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184435444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3184435444
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2637579820
Short name T702
Test name
Test status
Simulation time 42797915 ps
CPU time 0.8 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:48:39 PM PDT 24
Peak memory 207348 kb
Host smart-9d1f0e06-5dd7-48de-a8af-af3d8fc37a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637579820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2637579820
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1328384874
Short name T156
Test name
Test status
Simulation time 19624754300 ps
CPU time 134.01 seconds
Started Aug 08 07:48:44 PM PDT 24
Finished Aug 08 07:50:58 PM PDT 24
Peak memory 268800 kb
Host smart-557a6716-afb5-420a-bebf-0b02f8dd9fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328384874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1328384874
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3335311847
Short name T122
Test name
Test status
Simulation time 145757681281 ps
CPU time 343.46 seconds
Started Aug 08 07:48:49 PM PDT 24
Finished Aug 08 07:54:33 PM PDT 24
Peak memory 263908 kb
Host smart-1d2b28a2-d5fd-48d0-abec-b0d90201aaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335311847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3335311847
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2236625563
Short name T29
Test name
Test status
Simulation time 3051655577 ps
CPU time 63.14 seconds
Started Aug 08 07:48:46 PM PDT 24
Finished Aug 08 07:49:49 PM PDT 24
Peak memory 250896 kb
Host smart-23b07630-3a1a-482f-af1b-e357b154fc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236625563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2236625563
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3899383332
Short name T291
Test name
Test status
Simulation time 2755436735 ps
CPU time 45.69 seconds
Started Aug 08 07:48:44 PM PDT 24
Finished Aug 08 07:49:30 PM PDT 24
Peak memory 243376 kb
Host smart-ca5b52bf-711d-4d5b-9fd3-103158a1913a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899383332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3899383332
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3184808899
Short name T471
Test name
Test status
Simulation time 18189562078 ps
CPU time 144.83 seconds
Started Aug 08 07:48:45 PM PDT 24
Finished Aug 08 07:51:10 PM PDT 24
Peak memory 257784 kb
Host smart-d5e596bb-f177-4cae-b914-4dad1192b47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184808899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3184808899
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.47272588
Short name T987
Test name
Test status
Simulation time 527307776 ps
CPU time 6.54 seconds
Started Aug 08 07:48:45 PM PDT 24
Finished Aug 08 07:48:52 PM PDT 24
Peak memory 224908 kb
Host smart-a0e0dfcc-0827-4204-a0b1-588bdde34dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47272588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.47272588
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3120007335
Short name T501
Test name
Test status
Simulation time 19936549717 ps
CPU time 90.94 seconds
Started Aug 08 07:48:49 PM PDT 24
Finished Aug 08 07:50:20 PM PDT 24
Peak memory 241332 kb
Host smart-3b273d59-a42d-4384-920a-35595831faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120007335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3120007335
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2218941775
Short name T857
Test name
Test status
Simulation time 7319104320 ps
CPU time 21.16 seconds
Started Aug 08 07:48:44 PM PDT 24
Finished Aug 08 07:49:05 PM PDT 24
Peak memory 241132 kb
Host smart-8ad9cd04-84cd-4e88-b15e-eb95266dddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218941775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2218941775
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1036697622
Short name T412
Test name
Test status
Simulation time 39968401 ps
CPU time 2.05 seconds
Started Aug 08 07:48:46 PM PDT 24
Finished Aug 08 07:48:48 PM PDT 24
Peak memory 224892 kb
Host smart-06c196cc-dafe-4695-9991-9d72feccd3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036697622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1036697622
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3195284661
Short name T609
Test name
Test status
Simulation time 2711057716 ps
CPU time 11.54 seconds
Started Aug 08 07:48:49 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 221272 kb
Host smart-a63a4b2b-606a-4759-ac04-24a39fe65c1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3195284661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3195284661
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4187756692
Short name T681
Test name
Test status
Simulation time 15597010320 ps
CPU time 141.13 seconds
Started Aug 08 07:48:43 PM PDT 24
Finished Aug 08 07:51:04 PM PDT 24
Peak memory 251704 kb
Host smart-971da709-28f8-4ae8-9b66-00475a92a487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187756692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4187756692
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.209861927
Short name T855
Test name
Test status
Simulation time 8642781432 ps
CPU time 17.35 seconds
Started Aug 08 07:48:38 PM PDT 24
Finished Aug 08 07:48:55 PM PDT 24
Peak memory 216764 kb
Host smart-52a9d65d-7200-4b32-b349-726c7556f108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209861927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.209861927
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2622308790
Short name T765
Test name
Test status
Simulation time 854833291 ps
CPU time 3.99 seconds
Started Aug 08 07:48:37 PM PDT 24
Finished Aug 08 07:48:41 PM PDT 24
Peak memory 216640 kb
Host smart-346acee0-e1ad-4a55-9f8f-c7999c8be54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622308790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2622308790
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.187540558
Short name T530
Test name
Test status
Simulation time 80560034 ps
CPU time 1.27 seconds
Started Aug 08 07:48:45 PM PDT 24
Finished Aug 08 07:48:46 PM PDT 24
Peak memory 216708 kb
Host smart-f5807808-ebf6-4abb-9864-10b47fe48da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187540558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.187540558
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1562112734
Short name T73
Test name
Test status
Simulation time 504491385 ps
CPU time 0.85 seconds
Started Aug 08 07:48:44 PM PDT 24
Finished Aug 08 07:48:45 PM PDT 24
Peak memory 206444 kb
Host smart-4fa5618c-dc42-4450-abe8-8e6474502231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562112734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1562112734
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3141500084
Short name T785
Test name
Test status
Simulation time 1797652929 ps
CPU time 8.53 seconds
Started Aug 08 07:48:46 PM PDT 24
Finished Aug 08 07:48:54 PM PDT 24
Peak memory 233124 kb
Host smart-6739c5bc-68c3-4224-9c54-f7a6a22e5ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141500084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3141500084
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3532430291
Short name T420
Test name
Test status
Simulation time 13462510 ps
CPU time 0.75 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:48:54 PM PDT 24
Peak memory 205256 kb
Host smart-53e6b070-464d-47d1-93da-5d69874ed789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532430291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3532430291
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.774210430
Short name T199
Test name
Test status
Simulation time 78164308 ps
CPU time 2.5 seconds
Started Aug 08 07:48:48 PM PDT 24
Finished Aug 08 07:48:50 PM PDT 24
Peak memory 224952 kb
Host smart-a58e8822-dddd-44b1-ac93-c450afda9594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774210430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.774210430
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1099127970
Short name T876
Test name
Test status
Simulation time 92185966 ps
CPU time 0.77 seconds
Started Aug 08 07:48:45 PM PDT 24
Finished Aug 08 07:48:46 PM PDT 24
Peak memory 207300 kb
Host smart-3f44c47f-0483-41c2-9337-f87e864a1be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099127970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1099127970
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2833618180
Short name T465
Test name
Test status
Simulation time 33218577582 ps
CPU time 295.63 seconds
Started Aug 08 07:48:51 PM PDT 24
Finished Aug 08 07:53:47 PM PDT 24
Peak memory 250156 kb
Host smart-a98f4291-3f17-4fdd-9703-fed82c7add14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833618180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2833618180
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.672999196
Short name T261
Test name
Test status
Simulation time 15503956230 ps
CPU time 139.03 seconds
Started Aug 08 07:48:50 PM PDT 24
Finished Aug 08 07:51:09 PM PDT 24
Peak memory 257852 kb
Host smart-a5acc7c5-45e0-4fa4-a9c2-9ec24b38e44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672999196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.672999196
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2154879035
Short name T299
Test name
Test status
Simulation time 204877860 ps
CPU time 6.98 seconds
Started Aug 08 07:48:45 PM PDT 24
Finished Aug 08 07:48:53 PM PDT 24
Peak memory 233148 kb
Host smart-1cb5b4fb-1aad-4dc2-889a-1c3cf6cbd772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154879035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2154879035
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2992376402
Short name T985
Test name
Test status
Simulation time 80230861655 ps
CPU time 279.25 seconds
Started Aug 08 07:48:43 PM PDT 24
Finished Aug 08 07:53:23 PM PDT 24
Peak memory 266464 kb
Host smart-28d1887c-37be-4081-b820-c40e33fdbfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992376402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2992376402
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3050823204
Short name T915
Test name
Test status
Simulation time 258079628 ps
CPU time 4.66 seconds
Started Aug 08 07:48:45 PM PDT 24
Finished Aug 08 07:48:50 PM PDT 24
Peak memory 233168 kb
Host smart-22e9b040-b202-4863-b038-8aa19f92084e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050823204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3050823204
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1638398460
Short name T258
Test name
Test status
Simulation time 10482871300 ps
CPU time 51.62 seconds
Started Aug 08 07:48:45 PM PDT 24
Finished Aug 08 07:49:37 PM PDT 24
Peak memory 233200 kb
Host smart-d0d24e73-a254-4991-8c86-355a2e73ba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638398460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1638398460
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1206222904
Short name T996
Test name
Test status
Simulation time 122981334 ps
CPU time 2.47 seconds
Started Aug 08 07:48:49 PM PDT 24
Finished Aug 08 07:48:52 PM PDT 24
Peak memory 232760 kb
Host smart-09aa859b-92af-43cb-acff-04c2849df277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206222904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1206222904
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.595399128
Short name T816
Test name
Test status
Simulation time 2016335375 ps
CPU time 3.44 seconds
Started Aug 08 07:48:45 PM PDT 24
Finished Aug 08 07:48:49 PM PDT 24
Peak memory 224932 kb
Host smart-6a1f4758-345d-42ca-8e43-345189d67d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595399128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.595399128
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3051667255
Short name T33
Test name
Test status
Simulation time 3440995740 ps
CPU time 8.22 seconds
Started Aug 08 07:48:50 PM PDT 24
Finished Aug 08 07:48:58 PM PDT 24
Peak memory 220836 kb
Host smart-002c43df-db89-4f06-9360-d0e5571f614f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3051667255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3051667255
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.830675849
Short name T464
Test name
Test status
Simulation time 23126567219 ps
CPU time 103.73 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:50:37 PM PDT 24
Peak memory 249728 kb
Host smart-20ed1cd8-aec5-4c1a-871a-9b709bb6ea0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830675849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.830675849
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3123466732
Short name T529
Test name
Test status
Simulation time 44002997931 ps
CPU time 23.12 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:49:16 PM PDT 24
Peak memory 217696 kb
Host smart-0c0cd065-10ef-4808-8bf0-e17de6ee2485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123466732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3123466732
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3232520956
Short name T427
Test name
Test status
Simulation time 1128284659 ps
CPU time 4.61 seconds
Started Aug 08 07:48:45 PM PDT 24
Finished Aug 08 07:48:49 PM PDT 24
Peak memory 216668 kb
Host smart-a4ecb684-e723-40e0-9c21-a038118adf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232520956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3232520956
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4223537551
Short name T684
Test name
Test status
Simulation time 20895663 ps
CPU time 1.24 seconds
Started Aug 08 07:48:43 PM PDT 24
Finished Aug 08 07:48:45 PM PDT 24
Peak memory 216612 kb
Host smart-5f7bcb8f-531e-40d2-b1f2-f55c6f650fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223537551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4223537551
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.489764529
Short name T628
Test name
Test status
Simulation time 168925164 ps
CPU time 0.94 seconds
Started Aug 08 07:48:46 PM PDT 24
Finished Aug 08 07:48:47 PM PDT 24
Peak memory 206332 kb
Host smart-8c6b2736-6e06-45aa-a012-559dab145e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489764529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.489764529
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3176246193
Short name T742
Test name
Test status
Simulation time 4472557919 ps
CPU time 7.96 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 224888 kb
Host smart-b9e122a7-eb97-473e-a58f-9b87cac843a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176246193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3176246193
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2817132805
Short name T686
Test name
Test status
Simulation time 60336541 ps
CPU time 0.71 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:48:53 PM PDT 24
Peak memory 205848 kb
Host smart-1dd7727d-93da-433c-afd1-f25df5d0f8f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817132805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2817132805
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3467489318
Short name T493
Test name
Test status
Simulation time 165155847 ps
CPU time 4.53 seconds
Started Aug 08 07:48:52 PM PDT 24
Finished Aug 08 07:48:56 PM PDT 24
Peak memory 224864 kb
Host smart-4fa82dc4-3477-4e76-80d9-55b77e989d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467489318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3467489318
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.845230692
Short name T871
Test name
Test status
Simulation time 29478552 ps
CPU time 0.79 seconds
Started Aug 08 07:48:51 PM PDT 24
Finished Aug 08 07:48:52 PM PDT 24
Peak memory 207028 kb
Host smart-0523f42e-37ae-446c-8c73-5842dddfd702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845230692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.845230692
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3297669876
Short name T170
Test name
Test status
Simulation time 67549180319 ps
CPU time 172.38 seconds
Started Aug 08 07:48:52 PM PDT 24
Finished Aug 08 07:51:44 PM PDT 24
Peak memory 249588 kb
Host smart-30632f6e-505a-442c-99e5-b1c947858161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297669876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3297669876
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3348054718
Short name T267
Test name
Test status
Simulation time 3429874927 ps
CPU time 16.7 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:49:10 PM PDT 24
Peak memory 249664 kb
Host smart-2af0e936-c6a0-4691-88a3-7517c20b2520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348054718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3348054718
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2331859160
Short name T746
Test name
Test status
Simulation time 6931643483 ps
CPU time 99.08 seconds
Started Aug 08 07:48:52 PM PDT 24
Finished Aug 08 07:50:31 PM PDT 24
Peak memory 256812 kb
Host smart-6dcc3ecb-06dd-4ea9-b8ad-ae81bbb645ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331859160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2331859160
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.81338939
Short name T364
Test name
Test status
Simulation time 4488394131 ps
CPU time 12.49 seconds
Started Aug 08 07:48:51 PM PDT 24
Finished Aug 08 07:49:04 PM PDT 24
Peak memory 241376 kb
Host smart-3ac603e4-f50e-42e4-81a1-923158dc55c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81338939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.81338939
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1536071773
Short name T163
Test name
Test status
Simulation time 102087679156 ps
CPU time 125.17 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:50:59 PM PDT 24
Peak memory 257740 kb
Host smart-d98a8aff-18c3-4794-addb-bd3cbce315a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536071773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1536071773
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.964326007
Short name T839
Test name
Test status
Simulation time 7762438207 ps
CPU time 18.16 seconds
Started Aug 08 07:48:54 PM PDT 24
Finished Aug 08 07:49:12 PM PDT 24
Peak memory 222708 kb
Host smart-249c6029-cded-491a-91e3-cb387d1b8ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964326007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.964326007
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.775764061
Short name T863
Test name
Test status
Simulation time 233699358 ps
CPU time 2.49 seconds
Started Aug 08 07:48:52 PM PDT 24
Finished Aug 08 07:48:54 PM PDT 24
Peak memory 232884 kb
Host smart-c99d642e-d99f-4ebe-a784-b8d6fc87cca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775764061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.775764061
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1938982743
Short name T477
Test name
Test status
Simulation time 4235433023 ps
CPU time 6.52 seconds
Started Aug 08 07:48:52 PM PDT 24
Finished Aug 08 07:48:58 PM PDT 24
Peak memory 233176 kb
Host smart-340af396-074f-4bb9-ac93-da5970f8bb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938982743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1938982743
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1204111466
Short name T610
Test name
Test status
Simulation time 29089227 ps
CPU time 2.23 seconds
Started Aug 08 07:48:52 PM PDT 24
Finished Aug 08 07:48:54 PM PDT 24
Peak memory 232808 kb
Host smart-0e40e2dc-4d30-476a-9e5b-8b3aa0fc3577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204111466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1204111466
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3861482845
Short name T818
Test name
Test status
Simulation time 199206657 ps
CPU time 5.7 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:48:59 PM PDT 24
Peak memory 219756 kb
Host smart-882b3c92-7d75-401b-8b86-ae5d30563fda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3861482845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3861482845
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1826527528
Short name T146
Test name
Test status
Simulation time 6056682310 ps
CPU time 11.33 seconds
Started Aug 08 07:48:51 PM PDT 24
Finished Aug 08 07:49:03 PM PDT 24
Peak memory 224972 kb
Host smart-440f3eff-fb69-4f4b-80f9-8d84a604c257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826527528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1826527528
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.585834318
Short name T862
Test name
Test status
Simulation time 2634587402 ps
CPU time 27.43 seconds
Started Aug 08 07:48:52 PM PDT 24
Finished Aug 08 07:49:19 PM PDT 24
Peak memory 216700 kb
Host smart-e2977c29-1269-444e-befe-c567e52d18cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585834318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.585834318
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3004171457
Short name T115
Test name
Test status
Simulation time 990313201 ps
CPU time 7.01 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 216636 kb
Host smart-7b7b89d8-02f3-4032-8f2a-3988f4548ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004171457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3004171457
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1530150647
Short name T390
Test name
Test status
Simulation time 279603319 ps
CPU time 2.58 seconds
Started Aug 08 07:48:52 PM PDT 24
Finished Aug 08 07:48:54 PM PDT 24
Peak memory 216664 kb
Host smart-ba1490ef-3c20-42e0-8ac8-ded67e51a877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530150647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1530150647
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1159028830
Short name T487
Test name
Test status
Simulation time 38096386 ps
CPU time 0.8 seconds
Started Aug 08 07:48:50 PM PDT 24
Finished Aug 08 07:48:51 PM PDT 24
Peak memory 206420 kb
Host smart-35d1f845-8722-410c-8c6d-b8f44f74e798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159028830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1159028830
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1478495488
Short name T776
Test name
Test status
Simulation time 1268710237 ps
CPU time 6.69 seconds
Started Aug 08 07:48:54 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 224948 kb
Host smart-3a3e87b9-da4c-4454-ad9d-7b6d33873282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478495488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1478495488
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2867031695
Short name T49
Test name
Test status
Simulation time 15212192 ps
CPU time 0.76 seconds
Started Aug 08 07:49:03 PM PDT 24
Finished Aug 08 07:49:03 PM PDT 24
Peak memory 206184 kb
Host smart-a51f9955-8c0e-4aa3-92db-d10e61c1f44f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867031695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2867031695
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3448502519
Short name T386
Test name
Test status
Simulation time 30780172 ps
CPU time 2.33 seconds
Started Aug 08 07:49:02 PM PDT 24
Finished Aug 08 07:49:04 PM PDT 24
Peak memory 233056 kb
Host smart-a87f35c4-2a95-4429-8e89-b1d05b87aa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448502519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3448502519
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1320165852
Short name T316
Test name
Test status
Simulation time 34517367 ps
CPU time 0.8 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:48:54 PM PDT 24
Peak memory 205996 kb
Host smart-2e14f93a-509c-4fb7-a521-b33cb0104b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320165852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1320165852
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3724263735
Short name T505
Test name
Test status
Simulation time 15754861 ps
CPU time 0.79 seconds
Started Aug 08 07:49:00 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 216172 kb
Host smart-66dfc11f-a261-4840-9b17-0cdd55d4c904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724263735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3724263735
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.678364499
Short name T675
Test name
Test status
Simulation time 25925981915 ps
CPU time 90.1 seconds
Started Aug 08 07:49:01 PM PDT 24
Finished Aug 08 07:50:31 PM PDT 24
Peak memory 241152 kb
Host smart-cd8741cd-3000-4d1a-bd0d-66bbc4ec4eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678364499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.678364499
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.18889846
Short name T149
Test name
Test status
Simulation time 20404891219 ps
CPU time 96.24 seconds
Started Aug 08 07:48:58 PM PDT 24
Finished Aug 08 07:50:35 PM PDT 24
Peak memory 250160 kb
Host smart-e5841aef-de64-4b53-8e7f-e199f8de323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18889846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.18889846
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2319312752
Short name T263
Test name
Test status
Simulation time 761256186 ps
CPU time 12.55 seconds
Started Aug 08 07:48:57 PM PDT 24
Finished Aug 08 07:49:10 PM PDT 24
Peak memory 224848 kb
Host smart-ea3a5ff7-a0d3-46b4-a86d-7d35f1fff2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319312752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2319312752
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1166124881
Short name T715
Test name
Test status
Simulation time 116128100 ps
CPU time 0.78 seconds
Started Aug 08 07:49:03 PM PDT 24
Finished Aug 08 07:49:04 PM PDT 24
Peak memory 216156 kb
Host smart-651d2624-5b01-4f35-b9aa-7ea7d08e8c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166124881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1166124881
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1099697974
Short name T533
Test name
Test status
Simulation time 699618535 ps
CPU time 8.27 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 224952 kb
Host smart-02b2909a-9008-4344-a6ef-8e0d38863830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099697974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1099697974
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2252241676
Short name T461
Test name
Test status
Simulation time 9804955344 ps
CPU time 35.01 seconds
Started Aug 08 07:48:51 PM PDT 24
Finished Aug 08 07:49:26 PM PDT 24
Peak memory 224952 kb
Host smart-4a3190be-4b13-47a2-b31e-19c27f2c2deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252241676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2252241676
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3844824082
Short name T511
Test name
Test status
Simulation time 1223439057 ps
CPU time 5.78 seconds
Started Aug 08 07:48:55 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 233132 kb
Host smart-ff7583a0-554f-4d34-9d74-ad8f054a52f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844824082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3844824082
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3879248610
Short name T721
Test name
Test status
Simulation time 96712162 ps
CPU time 2.17 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:48:55 PM PDT 24
Peak memory 224656 kb
Host smart-cb63ca29-561b-4164-82b1-c364a4d7f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879248610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3879248610
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1123976902
Short name T469
Test name
Test status
Simulation time 160978558 ps
CPU time 4.08 seconds
Started Aug 08 07:49:00 PM PDT 24
Finished Aug 08 07:49:04 PM PDT 24
Peak memory 220468 kb
Host smart-9224602a-b840-4bd9-b736-972160f50a1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1123976902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1123976902
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3133062074
Short name T827
Test name
Test status
Simulation time 160509391 ps
CPU time 2.27 seconds
Started Aug 08 07:48:51 PM PDT 24
Finished Aug 08 07:48:53 PM PDT 24
Peak memory 216732 kb
Host smart-510295b7-0fc1-4522-800f-1535f61cc19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133062074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3133062074
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1504338503
Short name T678
Test name
Test status
Simulation time 22974430 ps
CPU time 0.73 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:48:54 PM PDT 24
Peak memory 206112 kb
Host smart-1b6956dc-4a2c-43a8-88b3-25d3a47a8870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504338503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1504338503
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2728819031
Short name T564
Test name
Test status
Simulation time 78560674 ps
CPU time 2.27 seconds
Started Aug 08 07:48:53 PM PDT 24
Finished Aug 08 07:48:55 PM PDT 24
Peak memory 216720 kb
Host smart-09ff4aa3-37fc-4408-8b4e-b8c0f235d0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728819031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2728819031
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.740149318
Short name T338
Test name
Test status
Simulation time 26623163 ps
CPU time 0.84 seconds
Started Aug 08 07:48:51 PM PDT 24
Finished Aug 08 07:48:52 PM PDT 24
Peak memory 206596 kb
Host smart-0130439d-b416-4fb1-95f6-a6a8ee5466fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740149318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.740149318
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3037511556
Short name T252
Test name
Test status
Simulation time 11087237810 ps
CPU time 9.55 seconds
Started Aug 08 07:48:52 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 224972 kb
Host smart-73e51e27-a652-48c5-9d93-fef887a6f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037511556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3037511556
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1312830767
Short name T646
Test name
Test status
Simulation time 18188311 ps
CPU time 0.8 seconds
Started Aug 08 07:49:01 PM PDT 24
Finished Aug 08 07:49:02 PM PDT 24
Peak memory 205276 kb
Host smart-392c6017-38a5-4eff-9417-ec4aa429c518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312830767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1312830767
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.93818571
Short name T433
Test name
Test status
Simulation time 292175753 ps
CPU time 4.95 seconds
Started Aug 08 07:48:58 PM PDT 24
Finished Aug 08 07:49:03 PM PDT 24
Peak memory 224932 kb
Host smart-e17892b9-e4b7-4456-8df8-463d58e74228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93818571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.93818571
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2097011451
Short name T350
Test name
Test status
Simulation time 19651216 ps
CPU time 0.76 seconds
Started Aug 08 07:48:59 PM PDT 24
Finished Aug 08 07:49:00 PM PDT 24
Peak memory 206984 kb
Host smart-bf587b78-e430-4b43-8508-37c0b04cc6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097011451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2097011451
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.797788535
Short name T152
Test name
Test status
Simulation time 3756407105 ps
CPU time 54.97 seconds
Started Aug 08 07:49:01 PM PDT 24
Finished Aug 08 07:49:56 PM PDT 24
Peak memory 263424 kb
Host smart-87c2576d-acee-4258-9212-0f3141e6a649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797788535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.797788535
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4072602766
Short name T68
Test name
Test status
Simulation time 114370153920 ps
CPU time 298.57 seconds
Started Aug 08 07:49:00 PM PDT 24
Finished Aug 08 07:53:59 PM PDT 24
Peak memory 253352 kb
Host smart-3128f4e6-e447-4199-89b4-39c335a7de01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072602766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4072602766
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1615064381
Short name T739
Test name
Test status
Simulation time 44064601458 ps
CPU time 410.62 seconds
Started Aug 08 07:49:00 PM PDT 24
Finished Aug 08 07:55:51 PM PDT 24
Peak memory 257804 kb
Host smart-66856eac-9bc2-4d8a-8154-ed69b5542f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615064381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1615064381
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.776248093
Short name T589
Test name
Test status
Simulation time 886788515 ps
CPU time 17.55 seconds
Started Aug 08 07:49:03 PM PDT 24
Finished Aug 08 07:49:20 PM PDT 24
Peak memory 238108 kb
Host smart-aa418a15-c6ce-43cd-8968-f8e5d8b0fd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776248093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.776248093
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3968048705
Short name T523
Test name
Test status
Simulation time 3130834373 ps
CPU time 8.94 seconds
Started Aug 08 07:49:01 PM PDT 24
Finished Aug 08 07:49:10 PM PDT 24
Peak memory 233188 kb
Host smart-818a018b-8dd0-4214-b1ad-b3ab25be051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968048705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3968048705
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1464272039
Short name T821
Test name
Test status
Simulation time 4122374146 ps
CPU time 37.96 seconds
Started Aug 08 07:49:02 PM PDT 24
Finished Aug 08 07:49:40 PM PDT 24
Peak memory 234084 kb
Host smart-8e62669b-4017-4637-9c75-79d566f2e671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464272039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1464272039
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2982345226
Short name T921
Test name
Test status
Simulation time 175978078295 ps
CPU time 45.36 seconds
Started Aug 08 07:48:59 PM PDT 24
Finished Aug 08 07:49:45 PM PDT 24
Peak memory 241432 kb
Host smart-13e82458-d9bf-432d-adf2-d999e2a64e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982345226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2982345226
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1315861681
Short name T187
Test name
Test status
Simulation time 4967799323 ps
CPU time 3.6 seconds
Started Aug 08 07:49:03 PM PDT 24
Finished Aug 08 07:49:06 PM PDT 24
Peak memory 225012 kb
Host smart-90c21cb0-5b51-42bf-8c54-4adfa4059094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315861681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1315861681
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3719181065
Short name T359
Test name
Test status
Simulation time 1382897352 ps
CPU time 8.4 seconds
Started Aug 08 07:49:00 PM PDT 24
Finished Aug 08 07:49:09 PM PDT 24
Peak memory 223648 kb
Host smart-39942ee7-892b-45aa-83c4-1194df4a3cab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3719181065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3719181065
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1264237512
Short name T991
Test name
Test status
Simulation time 2464833468 ps
CPU time 16.43 seconds
Started Aug 08 07:49:08 PM PDT 24
Finished Aug 08 07:49:24 PM PDT 24
Peak memory 216620 kb
Host smart-08b410ec-8776-41fb-a8e1-3467baf27269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264237512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1264237512
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3125316077
Short name T665
Test name
Test status
Simulation time 50496535719 ps
CPU time 17.9 seconds
Started Aug 08 07:49:02 PM PDT 24
Finished Aug 08 07:49:20 PM PDT 24
Peak memory 216824 kb
Host smart-5da5e7c0-32c0-4faa-8a4a-2f55a2ab516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125316077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3125316077
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4082275686
Short name T367
Test name
Test status
Simulation time 34801717 ps
CPU time 0.71 seconds
Started Aug 08 07:49:00 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 206012 kb
Host smart-8f90a3b9-7e2c-4db1-a25c-ecd54d104b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082275686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4082275686
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3057911430
Short name T676
Test name
Test status
Simulation time 198604840 ps
CPU time 0.9 seconds
Started Aug 08 07:48:58 PM PDT 24
Finished Aug 08 07:48:59 PM PDT 24
Peak memory 206432 kb
Host smart-da313ee9-d3f6-4682-b0ec-729922596a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057911430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3057911430
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1229933878
Short name T969
Test name
Test status
Simulation time 251628840 ps
CPU time 2.35 seconds
Started Aug 08 07:48:58 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 224916 kb
Host smart-bad89b59-6bbd-4679-b2ad-4d94c3703876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229933878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1229933878
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3712394167
Short name T899
Test name
Test status
Simulation time 15439126 ps
CPU time 0.78 seconds
Started Aug 08 07:49:08 PM PDT 24
Finished Aug 08 07:49:08 PM PDT 24
Peak memory 205768 kb
Host smart-d50358f1-b638-4d9c-8eea-f20bdbe8418c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712394167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3712394167
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2017584971
Short name T436
Test name
Test status
Simulation time 408968117 ps
CPU time 2.39 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:49:10 PM PDT 24
Peak memory 223580 kb
Host smart-57f1804a-ff4f-4d02-850b-1f7b931e8755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017584971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2017584971
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3733972182
Short name T398
Test name
Test status
Simulation time 132364188 ps
CPU time 0.79 seconds
Started Aug 08 07:48:59 PM PDT 24
Finished Aug 08 07:49:00 PM PDT 24
Peak memory 207012 kb
Host smart-a832dc72-2a09-4352-9e24-d8f178cc54e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733972182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3733972182
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1607872660
Short name T622
Test name
Test status
Simulation time 59058486598 ps
CPU time 112.44 seconds
Started Aug 08 07:49:08 PM PDT 24
Finished Aug 08 07:51:01 PM PDT 24
Peak memory 238956 kb
Host smart-ed3daa6a-bd14-473a-bd1f-4d05bd99a6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607872660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1607872660
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4125093148
Short name T200
Test name
Test status
Simulation time 18423909027 ps
CPU time 101.16 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:50:48 PM PDT 24
Peak memory 254804 kb
Host smart-9a5de4ed-5c73-40ad-83ca-d23c8d9f732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125093148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4125093148
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2583949647
Short name T38
Test name
Test status
Simulation time 60063736002 ps
CPU time 339.3 seconds
Started Aug 08 07:49:06 PM PDT 24
Finished Aug 08 07:54:46 PM PDT 24
Peak memory 266000 kb
Host smart-ecbba66a-b2ec-416b-811f-0993f67a7b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583949647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2583949647
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.862397541
Short name T604
Test name
Test status
Simulation time 2213257298 ps
CPU time 21.22 seconds
Started Aug 08 07:49:05 PM PDT 24
Finished Aug 08 07:49:27 PM PDT 24
Peak memory 224968 kb
Host smart-49abf146-390c-4e7e-bdcc-97c2b3fc9608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862397541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.862397541
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1482727793
Short name T457
Test name
Test status
Simulation time 37141530578 ps
CPU time 253.52 seconds
Started Aug 08 07:49:09 PM PDT 24
Finished Aug 08 07:53:23 PM PDT 24
Peak memory 249592 kb
Host smart-622d5d5d-a208-40b6-bdea-fd3e6a176c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482727793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1482727793
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2231644823
Short name T793
Test name
Test status
Simulation time 395053834 ps
CPU time 3.57 seconds
Started Aug 08 07:49:08 PM PDT 24
Finished Aug 08 07:49:12 PM PDT 24
Peak memory 224888 kb
Host smart-f6ffd7f3-db9e-4d78-952d-41461d2e4b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231644823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2231644823
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.965589106
Short name T849
Test name
Test status
Simulation time 9541878530 ps
CPU time 87.75 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:50:35 PM PDT 24
Peak memory 234880 kb
Host smart-34393d8e-e1e1-4736-9380-6ae8df872275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965589106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.965589106
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.794988322
Short name T932
Test name
Test status
Simulation time 1165650878 ps
CPU time 5.24 seconds
Started Aug 08 07:49:06 PM PDT 24
Finished Aug 08 07:49:11 PM PDT 24
Peak memory 224944 kb
Host smart-4c78314e-6808-40db-9bf5-b9b380242936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794988322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.794988322
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1989823034
Short name T153
Test name
Test status
Simulation time 4812957747 ps
CPU time 5.06 seconds
Started Aug 08 07:49:06 PM PDT 24
Finished Aug 08 07:49:11 PM PDT 24
Peak memory 225000 kb
Host smart-d1ab051e-0560-4480-a217-432e68fa82d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989823034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1989823034
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2602543394
Short name T669
Test name
Test status
Simulation time 130434316 ps
CPU time 3.42 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:49:11 PM PDT 24
Peak memory 223544 kb
Host smart-81cd7d80-a97d-4a97-89d7-efa51a395edf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2602543394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2602543394
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3133778669
Short name T792
Test name
Test status
Simulation time 67553958575 ps
CPU time 158.64 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:51:45 PM PDT 24
Peak memory 257860 kb
Host smart-4f1cefbb-a178-412e-86d7-255f58f78785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133778669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3133778669
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2542958092
Short name T453
Test name
Test status
Simulation time 51302071 ps
CPU time 0.81 seconds
Started Aug 08 07:49:00 PM PDT 24
Finished Aug 08 07:49:01 PM PDT 24
Peak memory 206148 kb
Host smart-cadca0b9-3397-4696-a24b-2e79632a2e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542958092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2542958092
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.493553537
Short name T328
Test name
Test status
Simulation time 1013042774 ps
CPU time 4.2 seconds
Started Aug 08 07:49:08 PM PDT 24
Finished Aug 08 07:49:12 PM PDT 24
Peak memory 216656 kb
Host smart-aaf64a8d-81d7-4f4b-9bd2-b8784a694dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493553537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.493553537
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.969092976
Short name T329
Test name
Test status
Simulation time 1364216654 ps
CPU time 3.44 seconds
Started Aug 08 07:49:00 PM PDT 24
Finished Aug 08 07:49:03 PM PDT 24
Peak memory 216656 kb
Host smart-e7a59ab6-a17d-4892-a8ed-b8b277f83584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969092976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.969092976
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1911340784
Short name T786
Test name
Test status
Simulation time 623327566 ps
CPU time 1.03 seconds
Started Aug 08 07:49:08 PM PDT 24
Finished Aug 08 07:49:09 PM PDT 24
Peak memory 206692 kb
Host smart-c4323d61-d321-4179-a351-cdf1244150c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911340784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1911340784
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1739300773
Short name T802
Test name
Test status
Simulation time 17805298402 ps
CPU time 7.72 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:49:15 PM PDT 24
Peak memory 224920 kb
Host smart-bd102b75-729c-4743-a80e-1e9d12a27c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739300773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1739300773
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1253372782
Short name T636
Test name
Test status
Simulation time 13889479 ps
CPU time 0.75 seconds
Started Aug 08 07:49:16 PM PDT 24
Finished Aug 08 07:49:17 PM PDT 24
Peak memory 205872 kb
Host smart-ffd7ec11-f3fb-4777-bd1e-da4136e8554d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253372782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1253372782
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.877234650
Short name T601
Test name
Test status
Simulation time 9270483378 ps
CPU time 9.78 seconds
Started Aug 08 07:49:18 PM PDT 24
Finished Aug 08 07:49:28 PM PDT 24
Peak memory 224948 kb
Host smart-4ad9d123-6316-4dc2-8e68-47f36aa52110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877234650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.877234650
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4116630872
Short name T315
Test name
Test status
Simulation time 18268646 ps
CPU time 0.77 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:49:08 PM PDT 24
Peak memory 206992 kb
Host smart-a4be2a58-6b9f-40ac-93a4-db8fb64487d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116630872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4116630872
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4036504548
Short name T232
Test name
Test status
Simulation time 406496655804 ps
CPU time 158.48 seconds
Started Aug 08 07:49:14 PM PDT 24
Finished Aug 08 07:51:52 PM PDT 24
Peak memory 254376 kb
Host smart-c9a495f0-a8db-4f83-8e8e-41246f8d22df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036504548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4036504548
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.544930976
Short name T940
Test name
Test status
Simulation time 17330164484 ps
CPU time 151.11 seconds
Started Aug 08 07:49:14 PM PDT 24
Finished Aug 08 07:51:45 PM PDT 24
Peak memory 241480 kb
Host smart-148d454b-26f6-4960-8eb5-a34d8b1a7039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544930976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.544930976
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4205751434
Short name T169
Test name
Test status
Simulation time 14230029513 ps
CPU time 120.72 seconds
Started Aug 08 07:49:16 PM PDT 24
Finished Aug 08 07:51:17 PM PDT 24
Peak memory 233268 kb
Host smart-c4729685-8f45-4f80-8919-545874b64238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205751434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4205751434
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1032101031
Short name T957
Test name
Test status
Simulation time 107014026875 ps
CPU time 182.03 seconds
Started Aug 08 07:49:17 PM PDT 24
Finished Aug 08 07:52:19 PM PDT 24
Peak memory 250264 kb
Host smart-a9c7fc95-af1d-43ce-b969-e87c7dbfdbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032101031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1032101031
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1853517750
Short name T340
Test name
Test status
Simulation time 1934757160 ps
CPU time 6.23 seconds
Started Aug 08 07:49:08 PM PDT 24
Finished Aug 08 07:49:15 PM PDT 24
Peak memory 233160 kb
Host smart-0e43bea6-1862-4aa4-a6cc-46d0c4837937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853517750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1853517750
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3808115848
Short name T517
Test name
Test status
Simulation time 379347896 ps
CPU time 7.97 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:49:15 PM PDT 24
Peak memory 237136 kb
Host smart-2841e4b9-b8e1-4594-827d-5fa278adeb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808115848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3808115848
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2514403364
Short name T285
Test name
Test status
Simulation time 2815720197 ps
CPU time 10.96 seconds
Started Aug 08 07:49:06 PM PDT 24
Finished Aug 08 07:49:18 PM PDT 24
Peak memory 237840 kb
Host smart-a15614eb-fde6-493d-8c35-5f753a84d7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514403364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2514403364
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1701856332
Short name T186
Test name
Test status
Simulation time 37475204395 ps
CPU time 15.73 seconds
Started Aug 08 07:49:08 PM PDT 24
Finished Aug 08 07:49:23 PM PDT 24
Peak memory 233204 kb
Host smart-b118ee98-cd61-4e8d-a830-42f88d014b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701856332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1701856332
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1915709661
Short name T782
Test name
Test status
Simulation time 243027420 ps
CPU time 3.66 seconds
Started Aug 08 07:49:15 PM PDT 24
Finished Aug 08 07:49:19 PM PDT 24
Peak memory 219304 kb
Host smart-015edcac-62af-405d-be69-2f5087f2237c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1915709661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1915709661
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3728900699
Short name T361
Test name
Test status
Simulation time 140066420 ps
CPU time 0.96 seconds
Started Aug 08 07:49:17 PM PDT 24
Finished Aug 08 07:49:18 PM PDT 24
Peak memory 207196 kb
Host smart-1fd155af-9c06-4f06-afe7-265da1e7478f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728900699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3728900699
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4160147976
Short name T306
Test name
Test status
Simulation time 2256539603 ps
CPU time 28.11 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:49:35 PM PDT 24
Peak memory 217024 kb
Host smart-606f7e84-bb0f-40c3-86e4-61f2d8bb79c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160147976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4160147976
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2152347382
Short name T502
Test name
Test status
Simulation time 5649209379 ps
CPU time 16.13 seconds
Started Aug 08 07:49:07 PM PDT 24
Finished Aug 08 07:49:23 PM PDT 24
Peak memory 216728 kb
Host smart-c835a816-d245-4b74-92a4-d15b3f46666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152347382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2152347382
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.946093350
Short name T807
Test name
Test status
Simulation time 72015911 ps
CPU time 1.29 seconds
Started Aug 08 07:49:05 PM PDT 24
Finished Aug 08 07:49:06 PM PDT 24
Peak memory 216884 kb
Host smart-f024c85c-067a-4bfc-9b45-25e2ed825657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946093350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.946093350
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2279599204
Short name T478
Test name
Test status
Simulation time 47516902 ps
CPU time 0.9 seconds
Started Aug 08 07:49:09 PM PDT 24
Finished Aug 08 07:49:10 PM PDT 24
Peak memory 206416 kb
Host smart-4789369e-3f45-4bb4-9c19-159f0646d3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279599204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2279599204
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.708717719
Short name T674
Test name
Test status
Simulation time 1202964879 ps
CPU time 6.52 seconds
Started Aug 08 07:49:14 PM PDT 24
Finished Aug 08 07:49:20 PM PDT 24
Peak memory 233196 kb
Host smart-a9dcc3f0-b9f6-4364-9f77-7d54ca1ca820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708717719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.708717719
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3743506993
Short name T737
Test name
Test status
Simulation time 43753585 ps
CPU time 0.73 seconds
Started Aug 08 07:49:25 PM PDT 24
Finished Aug 08 07:49:26 PM PDT 24
Peak memory 206200 kb
Host smart-a1fb2605-4cf5-40a2-b75f-fd8b943b86cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743506993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3743506993
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2027161046
Short name T553
Test name
Test status
Simulation time 98070280 ps
CPU time 2.08 seconds
Started Aug 08 07:49:15 PM PDT 24
Finished Aug 08 07:49:17 PM PDT 24
Peak memory 224856 kb
Host smart-cc3d055a-b393-4c54-ab87-3933f2d3db91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027161046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2027161046
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2192742544
Short name T641
Test name
Test status
Simulation time 37968873 ps
CPU time 0.81 seconds
Started Aug 08 07:49:21 PM PDT 24
Finished Aug 08 07:49:22 PM PDT 24
Peak memory 207024 kb
Host smart-445ea8a2-98f8-46f6-8f49-1651493048e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192742544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2192742544
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2874979368
Short name T844
Test name
Test status
Simulation time 11510310141 ps
CPU time 51.61 seconds
Started Aug 08 07:49:15 PM PDT 24
Finished Aug 08 07:50:07 PM PDT 24
Peak memory 254876 kb
Host smart-a25a197d-2b32-4942-8311-57ac9363cfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874979368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2874979368
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3938115101
Short name T496
Test name
Test status
Simulation time 36850168882 ps
CPU time 94.31 seconds
Started Aug 08 07:49:15 PM PDT 24
Finished Aug 08 07:50:49 PM PDT 24
Peak memory 256372 kb
Host smart-eac22090-6473-40c5-ac74-191f996d45a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938115101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3938115101
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.949654241
Short name T165
Test name
Test status
Simulation time 221593609957 ps
CPU time 209.88 seconds
Started Aug 08 07:49:14 PM PDT 24
Finished Aug 08 07:52:44 PM PDT 24
Peak memory 254296 kb
Host smart-3c0c5a94-8d16-4c7d-9377-62fe5bbd8b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949654241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.949654241
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3212553957
Short name T341
Test name
Test status
Simulation time 5384355832 ps
CPU time 65.43 seconds
Started Aug 08 07:49:15 PM PDT 24
Finished Aug 08 07:50:21 PM PDT 24
Peak memory 250996 kb
Host smart-7296410b-a286-49d1-b60b-39d17faf436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212553957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3212553957
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.198388654
Short name T973
Test name
Test status
Simulation time 27920564126 ps
CPU time 51.46 seconds
Started Aug 08 07:49:13 PM PDT 24
Finished Aug 08 07:50:05 PM PDT 24
Peak memory 254168 kb
Host smart-f8a57fd0-60a7-4321-acd9-23e5e645cccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198388654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.198388654
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3028686478
Short name T837
Test name
Test status
Simulation time 470365821 ps
CPU time 3.7 seconds
Started Aug 08 07:49:20 PM PDT 24
Finished Aug 08 07:49:23 PM PDT 24
Peak memory 233148 kb
Host smart-4cf571b7-9043-4912-a67e-01d37963903b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028686478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3028686478
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4035951007
Short name T714
Test name
Test status
Simulation time 5137831408 ps
CPU time 14.61 seconds
Started Aug 08 07:49:14 PM PDT 24
Finished Aug 08 07:49:29 PM PDT 24
Peak memory 235480 kb
Host smart-f00d15ac-044a-4d77-9a11-bd9e17652ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035951007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4035951007
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1421802842
Short name T233
Test name
Test status
Simulation time 11078470585 ps
CPU time 8.29 seconds
Started Aug 08 07:49:15 PM PDT 24
Finished Aug 08 07:49:23 PM PDT 24
Peak memory 233248 kb
Host smart-ecd501ff-5db3-4e23-80f2-bcc412a57523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421802842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1421802842
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3104464962
Short name T683
Test name
Test status
Simulation time 5443769719 ps
CPU time 12.83 seconds
Started Aug 08 07:49:13 PM PDT 24
Finished Aug 08 07:49:26 PM PDT 24
Peak memory 233172 kb
Host smart-bbb8ac1f-f948-435d-b474-4d858c00d676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104464962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3104464962
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1285636564
Short name T369
Test name
Test status
Simulation time 3253175932 ps
CPU time 10.14 seconds
Started Aug 08 07:49:13 PM PDT 24
Finished Aug 08 07:49:23 PM PDT 24
Peak memory 220820 kb
Host smart-a079e0ff-965a-4046-9435-e4a998c0205c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1285636564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1285636564
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2099719948
Short name T974
Test name
Test status
Simulation time 275164498 ps
CPU time 1.19 seconds
Started Aug 08 07:49:14 PM PDT 24
Finished Aug 08 07:49:16 PM PDT 24
Peak memory 207604 kb
Host smart-4772321f-4ad5-48dc-81f2-2679c4fe78c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099719948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2099719948
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.876726649
Short name T305
Test name
Test status
Simulation time 916575312 ps
CPU time 9.25 seconds
Started Aug 08 07:49:19 PM PDT 24
Finished Aug 08 07:49:29 PM PDT 24
Peak memory 216680 kb
Host smart-8fcae5bd-ebc0-4da9-a264-f16b7322b997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876726649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.876726649
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2108320035
Short name T639
Test name
Test status
Simulation time 342755643 ps
CPU time 2.13 seconds
Started Aug 08 07:49:13 PM PDT 24
Finished Aug 08 07:49:15 PM PDT 24
Peak memory 216500 kb
Host smart-59689483-07aa-44ce-88fd-1277dacd0281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108320035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2108320035
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1995104560
Short name T623
Test name
Test status
Simulation time 79091374 ps
CPU time 1.73 seconds
Started Aug 08 07:49:15 PM PDT 24
Finished Aug 08 07:49:16 PM PDT 24
Peak memory 216748 kb
Host smart-632a053e-fa16-4faf-8db8-45f1840bb714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995104560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1995104560
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4273967283
Short name T560
Test name
Test status
Simulation time 34944421 ps
CPU time 0.75 seconds
Started Aug 08 07:49:14 PM PDT 24
Finished Aug 08 07:49:15 PM PDT 24
Peak memory 206336 kb
Host smart-da52d390-654a-4499-a040-439a5dfa2a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273967283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4273967283
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3082198643
Short name T705
Test name
Test status
Simulation time 1152008959 ps
CPU time 9.88 seconds
Started Aug 08 07:49:21 PM PDT 24
Finished Aug 08 07:49:31 PM PDT 24
Peak memory 233108 kb
Host smart-1dd5262e-8187-4712-8689-aa035ee6007f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082198643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3082198643
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3616920477
Short name T66
Test name
Test status
Simulation time 36862437 ps
CPU time 0.71 seconds
Started Aug 08 07:49:24 PM PDT 24
Finished Aug 08 07:49:25 PM PDT 24
Peak memory 205816 kb
Host smart-489509ce-f6b0-43b4-b844-8f03e795121f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616920477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3616920477
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1939000874
Short name T45
Test name
Test status
Simulation time 403323736 ps
CPU time 4.56 seconds
Started Aug 08 07:49:24 PM PDT 24
Finished Aug 08 07:49:29 PM PDT 24
Peak memory 233064 kb
Host smart-7686b2ec-7fc5-41c6-aa91-2d40e78ef8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939000874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1939000874
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.175212554
Short name T399
Test name
Test status
Simulation time 17841555 ps
CPU time 0.81 seconds
Started Aug 08 07:49:24 PM PDT 24
Finished Aug 08 07:49:25 PM PDT 24
Peak memory 207020 kb
Host smart-8d2b23e3-7fa3-4fc8-9166-b79f1e431303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175212554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.175212554
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1524754893
Short name T205
Test name
Test status
Simulation time 68670558295 ps
CPU time 136.73 seconds
Started Aug 08 07:49:22 PM PDT 24
Finished Aug 08 07:51:39 PM PDT 24
Peak memory 249520 kb
Host smart-9606f2c4-0ba2-4ea3-95b9-5b31459da5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524754893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1524754893
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1409725636
Short name T222
Test name
Test status
Simulation time 61772497421 ps
CPU time 268.96 seconds
Started Aug 08 07:49:23 PM PDT 24
Finished Aug 08 07:53:53 PM PDT 24
Peak memory 266056 kb
Host smart-6eb00893-9acc-41ee-8a63-b3be6a8cce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409725636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1409725636
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3968693005
Short name T631
Test name
Test status
Simulation time 6469492168 ps
CPU time 96.54 seconds
Started Aug 08 07:49:22 PM PDT 24
Finished Aug 08 07:50:59 PM PDT 24
Peak memory 249716 kb
Host smart-103f3f54-291a-4637-8b85-48986735871c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968693005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3968693005
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2957384690
Short name T907
Test name
Test status
Simulation time 5049485479 ps
CPU time 22.04 seconds
Started Aug 08 07:49:25 PM PDT 24
Finished Aug 08 07:49:47 PM PDT 24
Peak memory 233900 kb
Host smart-17d14e71-b1a0-4145-b6a7-886f0a82cc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957384690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2957384690
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1144553390
Short name T878
Test name
Test status
Simulation time 17844151 ps
CPU time 0.78 seconds
Started Aug 08 07:49:24 PM PDT 24
Finished Aug 08 07:49:25 PM PDT 24
Peak memory 216148 kb
Host smart-f8a0da22-c28f-4c89-96c6-4ea7824969b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144553390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1144553390
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1686150580
Short name T284
Test name
Test status
Simulation time 124091644 ps
CPU time 2.71 seconds
Started Aug 08 07:49:23 PM PDT 24
Finished Aug 08 07:49:26 PM PDT 24
Peak memory 224896 kb
Host smart-aaada43e-86a0-49e5-8625-f5d68ee50839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686150580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1686150580
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3364172372
Short name T728
Test name
Test status
Simulation time 19134355564 ps
CPU time 42.18 seconds
Started Aug 08 07:49:22 PM PDT 24
Finished Aug 08 07:50:05 PM PDT 24
Peak memory 233132 kb
Host smart-50567795-6e0b-4368-bbb3-5ce9b6a98c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364172372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3364172372
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3566912275
Short name T912
Test name
Test status
Simulation time 683031361 ps
CPU time 4.92 seconds
Started Aug 08 07:49:22 PM PDT 24
Finished Aug 08 07:49:27 PM PDT 24
Peak memory 241344 kb
Host smart-c73602f0-18e0-481a-8e30-17f6d38f097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566912275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3566912275
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3981872878
Short name T62
Test name
Test status
Simulation time 2613778314 ps
CPU time 6.81 seconds
Started Aug 08 07:49:24 PM PDT 24
Finished Aug 08 07:49:31 PM PDT 24
Peak memory 225000 kb
Host smart-a3229043-4d95-4efc-afd1-9e677eef238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981872878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3981872878
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3276399366
Short name T384
Test name
Test status
Simulation time 1969480677 ps
CPU time 10.25 seconds
Started Aug 08 07:49:24 PM PDT 24
Finished Aug 08 07:49:35 PM PDT 24
Peak memory 222912 kb
Host smart-9b8a047a-cc24-47fe-b808-7086da1171d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3276399366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3276399366
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1112871151
Short name T25
Test name
Test status
Simulation time 34241630992 ps
CPU time 267.35 seconds
Started Aug 08 07:49:27 PM PDT 24
Finished Aug 08 07:53:54 PM PDT 24
Peak memory 257764 kb
Host smart-bf5b2bff-6d53-433e-89eb-4189d295e151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112871151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1112871151
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.321137388
Short name T468
Test name
Test status
Simulation time 12420106165 ps
CPU time 10.18 seconds
Started Aug 08 07:49:22 PM PDT 24
Finished Aug 08 07:49:33 PM PDT 24
Peak memory 216772 kb
Host smart-298fe926-5c86-40a1-b626-49e4c4b2a546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321137388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.321137388
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1244574102
Short name T981
Test name
Test status
Simulation time 250690429 ps
CPU time 2.46 seconds
Started Aug 08 07:49:22 PM PDT 24
Finished Aug 08 07:49:24 PM PDT 24
Peak memory 216632 kb
Host smart-d5005228-8a83-4186-b862-7f33fa13f4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244574102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1244574102
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3930329579
Short name T897
Test name
Test status
Simulation time 163709876 ps
CPU time 1.56 seconds
Started Aug 08 07:49:24 PM PDT 24
Finished Aug 08 07:49:25 PM PDT 24
Peak memory 216644 kb
Host smart-fbba7a7d-c1de-4f3b-9f0d-b87703d0ba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930329579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3930329579
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2145860356
Short name T419
Test name
Test status
Simulation time 14713922 ps
CPU time 0.69 seconds
Started Aug 08 07:49:22 PM PDT 24
Finished Aug 08 07:49:23 PM PDT 24
Peak memory 205956 kb
Host smart-87b6fc8b-dd50-4204-8cf9-f70bd5b68542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145860356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2145860356
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2372475660
Short name T42
Test name
Test status
Simulation time 2871598260 ps
CPU time 12.83 seconds
Started Aug 08 07:49:20 PM PDT 24
Finished Aug 08 07:49:33 PM PDT 24
Peak memory 233192 kb
Host smart-62c5bd84-4f75-4894-8d22-eaa60df37760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372475660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2372475660
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2762729348
Short name T414
Test name
Test status
Simulation time 28249571 ps
CPU time 0.7 seconds
Started Aug 08 07:46:15 PM PDT 24
Finished Aug 08 07:46:16 PM PDT 24
Peak memory 205280 kb
Host smart-8fd62284-e10d-48a7-be12-7f8de92e4542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762729348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
762729348
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2317554998
Short name T250
Test name
Test status
Simulation time 123259054 ps
CPU time 2.44 seconds
Started Aug 08 07:46:16 PM PDT 24
Finished Aug 08 07:46:18 PM PDT 24
Peak memory 224940 kb
Host smart-d9104064-4df7-47d0-8940-24a1d0de2e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317554998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2317554998
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3219270913
Short name T747
Test name
Test status
Simulation time 52401460 ps
CPU time 0.75 seconds
Started Aug 08 07:46:18 PM PDT 24
Finished Aug 08 07:46:19 PM PDT 24
Peak memory 205912 kb
Host smart-3ce13781-7af2-4519-abe1-444e6c50c608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219270913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3219270913
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3721565916
Short name T266
Test name
Test status
Simulation time 1139720243 ps
CPU time 26.36 seconds
Started Aug 08 07:46:19 PM PDT 24
Finished Aug 08 07:46:45 PM PDT 24
Peak memory 239648 kb
Host smart-decedba2-8189-454b-986c-e8815d532709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721565916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3721565916
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.23014148
Short name T1002
Test name
Test status
Simulation time 3877537038 ps
CPU time 40.92 seconds
Started Aug 08 07:46:17 PM PDT 24
Finished Aug 08 07:46:58 PM PDT 24
Peak memory 233320 kb
Host smart-0129e98a-e22b-4716-9b4d-e1dfddbf71b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23014148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.23014148
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1231616984
Short name T270
Test name
Test status
Simulation time 20463558268 ps
CPU time 171.39 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:49:12 PM PDT 24
Peak memory 254940 kb
Host smart-92d6056c-4211-4751-9e13-36738f91da1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231616984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1231616984
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.908882442
Short name T780
Test name
Test status
Simulation time 129625240 ps
CPU time 2.26 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 224924 kb
Host smart-266897dd-19fc-49a3-b529-8d34f30f8e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908882442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.908882442
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2729716391
Short name T924
Test name
Test status
Simulation time 240645309 ps
CPU time 5.65 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:26 PM PDT 24
Peak memory 234192 kb
Host smart-c310d32a-b758-4dbf-9871-4683ab7f661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729716391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2729716391
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3604866808
Short name T611
Test name
Test status
Simulation time 72237195 ps
CPU time 2.22 seconds
Started Aug 08 07:46:14 PM PDT 24
Finished Aug 08 07:46:16 PM PDT 24
Peak memory 224592 kb
Host smart-93ae6f8c-2878-49df-83fb-05d9fccd0d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604866808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3604866808
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3929149949
Short name T890
Test name
Test status
Simulation time 58083324681 ps
CPU time 38.88 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:59 PM PDT 24
Peak memory 239408 kb
Host smart-4ea96716-94af-4e28-ab7d-451a92489864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929149949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3929149949
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.957041476
Short name T790
Test name
Test status
Simulation time 400721075 ps
CPU time 5.1 seconds
Started Aug 08 07:46:12 PM PDT 24
Finished Aug 08 07:46:17 PM PDT 24
Peak memory 233172 kb
Host smart-c4031b06-1b80-429b-a4a6-5211bae0a886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957041476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
957041476
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1180161885
Short name T80
Test name
Test status
Simulation time 1942342596 ps
CPU time 5.81 seconds
Started Aug 08 07:46:16 PM PDT 24
Finished Aug 08 07:46:22 PM PDT 24
Peak memory 233208 kb
Host smart-a7665156-56d1-4e73-8cdb-d74d28dbb1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180161885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1180161885
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3549436089
Short name T32
Test name
Test status
Simulation time 2988115267 ps
CPU time 9.94 seconds
Started Aug 08 07:46:18 PM PDT 24
Finished Aug 08 07:46:28 PM PDT 24
Peak memory 222616 kb
Host smart-21ff3280-c864-4054-a72d-af6e26bf04d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3549436089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3549436089
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.898118088
Short name T320
Test name
Test status
Simulation time 19271524 ps
CPU time 0.77 seconds
Started Aug 08 07:46:15 PM PDT 24
Finished Aug 08 07:46:16 PM PDT 24
Peak memory 206340 kb
Host smart-2edc4ed0-795a-4aa0-8cab-4c7a5ec4a02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898118088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.898118088
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.554625937
Short name T719
Test name
Test status
Simulation time 20045809870 ps
CPU time 14.31 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:35 PM PDT 24
Peak memory 216684 kb
Host smart-1398cfff-f90b-4955-b600-48b355035c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554625937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.554625937
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3521694625
Short name T643
Test name
Test status
Simulation time 110540217 ps
CPU time 0.74 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:21 PM PDT 24
Peak memory 206428 kb
Host smart-4a40c4b5-093b-4053-b8d1-099f42985721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521694625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3521694625
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.208005402
Short name T624
Test name
Test status
Simulation time 89686032 ps
CPU time 0.85 seconds
Started Aug 08 07:46:15 PM PDT 24
Finished Aug 08 07:46:16 PM PDT 24
Peak memory 206368 kb
Host smart-6c5b1484-5689-4443-acd2-e145f7940d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208005402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.208005402
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.589625620
Short name T175
Test name
Test status
Simulation time 3560347311 ps
CPU time 5.8 seconds
Started Aug 08 07:46:16 PM PDT 24
Finished Aug 08 07:46:22 PM PDT 24
Peak memory 225008 kb
Host smart-e7d34dd0-2cfd-463a-b3bb-4d7d7814953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589625620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.589625620
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2591208489
Short name T422
Test name
Test status
Simulation time 12596522 ps
CPU time 0.72 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:34 PM PDT 24
Peak memory 205824 kb
Host smart-11881ba1-c38f-49f0-869f-603ce690b3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591208489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
591208489
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.544947113
Short name T526
Test name
Test status
Simulation time 810653610 ps
CPU time 5.08 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:26 PM PDT 24
Peak memory 233164 kb
Host smart-b3d6f737-ec06-457a-8726-b2ae86beee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544947113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.544947113
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2951278373
Short name T333
Test name
Test status
Simulation time 31274716 ps
CPU time 0.8 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:21 PM PDT 24
Peak memory 206920 kb
Host smart-5a646ed9-ae35-462a-820c-bc273175522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951278373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2951278373
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3052239734
Short name T902
Test name
Test status
Simulation time 2962866875 ps
CPU time 66.45 seconds
Started Aug 08 07:46:26 PM PDT 24
Finished Aug 08 07:47:33 PM PDT 24
Peak memory 253416 kb
Host smart-7dbf51cb-336a-41e0-b831-09a8d372f9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052239734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3052239734
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.579349287
Short name T497
Test name
Test status
Simulation time 12955595752 ps
CPU time 69.02 seconds
Started Aug 08 07:46:25 PM PDT 24
Finished Aug 08 07:47:34 PM PDT 24
Peak memory 249644 kb
Host smart-5921ee75-da47-4cdc-9d7e-6ecd91531f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579349287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
579349287
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3830336559
Short name T44
Test name
Test status
Simulation time 710437538 ps
CPU time 4.07 seconds
Started Aug 08 07:46:14 PM PDT 24
Finished Aug 08 07:46:18 PM PDT 24
Peak memory 225000 kb
Host smart-3ae342a2-2017-4098-a62b-092cfedd9903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830336559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3830336559
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3164619607
Short name T213
Test name
Test status
Simulation time 7685770384 ps
CPU time 85.12 seconds
Started Aug 08 07:46:15 PM PDT 24
Finished Aug 08 07:47:40 PM PDT 24
Peak memory 255424 kb
Host smart-418ec016-6860-4cfb-b7f2-6eb651843987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164619607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3164619607
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2153900484
Short name T179
Test name
Test status
Simulation time 80314045 ps
CPU time 3.38 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:25 PM PDT 24
Peak memory 233152 kb
Host smart-57653615-64fd-476f-a93d-8258be9e35f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153900484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2153900484
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3173143519
Short name T483
Test name
Test status
Simulation time 668759870 ps
CPU time 5.47 seconds
Started Aug 08 07:46:18 PM PDT 24
Finished Aug 08 07:46:24 PM PDT 24
Peak memory 233196 kb
Host smart-59213cb1-74a5-4e3c-a0d8-389f9f69235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173143519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3173143519
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1864515178
Short name T928
Test name
Test status
Simulation time 4860658723 ps
CPU time 14.62 seconds
Started Aug 08 07:46:22 PM PDT 24
Finished Aug 08 07:46:37 PM PDT 24
Peak memory 225044 kb
Host smart-4440b1d6-f2bf-40f5-9530-af5c917c13ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864515178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1864515178
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2805267164
Short name T260
Test name
Test status
Simulation time 4312683361 ps
CPU time 9.11 seconds
Started Aug 08 07:46:19 PM PDT 24
Finished Aug 08 07:46:28 PM PDT 24
Peak memory 233268 kb
Host smart-c50b0658-c8e6-4e58-8894-60ad46f1087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805267164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2805267164
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.972809340
Short name T689
Test name
Test status
Simulation time 508018058 ps
CPU time 5.13 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:26 PM PDT 24
Peak memory 220256 kb
Host smart-51e495be-f135-4736-a351-74c4ed9186bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=972809340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.972809340
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4084602545
Short name T933
Test name
Test status
Simulation time 13460640382 ps
CPU time 121.43 seconds
Started Aug 08 07:46:22 PM PDT 24
Finished Aug 08 07:48:24 PM PDT 24
Peak memory 268044 kb
Host smart-8a2437bd-b55a-4514-b559-66e37b824495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084602545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4084602545
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3698754843
Short name T301
Test name
Test status
Simulation time 2070209561 ps
CPU time 23.77 seconds
Started Aug 08 07:46:20 PM PDT 24
Finished Aug 08 07:46:44 PM PDT 24
Peak memory 216712 kb
Host smart-b5c70086-2fb4-491e-94e3-6e397f186f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698754843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3698754843
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1611814420
Short name T708
Test name
Test status
Simulation time 4070852116 ps
CPU time 3.94 seconds
Started Aug 08 07:46:19 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 216696 kb
Host smart-8a49391a-48a1-4e34-8e53-d7823eac26ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611814420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1611814420
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1562911537
Short name T120
Test name
Test status
Simulation time 279386996 ps
CPU time 3.35 seconds
Started Aug 08 07:46:19 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 216632 kb
Host smart-ea2323c1-7160-4050-938a-e8ab3568c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562911537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1562911537
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4034917872
Short name T946
Test name
Test status
Simulation time 1496828437 ps
CPU time 0.91 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:22 PM PDT 24
Peak memory 206336 kb
Host smart-fb8b30f6-065c-41c4-81e1-67890b145f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034917872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4034917872
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.946416101
Short name T264
Test name
Test status
Simulation time 266701124 ps
CPU time 5.89 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:27 PM PDT 24
Peak memory 233144 kb
Host smart-d628bbc1-cf7d-49d7-8e27-6b96fa6abbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946416101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.946416101
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.479431907
Short name T417
Test name
Test status
Simulation time 64581546 ps
CPU time 0.72 seconds
Started Aug 08 07:46:22 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 206056 kb
Host smart-2820bd5c-051b-4a85-bb16-3c655efbef39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479431907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.479431907
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.735458926
Short name T607
Test name
Test status
Simulation time 965039931 ps
CPU time 6.69 seconds
Started Aug 08 07:46:25 PM PDT 24
Finished Aug 08 07:46:31 PM PDT 24
Peak memory 233120 kb
Host smart-f245553f-92ee-43fa-b118-e4bfa5984e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735458926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.735458926
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3216178398
Short name T406
Test name
Test status
Simulation time 41203956 ps
CPU time 0.75 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:24 PM PDT 24
Peak memory 206888 kb
Host smart-2b6ed3ac-9b1b-4d40-8959-56e00ca415c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216178398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3216178398
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3320186573
Short name T216
Test name
Test status
Simulation time 108088062007 ps
CPU time 180.81 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:49:22 PM PDT 24
Peak memory 249612 kb
Host smart-30ea1c13-7f02-4090-a142-c2251faa7fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320186573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3320186573
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.698221467
Short name T256
Test name
Test status
Simulation time 14782345105 ps
CPU time 44.54 seconds
Started Aug 08 07:46:32 PM PDT 24
Finished Aug 08 07:47:17 PM PDT 24
Peak memory 249608 kb
Host smart-5794e4b7-f393-477e-b62d-dc9467169459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698221467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.698221467
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2676503950
Short name T574
Test name
Test status
Simulation time 22267175024 ps
CPU time 42.11 seconds
Started Aug 08 07:46:25 PM PDT 24
Finished Aug 08 07:47:07 PM PDT 24
Peak memory 225056 kb
Host smart-40cd657c-a93a-4fbd-940b-9169609a882f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676503950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2676503950
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3532065346
Short name T608
Test name
Test status
Simulation time 1366219361 ps
CPU time 5.42 seconds
Started Aug 08 07:46:22 PM PDT 24
Finished Aug 08 07:46:27 PM PDT 24
Peak memory 233116 kb
Host smart-efb78a14-7977-4357-9510-08f457a7ad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532065346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3532065346
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1321595707
Short name T201
Test name
Test status
Simulation time 2538409800 ps
CPU time 59.78 seconds
Started Aug 08 07:46:22 PM PDT 24
Finished Aug 08 07:47:22 PM PDT 24
Peak memory 268840 kb
Host smart-74245ec5-e815-4f2c-b2ce-530ff31a449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321595707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1321595707
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2776572300
Short name T644
Test name
Test status
Simulation time 1155348256 ps
CPU time 6.07 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:30 PM PDT 24
Peak memory 225016 kb
Host smart-a834a0cf-8c3c-4a63-9fd6-b6cf68f9cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776572300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2776572300
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2563031023
Short name T703
Test name
Test status
Simulation time 215613097 ps
CPU time 2.33 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:26 PM PDT 24
Peak memory 224292 kb
Host smart-2c80d1ab-f9cc-442b-8c64-2d7b81643bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563031023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2563031023
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2001891778
Short name T596
Test name
Test status
Simulation time 81103167 ps
CPU time 2.16 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 224552 kb
Host smart-d9577403-1b17-4546-86e7-9837fb879079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001891778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2001891778
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4293540036
Short name T362
Test name
Test status
Simulation time 30893332226 ps
CPU time 10.48 seconds
Started Aug 08 07:46:26 PM PDT 24
Finished Aug 08 07:46:36 PM PDT 24
Peak memory 233200 kb
Host smart-c20ddd8d-f7b2-4802-9a75-fc9fe437f382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293540036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4293540036
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3064859601
Short name T738
Test name
Test status
Simulation time 1517886597 ps
CPU time 6.28 seconds
Started Aug 08 07:46:26 PM PDT 24
Finished Aug 08 07:46:32 PM PDT 24
Peak memory 219720 kb
Host smart-cc7eaa62-5acc-4dc9-860e-d4fba15342cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3064859601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3064859601
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3008000833
Short name T894
Test name
Test status
Simulation time 76700108 ps
CPU time 1.29 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:25 PM PDT 24
Peak memory 215560 kb
Host smart-f360d54d-a813-4312-aa7c-6e49e9f046dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008000833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3008000833
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3554182477
Short name T113
Test name
Test status
Simulation time 6726242962 ps
CPU time 13.93 seconds
Started Aug 08 07:46:24 PM PDT 24
Finished Aug 08 07:46:38 PM PDT 24
Peak memory 216796 kb
Host smart-94cd56f4-c88a-4d64-9d06-90dff1426c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554182477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3554182477
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1461105602
Short name T770
Test name
Test status
Simulation time 449436080 ps
CPU time 3.79 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:27 PM PDT 24
Peak memory 216756 kb
Host smart-6279245c-1dd8-4c01-8a44-82b3ebc3efef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461105602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1461105602
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1901618072
Short name T760
Test name
Test status
Simulation time 44011303 ps
CPU time 1.16 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:23 PM PDT 24
Peak memory 208232 kb
Host smart-09f6c405-d965-4fc9-b7ef-2edb33f4ec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901618072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1901618072
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1973914089
Short name T339
Test name
Test status
Simulation time 10310770 ps
CPU time 0.69 seconds
Started Aug 08 07:46:28 PM PDT 24
Finished Aug 08 07:46:29 PM PDT 24
Peak memory 206012 kb
Host smart-50da1b47-41fd-4ab7-b2fe-7a295a3200d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973914089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1973914089
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4055099183
Short name T181
Test name
Test status
Simulation time 1514007372 ps
CPU time 6.17 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:30 PM PDT 24
Peak memory 224932 kb
Host smart-2232772e-e60d-4a4f-9b93-ea9fa1a74122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055099183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4055099183
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2471417158
Short name T697
Test name
Test status
Simulation time 16805609 ps
CPU time 0.71 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:34 PM PDT 24
Peak memory 205244 kb
Host smart-a74b19d0-408a-4e01-89ec-32429e91349d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471417158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
471417158
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1494369708
Short name T176
Test name
Test status
Simulation time 350660256 ps
CPU time 5.79 seconds
Started Aug 08 07:46:28 PM PDT 24
Finished Aug 08 07:46:34 PM PDT 24
Peak memory 233120 kb
Host smart-46637ddc-758b-4d3e-becf-40ec4a7f43ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494369708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1494369708
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2124142150
Short name T846
Test name
Test status
Simulation time 18863285 ps
CPU time 0.77 seconds
Started Aug 08 07:46:24 PM PDT 24
Finished Aug 08 07:46:25 PM PDT 24
Peak memory 206256 kb
Host smart-5c9cbb11-7170-4f1f-bdfe-d95a9df9c330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124142150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2124142150
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3586015130
Short name T962
Test name
Test status
Simulation time 1970964277 ps
CPU time 25.01 seconds
Started Aug 08 07:46:25 PM PDT 24
Finished Aug 08 07:46:50 PM PDT 24
Peak memory 249996 kb
Host smart-fb4fb891-0da4-476d-a070-6c61e4b1cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586015130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3586015130
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3615021271
Short name T670
Test name
Test status
Simulation time 21485504783 ps
CPU time 145.72 seconds
Started Aug 08 07:46:26 PM PDT 24
Finished Aug 08 07:48:51 PM PDT 24
Peak memory 257752 kb
Host smart-bc2ae173-bc86-4e25-8532-46158a5c7924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615021271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3615021271
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1261110487
Short name T774
Test name
Test status
Simulation time 90896697621 ps
CPU time 420.84 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:53:34 PM PDT 24
Peak memory 273232 kb
Host smart-86a75250-3e21-403e-a63b-48f7bb5f7d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261110487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1261110487
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2790306648
Short name T732
Test name
Test status
Simulation time 3477659609 ps
CPU time 54.4 seconds
Started Aug 08 07:46:32 PM PDT 24
Finished Aug 08 07:47:27 PM PDT 24
Peak memory 233196 kb
Host smart-bb6c37d9-2724-42f7-83cf-775a983ea9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790306648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2790306648
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2638817793
Short name T335
Test name
Test status
Simulation time 3898665916 ps
CPU time 34.05 seconds
Started Aug 08 07:46:25 PM PDT 24
Finished Aug 08 07:47:00 PM PDT 24
Peak memory 241380 kb
Host smart-adfea02c-675c-4146-ab67-585bff3793d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638817793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2638817793
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1553986577
Short name T672
Test name
Test status
Simulation time 391727736 ps
CPU time 7.47 seconds
Started Aug 08 07:46:29 PM PDT 24
Finished Aug 08 07:46:36 PM PDT 24
Peak memory 233132 kb
Host smart-d940c23f-66cf-4da2-b338-3b734fe87709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553986577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1553986577
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2540528540
Short name T627
Test name
Test status
Simulation time 2188300793 ps
CPU time 21.94 seconds
Started Aug 08 07:46:24 PM PDT 24
Finished Aug 08 07:46:46 PM PDT 24
Peak memory 224928 kb
Host smart-91fc8142-813a-4204-a421-41beb24be252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540528540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2540528540
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.995861631
Short name T224
Test name
Test status
Simulation time 1858739168 ps
CPU time 9.75 seconds
Started Aug 08 07:46:28 PM PDT 24
Finished Aug 08 07:46:37 PM PDT 24
Peak memory 224916 kb
Host smart-2320d2f1-31e5-472c-b090-4be1fe0f7202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995861631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
995861631
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3516791920
Short name T733
Test name
Test status
Simulation time 33481197 ps
CPU time 2.58 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:25 PM PDT 24
Peak memory 232808 kb
Host smart-2433cc10-7808-4659-bec7-0f90a8d6f4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516791920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3516791920
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2918665138
Short name T592
Test name
Test status
Simulation time 23363545536 ps
CPU time 11.62 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:44 PM PDT 24
Peak memory 221060 kb
Host smart-707cc939-7855-451e-98b7-e3ea4a29f93d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2918665138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2918665138
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.482004784
Short name T142
Test name
Test status
Simulation time 71408663 ps
CPU time 0.98 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:24 PM PDT 24
Peak memory 206000 kb
Host smart-41a2ed69-75ec-4432-889b-88180b6517cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482004784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.482004784
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.40564869
Short name T543
Test name
Test status
Simulation time 9468996129 ps
CPU time 40.33 seconds
Started Aug 08 07:46:34 PM PDT 24
Finished Aug 08 07:47:14 PM PDT 24
Peak memory 216656 kb
Host smart-7c5792d6-ac31-4df9-a9ff-54c6fe2b3b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40564869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.40564869
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.164544951
Short name T653
Test name
Test status
Simulation time 49077612 ps
CPU time 0.71 seconds
Started Aug 08 07:46:25 PM PDT 24
Finished Aug 08 07:46:26 PM PDT 24
Peak memory 206148 kb
Host smart-ee7e4577-72b6-4163-85b9-34319e77d395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164544951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.164544951
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3876485196
Short name T393
Test name
Test status
Simulation time 274188992 ps
CPU time 1.18 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:24 PM PDT 24
Peak memory 207664 kb
Host smart-e3f9638d-1958-4599-a109-cb560f9cc840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876485196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3876485196
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3389969628
Short name T797
Test name
Test status
Simulation time 596054489 ps
CPU time 0.92 seconds
Started Aug 08 07:46:21 PM PDT 24
Finished Aug 08 07:46:22 PM PDT 24
Peak memory 206404 kb
Host smart-0e0b9f67-fe78-4654-9a80-8d418d0f0f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389969628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3389969628
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1121874382
Short name T858
Test name
Test status
Simulation time 157109950 ps
CPU time 2.19 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:35 PM PDT 24
Peak memory 224532 kb
Host smart-8742795c-d113-4bee-a138-d837c61603a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121874382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1121874382
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.108952322
Short name T378
Test name
Test status
Simulation time 12774120 ps
CPU time 0.71 seconds
Started Aug 08 07:46:39 PM PDT 24
Finished Aug 08 07:46:40 PM PDT 24
Peak memory 206156 kb
Host smart-c929c24c-8992-4633-a88d-9c515ba5ac23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108952322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.108952322
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.509308318
Short name T552
Test name
Test status
Simulation time 907063472 ps
CPU time 6.27 seconds
Started Aug 08 07:46:32 PM PDT 24
Finished Aug 08 07:46:39 PM PDT 24
Peak memory 233024 kb
Host smart-6703fc54-9612-44c6-9015-c74175229f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509308318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.509308318
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2712173277
Short name T865
Test name
Test status
Simulation time 24825694 ps
CPU time 0.75 seconds
Started Aug 08 07:46:27 PM PDT 24
Finished Aug 08 07:46:28 PM PDT 24
Peak memory 206328 kb
Host smart-5b735a0c-5ac3-46a3-ae01-e0965d8c1fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712173277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2712173277
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2816086647
Short name T504
Test name
Test status
Simulation time 856578227 ps
CPU time 17.96 seconds
Started Aug 08 07:46:34 PM PDT 24
Finished Aug 08 07:46:53 PM PDT 24
Peak memory 238992 kb
Host smart-a21af3a4-7a4d-4aee-aa92-c6566b272e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816086647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2816086647
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2610656386
Short name T808
Test name
Test status
Simulation time 110850119187 ps
CPU time 205.48 seconds
Started Aug 08 07:46:34 PM PDT 24
Finished Aug 08 07:50:00 PM PDT 24
Peak memory 255680 kb
Host smart-52e9c019-db53-4611-afb1-c9dbb6a4807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610656386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2610656386
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.294252574
Short name T582
Test name
Test status
Simulation time 12298001875 ps
CPU time 65.65 seconds
Started Aug 08 07:46:32 PM PDT 24
Finished Aug 08 07:47:38 PM PDT 24
Peak memory 253864 kb
Host smart-957d4d1b-bcb2-4dcd-9e89-89ae80a5548c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294252574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
294252574
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3040117675
Short name T935
Test name
Test status
Simulation time 1948149079 ps
CPU time 13.8 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:49 PM PDT 24
Peak memory 233096 kb
Host smart-a98818a6-a87e-4e0a-9b4e-99cbcdf9059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040117675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3040117675
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2635137040
Short name T885
Test name
Test status
Simulation time 1088980173 ps
CPU time 23.07 seconds
Started Aug 08 07:46:34 PM PDT 24
Finished Aug 08 07:46:57 PM PDT 24
Peak memory 241656 kb
Host smart-617f311b-0564-4c17-a53b-b2f1758091b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635137040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2635137040
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3153161260
Short name T254
Test name
Test status
Simulation time 6061672980 ps
CPU time 12.4 seconds
Started Aug 08 07:46:34 PM PDT 24
Finished Aug 08 07:46:47 PM PDT 24
Peak memory 233220 kb
Host smart-5d957cda-3d19-4061-ba9e-c7bd3093f458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153161260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3153161260
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1811521781
Short name T499
Test name
Test status
Simulation time 1773057619 ps
CPU time 10.46 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:46 PM PDT 24
Peak memory 249512 kb
Host smart-f36cc910-8250-4106-a6de-c79879d65aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811521781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1811521781
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1628675596
Short name T606
Test name
Test status
Simulation time 955901922 ps
CPU time 6.52 seconds
Started Aug 08 07:46:23 PM PDT 24
Finished Aug 08 07:46:29 PM PDT 24
Peak memory 240916 kb
Host smart-bb9d8155-1ab3-4330-9bc2-d73fb8b99584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628675596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1628675596
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2231106028
Short name T605
Test name
Test status
Simulation time 5135685962 ps
CPU time 9.81 seconds
Started Aug 08 07:46:29 PM PDT 24
Finished Aug 08 07:46:39 PM PDT 24
Peak memory 233172 kb
Host smart-f065d374-d8fb-45c4-a83f-9995dfd54d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231106028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2231106028
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1458730375
Short name T1004
Test name
Test status
Simulation time 4327576500 ps
CPU time 10.97 seconds
Started Aug 08 07:46:35 PM PDT 24
Finished Aug 08 07:46:46 PM PDT 24
Peak memory 223124 kb
Host smart-95792a23-9e50-46f4-8668-59217393c7a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1458730375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1458730375
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2658387991
Short name T918
Test name
Test status
Simulation time 74421827 ps
CPU time 1.22 seconds
Started Aug 08 07:46:33 PM PDT 24
Finished Aug 08 07:46:34 PM PDT 24
Peak memory 207488 kb
Host smart-c3eabfb4-1fb2-4828-9a37-b95f419852e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658387991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2658387991
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4080544518
Short name T423
Test name
Test status
Simulation time 1184383520 ps
CPU time 11.73 seconds
Started Aug 08 07:46:28 PM PDT 24
Finished Aug 08 07:46:40 PM PDT 24
Peak memory 220152 kb
Host smart-41c67b97-1fe0-464b-9ad5-a2650d55c691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080544518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4080544518
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.15858094
Short name T787
Test name
Test status
Simulation time 4134111609 ps
CPU time 9.24 seconds
Started Aug 08 07:46:28 PM PDT 24
Finished Aug 08 07:46:37 PM PDT 24
Peak memory 216636 kb
Host smart-a2b70b34-62c3-4a70-b747-9ee5871c79ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15858094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.15858094
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3704631015
Short name T435
Test name
Test status
Simulation time 39391746 ps
CPU time 0.76 seconds
Started Aug 08 07:46:29 PM PDT 24
Finished Aug 08 07:46:30 PM PDT 24
Peak memory 206352 kb
Host smart-20e054de-9318-4929-be78-d1c0a98f3ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704631015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3704631015
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.914345074
Short name T602
Test name
Test status
Simulation time 25453117 ps
CPU time 0.73 seconds
Started Aug 08 07:46:25 PM PDT 24
Finished Aug 08 07:46:26 PM PDT 24
Peak memory 206400 kb
Host smart-a982bff3-71fc-4444-94bb-2d44bd5da81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914345074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.914345074
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3149359458
Short name T750
Test name
Test status
Simulation time 85718238 ps
CPU time 2.31 seconds
Started Aug 08 07:46:37 PM PDT 24
Finished Aug 08 07:46:40 PM PDT 24
Peak memory 224572 kb
Host smart-ff9419a6-5774-4936-afe1-73ac51f3464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149359458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3149359458
Directory /workspace/9.spi_device_upload/latest
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