Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2707755	1			T1	24716		T2	30793		T3	1639
all_values[1]	2707755	1			T1	24716		T2	30793		T3	1639
all_values[2]	2707755	1			T1	24716		T2	30793		T3	1639
all_values[3]	2707755	1			T1	24716		T2	30793		T3	1639
all_values[4]	2707755	1			T1	24716		T2	30793		T3	1639
all_values[5]	2707755	1			T1	24716		T2	30793		T3	1639
all_values[6]	2707755	1			T1	24716		T2	30793		T3	1639
all_values[7]	2707755	1			T1	24716		T2	30793		T3	1639

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20927334

1

T1

197728

T2

246344

T3

13112

auto[1]

734706

1

T15

162409

T16

37

T17

70

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21635438

1

T1

197701

T2

246118

T3

13112

auto[1]

26602

1

T1

27

T2

226

T11

63

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2571210	1			T1	24705		T2	30649		T3	1639
all_values[0]	auto[0]	auto[1]	12497	1			T1	11		T2	144		T11	29
all_values[0]	auto[1]	auto[0]	123448	1			T15	3		T17	8		T18	6176
all_values[0]	auto[1]	auto[1]	600	1			T16	1		T17	1		T18	27
all_values[1]	auto[0]	auto[0]	2630982	1			T1	24708		T2	30711		T3	1639
all_values[1]	auto[0]	auto[1]	8192	1			T1	8		T2	82		T11	29
all_values[1]	auto[1]	auto[0]	68247	1			T15	32363		T16	4		T17	5
all_values[1]	auto[1]	auto[1]	334	1			T15	115		T16	2		T17	2
all_values[2]	auto[0]	auto[0]	2596331	1			T1	24708		T2	30793		T3	1639
all_values[2]	auto[0]	auto[1]	2869	1			T1	8		T11	5		T42	120
all_values[2]	auto[1]	auto[0]	108304	1			T15	32451		T17	7		T18	6198
all_values[2]	auto[1]	auto[1]	251	1			T15	28		T16	1		T17	6
all_values[3]	auto[0]	auto[0]	2612371	1			T1	24716		T2	30793		T3	1639
all_values[3]	auto[0]	auto[1]	186	1			T15	1		T17	5		T18	1
all_values[3]	auto[1]	auto[0]	95015	1			T15	32475		T16	3		T17	3
all_values[3]	auto[1]	auto[1]	183	1			T15	4		T16	3		T17	2
all_values[4]	auto[0]	auto[0]	2641028	1			T1	24716		T2	30793		T3	1639
all_values[4]	auto[0]	auto[1]	184	1			T15	5		T16	1		T17	4
all_values[4]	auto[1]	auto[0]	66341	1			T15	2		T16	5		T17	4
all_values[4]	auto[1]	auto[1]	202	1			T15	2		T17	5		T18	3
all_values[5]	auto[0]	auto[0]	2649851	1			T1	24716		T2	30793		T3	1639
all_values[5]	auto[0]	auto[1]	170	1			T15	3		T16	2		T17	6
all_values[5]	auto[1]	auto[0]	57544	1			T15	1		T16	5		T17	4
all_values[5]	auto[1]	auto[1]	190	1			T15	2		T17	1		T18	2
all_values[6]	auto[0]	auto[0]	2588438	1			T1	24716		T2	30793		T3	1639
all_values[6]	auto[0]	auto[1]	191	1			T17	1		T18	1		T19	5
all_values[6]	auto[1]	auto[0]	118973	1			T15	32480		T16	6		T17	9
all_values[6]	auto[1]	auto[1]	153	1			T15	4		T17	4		T19	2
all_values[7]	auto[0]	auto[0]	2612626	1			T1	24716		T2	30793		T3	1639
all_values[7]	auto[0]	auto[1]	208	1			T15	1		T17	2		T18	3
all_values[7]	auto[1]	auto[0]	94729	1			T15	32478		T16	7		T17	5
all_values[7]	auto[1]	auto[1]	192	1			T15	1		T17	4		T18	5