Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35896	1			T1	45		T2	149		T3	388
auto[SpiFlashAddrCfg]	8067	1			T1	13		T2	42		T3	26
auto[SpiFlashAddr3b]	9620	1			T1	19		T2	52		T3	33
auto[SpiFlashAddr4b]	7844	1			T1	6		T2	44		T3	23

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35632

1

T1

48

T2

158

T3

173

auto[1]

25795

1

T1

35

T2

129

T3

297

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32139

1

T1

49

T2

153

T3

191

auto[1]

29288

1

T1

34

T2

134

T3

279

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40653	1			T1	57		T2	191		T3	399
values[1]	1142	1			T1	2		T2	10		T3	2
values[2]	1525	1			T2	6		T5	17		T8	2
values[3]	1603	1			T1	2		T2	7		T3	5
values[4]	1541	1			T2	2		T3	4		T4	4
values[5]	1540	1			T1	3		T2	8		T3	5
values[6]	1550	1			T1	1		T2	12		T3	1
values[7]	1587	1			T1	3		T2	4		T3	6
values[8]	10286	1			T1	15		T2	47		T3	48

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31850

1

T3

470

T4

14

T5

194

auto[1]

29577

1

T1

83

T2

287

T34

100

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58012

1

T1

81

T2

262

T3

452

write

3415

1

T1

2

T2

25

T3

18

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20331

1

T1

37

T2

103

T3

64

valids[0x1]

41096

1

T1

46

T2

184

T3

406

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1620	1			T1	3		T2	14		T3	7
internal_process_ops[0x5a]	1589	1			T1	3		T2	7		T3	4
internal_process_ops[0x05]	21298	1			T1	10		T2	55		T3	340
internal_process_ops[0x35]	1621	1			T1	6		T2	4		T3	2
internal_process_ops[0x15]	1625	1			T1	4		T2	7		T3	4
internal_process_ops[0x03]	1125	1			T1	2		T2	4		T3	4
internal_process_ops[0x0b]	1106	1			T1	1		T2	3		T3	2
internal_process_ops[0x3b]	1150	1			T2	2		T3	4		T5	9
internal_process_ops[0x6b]	1109	1			T1	1		T2	3		T3	7
internal_process_ops[0xbb]	1059	1			T1	1		T2	2		T3	2
internal_process_ops[0xeb]	1110	1			T2	2		T3	3		T5	9

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59732

1

T1

82

T2

267

T3

463

auto[1]

1695

1

T1

1

T2

20

T3

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58970

1

T1

80

T2

270

T3

456

auto[1]

2457

1

T1

3

T2

17

T3

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10785

1

T3

132

T5

57

T8

45

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6400

1

T3

249

T4

4

T5

27

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2237

1

T3

4

T5

29

T8

7

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1856

1

T3

17

T4

6

T5

23

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2623

1

T3

13

T5

8

T8

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2279

1

T3

18

T4

2

T5

19

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2070

1

T3

10

T5

15

T8

17

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1931

1

T3

9

T4

2

T5

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

112

1

T3

3

T13

1

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

93

1

T3

4

T8

2

T13

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

97

1

T13

1

T36

1

T174

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

95

1

T8

1

T13

2

T174

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T3

2

T13

2

T42

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

90

1

T5

1

T8

1

T13

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

101

1

T3

2

T11

2

T13

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T3

1

T13

1

T40

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

128

1

T3

2

T42

5

T174

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

107

1

T5

1

T13

3

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

100

1

T8

2

T13

3

T15

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

132

1

T8

1

T13

2

T14

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T3

1

T13

1

T35

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

104

1

T3

2

T5

3

T11

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

96

1

T3

1

T8

2

T11

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

99

1

T5

1

T8

1

T11

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11092

1

T1

28

T2

83

T34

40

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6771

1

T1

16

T2

58

T34

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1574

1

T1

7

T2

16

T34

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1561

1

T1

5

T2

23

T34

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1974

1

T1

10

T2

23

T34

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1839

1

T1

9

T2

20

T34

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1542

1

T1

3

T2

19

T34

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1478

1

T1

3

T2

20

T34

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T25

3

T15

2

T16

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

124

1

T2

7

T34

2

T96

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

133

1

T2

1

T34

3

T96

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

88

1

T1

1

T25

2

T181

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T34

1

T25

3

T96

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

107

1

T2

1

T96

4

T182

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

105

1

T1

1

T25

3

T181

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

111

1

T2

2

T96

1

T181

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T2

1

T34

1

T96

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

123

1

T2

4

T25

1

T181

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

122

1

T2

3

T25

1

T181

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

105

1

T2

1

T25

2

T96

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

109

1

T96

2

T181

5

T182

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

115

1

T2

4

T34

1

T96

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

94

1

T181

1

T182

1

T183

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T2

1

T25

1

T182

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4100	1			T3	21		T5	31		T8	32
auto[0]	values[0]	valids[0x1]	15988	1			T3	378		T4	4		T5	61
auto[0]	values[1]	valids[0x1]	590	1			T3	2		T5	7		T8	4
auto[0]	values[2]	valids[0x0]	540	1			T5	4		T8	2		T11	2
auto[0]	values[2]	valids[0x1]	346	1			T5	13		T13	2		T36	4
auto[0]	values[3]	valids[0x0]	611	1			T3	2		T4	2		T5	5
auto[0]	values[3]	valids[0x1]	304	1			T3	3		T5	1		T13	4
auto[0]	values[4]	valids[0x0]	541	1			T3	2		T4	4		T5	6
auto[0]	values[4]	valids[0x1]	298	1			T3	2		T5	1		T8	3
auto[0]	values[5]	valids[0x0]	584	1			T3	5		T8	2		T11	2
auto[0]	values[5]	valids[0x1]	304	1			T4	2		T11	1		T13	4
auto[0]	values[6]	valids[0x0]	585	1			T3	1		T5	1		T8	2
auto[0]	values[6]	valids[0x1]	337	1			T5	4		T8	4		T11	1
auto[0]	values[7]	valids[0x0]	580	1			T3	2		T5	2		T8	8
auto[0]	values[7]	valids[0x1]	311	1			T3	4		T5	1		T8	2
auto[0]	values[8]	valids[0x0]	3656	1			T3	31		T4	2		T5	39
auto[0]	values[8]	valids[0x1]	2175	1			T3	17		T5	18		T8	16
auto[1]	values[0]	valids[0x0]	4152	1			T1	24		T2	62		T34	28
auto[1]	values[0]	valids[0x1]	16413	1			T1	33		T2	129		T34	29
auto[1]	values[1]	valids[0x1]	552	1			T1	2		T2	10		T25	4
auto[1]	values[2]	valids[0x0]	365	1			T2	1		T25	3		T96	8
auto[1]	values[2]	valids[0x1]	274	1			T2	5		T34	3		T181	1
auto[1]	values[3]	valids[0x0]	371	1			T1	2		T2	3		T25	4
auto[1]	values[3]	valids[0x1]	317	1			T2	4		T25	2		T96	4
auto[1]	values[4]	valids[0x0]	422	1			T2	1		T34	3		T25	10
auto[1]	values[4]	valids[0x1]	280	1			T2	1		T34	4		T25	3
auto[1]	values[5]	valids[0x0]	385	1			T1	2		T2	1		T34	1
auto[1]	values[5]	valids[0x1]	267	1			T1	1		T2	7		T34	5
auto[1]	values[6]	valids[0x0]	372	1			T1	1		T2	7		T34	1
auto[1]	values[6]	valids[0x1]	256	1			T2	5		T96	1		T181	1
auto[1]	values[7]	valids[0x0]	411	1			T1	1		T2	2		T34	3
auto[1]	values[7]	valids[0x1]	285	1			T1	2		T2	2		T34	1
auto[1]	values[8]	valids[0x0]	2656	1			T1	7		T2	26		T34	19
auto[1]	values[8]	valids[0x1]	1799	1			T1	8		T2	21		T34	3