Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3361960

1

T1

4118

T2

7544

T3

10657

auto[1]

29513

1

T1

3

T2

47

T3

330

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

809225

1

T1

23

T2

87

T3

66

auto[1]

2582248

1

T1

4098

T2

7504

T3

10921

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	655208	1			T1	139		T2	522		T3	2833
auto[524288:1048575]	400949	1			T1	298		T2	3801		T3	3
auto[1048576:1572863]	397539	1			T2	13		T3	795		T5	2189
auto[1572864:2097151]	403913	1			T1	2839		T2	604		T3	551
auto[2097152:2621439]	349531	1			T1	390		T2	2		T3	93
auto[2621440:3145727]	367406	1			T1	192		T2	2638		T3	3406
auto[3145728:3670015]	402764	1			T1	261		T2	5		T3	3005
auto[3670016:4194303]	414163	1			T1	2		T2	6		T3	301

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2619337

1

T1

4121

T2

7583

T3

10978

auto[1]

772136

1

T2

8

T3

9

T5

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2906970

1

T1

3024

T2

7200

T3

10552

auto[1]

484503

1

T1

1097

T2

391

T3

435

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	208189	1			T1	4		T2	6		T3	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	369112	1			T1	135		T2	514		T3	2605
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	68460	1			T1	1		T2	13		T3	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	264955	1			T1	169		T2	3781		T5	2271
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	86911	1			T2	8		T3	9		T5	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	256912	1			T2	2		T3	714		T5	2175
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	83567	1			T2	6		T3	1		T5	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	268004	1			T1	2065		T2	596		T3	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	87875	1			T1	2		T2	2		T3	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	194940	1			T1	388		T3	3		T5	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	85500	1			T1	2		T2	27		T3	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	225632	1			T2	2187		T3	3393		T5	517
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	82758	1			T1	3		T2	5		T3	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	249176	1			T1	252		T3	2990		T5	2819
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	83591	1			T1	2		T2	1		T3	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	267518	1			T2	5		T3	257		T5	2170
auto[0]	auto[1]	auto[0:524287]	auto[0]	1652	1			T8	2		T181	7		T15	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	72338	1			T3	128		T8	258		T181	1795
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	3632	1			T8	2		T11	2		T13	13
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	59140	1			T1	128		T8	1911		T13	4374
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1767	1			T3	1		T8	2		T13	17
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	48459	1			T13	128		T96	128		T181	1988
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2483	1			T1	4		T3	7		T13	22
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	45653	1			T1	769		T3	258		T13	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3767	1			T8	1		T25	2		T96	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59333	1			T25	385		T36	257		T15	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	742	1			T1	1		T2	2		T3	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	52280	1			T1	188		T2	389		T8	1313
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1006	1			T1	1		T3	4		T34	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	66369	1			T1	4		T3	1		T181	641
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	3039	1			T5	3		T13	5		T34	12
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	57200	1			T34	128		T96	526		T42	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	534	1			T2	2		T3	3		T11	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2975	1			T3	93		T11	4		T35	24
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	457	1			T2	3		T8	1		T182	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3347	1			T2	4		T8	8		T182	25
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	441	1			T2	2		T3	3		T5	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2634	1			T2	1		T3	68		T5	8
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	444	1			T2	2		T5	1		T34	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3052	1			T5	3		T25	3		T182	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	405	1			T3	3		T8	3		T11	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2671	1			T3	78		T8	32		T11	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	397	1			T2	8		T3	1		T11	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1488	1			T2	25		T3	6		T11	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	468	1			T1	1		T5	1		T13	11
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2407	1			T13	4		T25	2		T181	26
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	346	1			T3	1		T8	2		T13	11
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1804	1			T3	39		T8	22		T25	7
auto[1]	auto[1]	auto[0:524287]	auto[0]	93	1			T8	2		T181	2		T225	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	315	1			T8	6		T181	12		T225	63
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	105	1			T42	1		T178	1		T16	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	853	1			T178	1		T16	9		T197	11
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	108	1			T181	1		T15	1		T16	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	307	1			T181	26		T15	6		T16	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	116	1			T1	1		T3	2		T195	10
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	594	1			T3	27		T195	55		T209	11
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	56	1			T25	1		T15	2		T209	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	484	1			T15	8		T209	1		T31	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	129	1			T1	1		T8	1		T13	8
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1238	1			T8	12		T34	4		T181	25
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	97	1			T3	1		T34	2		T181	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	483	1			T3	5		T181	1		T209	7
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	90	1			T42	1		T209	1		T16	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	575	1			T42	5		T209	2		T16	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2124320	1			T1	3023		T2	7150		T3	10254
auto[0]	auto[0]	auto[1]	758780	1			T2	3		T3	3		T5	1
auto[0]	auto[1]	auto[0]	466234	1			T1	1095		T2	391		T3	397
auto[0]	auto[1]	auto[1]	12626	1			T3	3		T8	2		T181	3
auto[1]	auto[0]	auto[0]	23269	1			T1	1		T2	42		T3	292
auto[1]	auto[0]	auto[1]	601	1			T2	5		T3	3		T5	2
auto[1]	auto[1]	auto[0]	5514	1			T1	2		T3	35		T8	19
auto[1]	auto[1]	auto[1]	129	1			T8	2		T13	1		T34	1