Group : spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 9 0 9 100.00
Crosses 8 0 8 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_is_write 2 0 2 100.00 100 1 1 0
cp_payload_size 7 0 7 100.00 100 1 1 0


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 8 0 8 100.00 100 1 1 0


Summary for Variable cp_is_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_is_write

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
read 803 1 T1 2 T2 11 T3 2
write 1594 1 T1 1 T2 6 T3 12



Summary for Variable cp_payload_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for cp_payload_size

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
excess_fifo 581 1 T1 1 T2 1 T3 7
frequent_use_values[0] 849 1 T1 2 T2 11 T3 2
frequent_use_values[1] 56 1 T181 1 T182 1 T42 1
frequent_use_values[2] 60 1 T11 1 T13 1 T183 1
frequent_use_values[3] 63 1 T2 1 T13 2 T96 1
frequent_use_values[4] 64 1 T3 1 T43 1 T15 1
frequent_use_values[256] 349 1 T2 2 T3 2 T5 1



Summary for Cross cr_all

Samples crossed: cp_is_write cp_payload_size
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_all

Bins
cp_is_write   cp_payload_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
read frequent_use_values[0] 803 1 T1 2 T2 11 T3 2
write excess_fifo 581 1 T1 1 T2 1 T3 7
write frequent_use_values[0] 46 1 T13 1 T34 1 T35 2
write frequent_use_values[1] 56 1 T181 1 T182 1 T42 1
write frequent_use_values[2] 60 1 T11 1 T13 1 T183 1
write frequent_use_values[3] 63 1 T2 1 T13 2 T96 1
write frequent_use_values[4] 64 1 T3 1 T43 1 T15 1
write frequent_use_values[256] 349 1 T2 2 T3 2 T5 1


User Defined Cross Bins for cr_all

Excluded/Illegal bins
NAMECOUNTSTATUS
read_w_nonzero_payload 0 Illegal