Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2707755	1			T1	24716		T2	30793		T3	1639
all_pins[1]	2707755	1			T1	24716		T2	30793		T3	1639
all_pins[2]	2707755	1			T1	24716		T2	30793		T3	1639
all_pins[3]	2707755	1			T1	24716		T2	30793		T3	1639
all_pins[4]	2707755	1			T1	24716		T2	30793		T3	1639
all_pins[5]	2707755	1			T1	24716		T2	30793		T3	1639
all_pins[6]	2707755	1			T1	24716		T2	30793		T3	1639
all_pins[7]	2707755	1			T1	24716		T2	30793		T3	1639

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21540278	1			T1	197728		T2	246344		T3	13112
values[0x1]	121762	1			T15	32621		T16	7		T17	25
transitions[0x0=>0x1]	120981	1			T15	32588		T16	7		T17	19
transitions[0x1=>0x0]	120992	1			T15	32588		T16	7		T17	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2707069	1			T1	24716		T2	30793		T3	1639
all_pins[0]	values[0x1]	686	1			T16	1		T17	1		T18	33
all_pins[0]	transitions[0x0=>0x1]	596	1			T16	1		T17	1		T18	5
all_pins[0]	transitions[0x1=>0x0]	266	1			T15	122		T16	2		T17	2
all_pins[1]	values[0x0]	2707399	1			T1	24716		T2	30793		T3	1639
all_pins[1]	values[0x1]	356	1			T15	122		T16	2		T17	2
all_pins[1]	transitions[0x0=>0x1]	264	1			T15	92		T16	2		T17	1
all_pins[1]	transitions[0x1=>0x0]	175	1			T16	1		T17	5		T18	2
all_pins[2]	values[0x0]	2707488	1			T1	24716		T2	30793		T3	1639
all_pins[2]	values[0x1]	267	1			T15	30		T16	1		T17	6
all_pins[2]	transitions[0x0=>0x1]	202	1			T15	30		T16	1		T17	4
all_pins[2]	transitions[0x1=>0x0]	118	1			T15	4		T16	3		T30	3
all_pins[3]	values[0x0]	2707572	1			T1	24716		T2	30793		T3	1639
all_pins[3]	values[0x1]	183	1			T15	4		T16	3		T17	2
all_pins[3]	transitions[0x0=>0x1]	135	1			T15	3		T16	3		T17	1
all_pins[3]	transitions[0x1=>0x0]	154	1			T15	1		T17	4		T18	3
all_pins[4]	values[0x0]	2707553	1			T1	24716		T2	30793		T3	1639
all_pins[4]	values[0x1]	202	1			T15	2		T17	5		T18	3
all_pins[4]	transitions[0x0=>0x1]	161	1			T15	1		T17	5		T18	2
all_pins[4]	transitions[0x1=>0x0]	1165	1			T15	1		T17	1		T18	1
all_pins[5]	values[0x0]	2706549	1			T1	24716		T2	30793		T3	1639
all_pins[5]	values[0x1]	1206	1			T15	2		T17	1		T18	2
all_pins[5]	transitions[0x0=>0x1]	861	1			T15	1		T18	2		T19	1
all_pins[5]	transitions[0x1=>0x0]	118325	1			T15	32459		T17	3		T19	2
all_pins[6]	values[0x0]	2589085	1			T1	24716		T2	30793		T3	1639
all_pins[6]	values[0x1]	118670	1			T15	32460		T17	4		T19	2
all_pins[6]	transitions[0x0=>0x1]	118630	1			T15	32460		T17	3		T19	2
all_pins[6]	transitions[0x1=>0x0]	152	1			T15	1		T17	3		T18	5
all_pins[7]	values[0x0]	2707563	1			T1	24716		T2	30793		T3	1639
all_pins[7]	values[0x1]	192	1			T15	1		T17	4		T18	5
all_pins[7]	transitions[0x0=>0x1]	132	1			T15	1		T17	4		T18	3
all_pins[7]	transitions[0x1=>0x0]	637	1			T16	1		T17	1		T18	31