Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18562

1

T3

173

T5

114

T8

91

auto[1]

13288

1

T3

297

T4

14

T5

80

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3837	1			T3	88		T5	20		T8	48
values[1]	4089	1			T3	81		T5	20		T8	110
values[2]	4229	1			T3	78		T5	29		T8	26
values[3]	4823	1			T3	112		T4	14		T5	85
values[4]	3388	1			T5	20		T8	20		T11	24
values[5]	3876	1			T11	27		T13	40		T14	16
values[6]	3324	1			T13	20		T95	8		T40	24
values[7]	4284	1			T3	111		T5	20		T8	47

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3812	1			T3	20		T5	20		T8	20
values[1]	4170	1			T3	49		T5	25		T13	80
values[2]	4094	1			T3	88		T5	69		T8	20
values[3]	3414	1			T3	141		T5	20		T13	80
values[4]	3619	1			T5	20		T8	50		T11	20
values[5]	4474	1			T3	91		T8	48		T12	20
values[6]	4386	1			T3	81		T5	20		T8	46
values[7]	3881	1			T4	14		T5	20		T8	67

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	371	1			T209	12		T92	20		T246	12
auto[0]	values[0]	values[1]	177	1			T13	10		T97	12		T221	10
auto[0]	values[0]	values[2]	303	1			T3	83		T45	17		T220	12
auto[0]	values[0]	values[3]	278	1			T5	13		T223	13		T221	15
auto[0]	values[0]	values[4]	210	1			T223	16		T61	53		T18	11
auto[0]	values[0]	values[5]	272	1			T8	10		T91	24		T45	14
auto[0]	values[0]	values[6]	330	1			T210	9		T208	8		T218	15
auto[0]	values[0]	values[7]	277	1			T221	11		T170	18		T211	14
auto[0]	values[1]	values[0]	376	1			T42	15		T97	15		T223	15
auto[0]	values[1]	values[1]	265	1			T42	19		T15	24		T18	9
auto[0]	values[1]	values[2]	281	1			T8	8		T36	3		T15	28
auto[0]	values[1]	values[3]	281	1			T13	11		T209	8		T247	2
auto[0]	values[1]	values[4]	391	1			T8	9		T11	10		T223	15
auto[0]	values[1]	values[5]	229	1			T248	2		T61	15		T249	4
auto[0]	values[1]	values[6]	384	1			T3	11		T5	12		T8	15
auto[0]	values[1]	values[7]	196	1			T8	11		T13	26		T250	8
auto[0]	values[2]	values[0]	237	1			T13	14		T42	10		T209	9
auto[0]	values[2]	values[1]	335	1			T13	14		T251	8		T20	15
auto[0]	values[2]	values[2]	277	1			T5	11		T42	8		T15	11
auto[0]	values[2]	values[3]	328	1			T3	10		T13	7		T178	13
auto[0]	values[2]	values[4]	158	1			T45	13		T61	7		T252	6
auto[0]	values[2]	values[5]	593	1			T36	12		T223	10		T231	12
auto[0]	values[2]	values[6]	372	1			T8	17		T36	9		T15	14
auto[0]	values[2]	values[7]	176	1			T178	6		T225	9		T233	14
auto[0]	values[3]	values[0]	261	1			T5	14		T139	13		T241	10
auto[0]	values[3]	values[1]	579	1			T3	40		T5	16		T15	12
auto[0]	values[3]	values[2]	358	1			T5	13		T36	14		T210	14
auto[0]	values[3]	values[3]	222	1			T3	10		T209	18		T221	15
auto[0]	values[3]	values[4]	292	1			T15	9		T97	9		T233	19
auto[0]	values[3]	values[5]	495	1			T13	9		T42	17		T15	12
auto[0]	values[3]	values[6]	361	1			T35	48		T222	24		T170	17
auto[0]	values[3]	values[7]	427	1			T5	10		T42	12		T97	17
auto[0]	values[4]	values[0]	215	1			T8	10		T11	17		T220	41
auto[0]	values[4]	values[1]	277	1			T161	10		T139	10		T253	35
auto[0]	values[4]	values[2]	368	1			T5	9		T18	11		T170	14
auto[0]	values[4]	values[3]	170	1			T13	10		T178	15		T97	12
auto[0]	values[4]	values[4]	196	1			T97	16		T61	13		T18	11
auto[0]	values[4]	values[5]	307	1			T13	15		T120	14		T178	24
auto[0]	values[4]	values[6]	305	1			T225	11		T204	8		T211	9
auto[0]	values[4]	values[7]	179	1			T174	11		T209	10		T254	14
auto[0]	values[5]	values[0]	321	1			T15	13		T210	24		T232	30
auto[0]	values[5]	values[1]	269	1			T13	14		T15	9		T204	20
auto[0]	values[5]	values[2]	201	1			T11	10		T178	11		T225	6
auto[0]	values[5]	values[3]	214	1			T13	6		T89	2		T223	16
auto[0]	values[5]	values[4]	200	1			T42	14		T135	15		T144	15
auto[0]	values[5]	values[5]	345	1			T229	22		T223	15		T60	2
auto[0]	values[5]	values[6]	212	1			T209	19		T45	34		T18	20
auto[0]	values[5]	values[7]	359	1			T42	10		T211	12		T208	9
auto[0]	values[6]	values[0]	327	1			T15	21		T209	12		T97	19
auto[0]	values[6]	values[1]	265	1			T13	7		T95	8		T36	8
auto[0]	values[6]	values[2]	241	1			T209	14		T97	6		T227	46
auto[0]	values[6]	values[3]	168	1			T255	17		T256	18		T257	16
auto[0]	values[6]	values[4]	330	1			T255	20		T257	5		T145	13
auto[0]	values[6]	values[5]	119	1			T212	8		T204	14		T216	13
auto[0]	values[6]	values[6]	256	1			T36	15		T42	13		T223	23
auto[0]	values[6]	values[7]	194	1			T258	4		T259	11		T255	56
auto[0]	values[7]	values[0]	270	1			T3	9		T174	9		T178	11
auto[0]	values[7]	values[1]	186	1			T20	14		T204	10		T139	7
auto[0]	values[7]	values[2]	299	1			T260	12		T243	22		T221	8
auto[0]	values[7]	values[3]	287	1			T15	9		T204	3		T234	14
auto[0]	values[7]	values[4]	338	1			T5	16		T223	25		T225	57
auto[0]	values[7]	values[5]	507	1			T3	10		T12	20		T42	9
auto[0]	values[7]	values[6]	245	1			T206	10		T204	12		T241	14
auto[0]	values[7]	values[7]	300	1			T8	11		T139	9		T241	10
auto[1]	values[0]	values[0]	177	1			T209	8		T220	9		T216	20
auto[1]	values[0]	values[1]	128	1			T13	10		T90	4		T97	8
auto[1]	values[0]	values[2]	322	1			T3	5		T45	3		T220	15
auto[1]	values[0]	values[3]	229	1			T5	7		T223	7		T221	5
auto[1]	values[0]	values[4]	157	1			T223	4		T61	9		T261	16
auto[1]	values[0]	values[5]	216	1			T8	38		T45	6		T221	8
auto[1]	values[0]	values[6]	147	1			T210	58		T208	12		T218	5
auto[1]	values[0]	values[7]	243	1			T221	9		T170	6		T211	6
auto[1]	values[1]	values[0]	237	1			T42	7		T97	5		T223	40
auto[1]	values[1]	values[1]	145	1			T42	7		T15	20		T18	11
auto[1]	values[1]	values[2]	183	1			T8	12		T36	17		T15	4
auto[1]	values[1]	values[3]	203	1			T13	9		T209	16		T241	8
auto[1]	values[1]	values[4]	197	1			T8	41		T11	10		T223	5
auto[1]	values[1]	values[5]	107	1			T61	5		T170	12		T262	6
auto[1]	values[1]	values[6]	484	1			T3	70		T5	8		T8	5
auto[1]	values[1]	values[7]	130	1			T8	9		T13	14		T135	16
auto[1]	values[2]	values[0]	166	1			T13	6		T42	11		T209	34
auto[1]	values[2]	values[1]	257	1			T13	6		T20	10		T259	58
auto[1]	values[2]	values[2]	191	1			T5	18		T42	17		T15	11
auto[1]	values[2]	values[3]	184	1			T3	68		T13	13		T178	7
auto[1]	values[2]	values[4]	243	1			T214	28		T45	12		T61	57
auto[1]	values[2]	values[5]	340	1			T162	14		T36	8		T223	10
auto[1]	values[2]	values[6]	186	1			T8	9		T36	11		T15	8
auto[1]	values[2]	values[7]	186	1			T178	24		T225	39		T233	35
auto[1]	values[3]	values[0]	166	1			T5	6		T139	7		T241	10
auto[1]	values[3]	values[1]	409	1			T3	9		T5	9		T15	12
auto[1]	values[3]	values[2]	224	1			T5	7		T36	43		T210	6
auto[1]	values[3]	values[3]	169	1			T3	53		T209	7		T221	5
auto[1]	values[3]	values[4]	157	1			T15	11		T97	11		T233	12
auto[1]	values[3]	values[5]	184	1			T13	11		T42	11		T15	8
auto[1]	values[3]	values[6]	289	1			T170	4		T226	8		T259	6
auto[1]	values[3]	values[7]	230	1			T4	14		T5	10		T42	10
auto[1]	values[4]	values[0]	81	1			T8	10		T11	7		T220	8
auto[1]	values[4]	values[1]	132	1			T139	10		T253	4		T263	4
auto[1]	values[4]	values[2]	249	1			T5	11		T18	9		T170	9
auto[1]	values[4]	values[3]	186	1			T13	10		T178	7		T97	8
auto[1]	values[4]	values[4]	158	1			T97	4		T61	7		T18	16
auto[1]	values[4]	values[5]	109	1			T13	5		T178	4		T97	10
auto[1]	values[4]	values[6]	252	1			T225	9		T204	12		T211	16
auto[1]	values[4]	values[7]	204	1			T174	9		T209	10		T259	39
auto[1]	values[5]	values[0]	179	1			T15	7		T210	10		T232	9
auto[1]	values[5]	values[1]	304	1			T13	6		T15	11		T204	22
auto[1]	values[5]	values[2]	231	1			T11	17		T178	9		T225	40
auto[1]	values[5]	values[3]	174	1			T13	14		T41	14		T223	21
auto[1]	values[5]	values[4]	119	1			T42	8		T135	6		T144	9
auto[1]	values[5]	values[5]	191	1			T223	5		T225	7		T18	9
auto[1]	values[5]	values[6]	181	1			T209	8		T45	3		T18	24
auto[1]	values[5]	values[7]	376	1			T14	16		T42	10		T211	65
auto[1]	values[6]	values[0]	199	1			T40	24		T15	7		T209	15
auto[1]	values[6]	values[1]	218	1			T13	13		T36	24		T42	8
auto[1]	values[6]	values[2]	278	1			T209	6		T97	14		T227	6
auto[1]	values[6]	values[3]	65	1			T255	6		T257	4		T253	5
auto[1]	values[6]	values[4]	176	1			T264	6		T255	39		T257	15
auto[1]	values[6]	values[5]	116	1			T204	6		T216	67		T202	8
auto[1]	values[6]	values[6]	148	1			T36	5		T42	8		T223	19
auto[1]	values[6]	values[7]	224	1			T259	9		T255	33		T265	10
auto[1]	values[7]	values[0]	229	1			T3	11		T174	12		T178	9
auto[1]	values[7]	values[1]	224	1			T20	26		T204	11		T139	20
auto[1]	values[7]	values[2]	88	1			T221	12		T233	6		T266	9
auto[1]	values[7]	values[3]	256	1			T15	27		T204	22		T234	6
auto[1]	values[7]	values[4]	297	1			T5	4		T223	1		T225	11
auto[1]	values[7]	values[5]	344	1			T3	81		T42	17		T209	30
auto[1]	values[7]	values[6]	234	1			T206	43		T204	10		T241	6
auto[1]	values[7]	values[7]	180	1			T8	36		T139	11		T241	10