Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15794

1

T3

152

T4

7

T5

77

auto[1]

45633

1

T1

83

T2

287

T3

318

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1415	1			T1	2		T2	6		T3	4
auto[4:7]	24696	1			T1	20		T2	73		T3	352
auto[8:11]	1372	1			T1	1		T2	4		T3	4
auto[12:15]	302	1			T1	1		T2	4		T3	2
auto[16:19]	357	1			T1	1		T2	7		T3	7
auto[20:23]	1886	1			T1	5		T2	9		T3	4
auto[24:27]	323	1			T2	1		T3	3		T5	2
auto[28:31]	352	1			T1	2		T2	2		T3	1
auto[32:35]	386	1			T2	2		T3	11		T11	2
auto[36:39]	369	1			T2	3		T3	1		T8	1
auto[40:43]	322	1			T2	4		T3	1		T13	4
auto[44:47]	338	1			T2	3		T3	1		T5	1
auto[48:51]	342	1			T2	1		T3	2		T8	2
auto[52:55]	1853	1			T1	6		T2	11		T3	3
auto[56:59]	1421	1			T2	3		T3	4		T5	9
auto[60:63]	334	1			T1	2		T2	5		T13	1
auto[64:67]	359	1			T2	3		T96	1		T181	4
auto[68:71]	331	1			T1	2		T2	1		T3	1
auto[72:75]	349	1			T2	5		T3	3		T4	2
auto[76:79]	339	1			T1	1		T2	3		T5	4
auto[80:83]	351	1			T2	2		T13	1		T34	1
auto[84:87]	311	1			T5	1		T8	4		T14	4
auto[88:91]	1857	1			T1	3		T2	9		T3	5
auto[92:95]	351	1			T1	1		T5	3		T8	1
auto[96:99]	367	1			T1	1		T2	1		T3	3
auto[100:103]	421	1			T2	2		T3	1		T5	1
auto[104:107]	1370	1			T1	3		T2	4		T3	8
auto[108:111]	286	1			T2	2		T8	2		T25	5
auto[112:115]	348	1			T1	2		T2	4		T4	6
auto[116:119]	346	1			T1	2		T2	1		T3	1
auto[120:123]	354	1			T1	2		T2	3		T5	1
auto[124:127]	310	1			T1	1		T2	2		T3	2
auto[128:131]	347	1			T1	2		T2	2		T5	2
auto[132:135]	338	1			T2	2		T5	1		T8	5
auto[136:139]	340	1			T3	1		T8	2		T11	3
auto[140:143]	309	1			T2	6		T8	1		T13	1
auto[144:147]	324	1			T2	2		T3	4		T8	1
auto[148:151]	331	1			T1	2		T3	1		T5	7
auto[152:155]	297	1			T5	3		T13	1		T34	3
auto[156:159]	1880	1			T1	3		T2	16		T3	8
auto[160:163]	326	1			T2	1		T3	1		T5	1
auto[164:167]	274	1			T1	1		T2	1		T3	1
auto[168:171]	349	1			T2	4		T5	1		T11	1
auto[172:175]	323	1			T2	2		T8	2		T13	3
auto[176:179]	324	1			T2	4		T3	3		T5	5
auto[180:183]	1818	1			T1	2		T2	10		T3	5
auto[184:187]	1337	1			T1	1		T2	3		T3	3
auto[188:191]	364	1			T2	7		T8	2		T11	1
auto[192:195]	328	1			T2	3		T8	4		T11	1
auto[196:199]	298	1			T1	2		T2	1		T3	1
auto[200:203]	379	1			T2	4		T3	3		T5	1
auto[204:207]	341	1			T2	6		T3	1		T5	2
auto[208:211]	341	1			T1	1		T2	4		T3	2
auto[212:215]	281	1			T2	1		T11	1		T13	7
auto[216:219]	368	1			T2	2		T5	1		T8	1
auto[220:223]	367	1			T1	1		T2	1		T5	3
auto[224:227]	327	1			T2	1		T3	3		T5	1
auto[228:231]	358	1			T1	2		T2	5		T5	6
auto[232:235]	2954	1			T1	5		T2	16		T3	5
auto[236:239]	317	1			T2	1		T11	2		T13	3
auto[240:243]	330	1			T1	1		T2	1		T3	1
auto[244:247]	345	1			T2	1		T5	3		T13	3
auto[248:251]	358	1			T3	2		T13	1		T34	1
auto[252:255]	336	1			T1	2		T3	1		T8	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	484	1			T3	2		T5	4		T8	1
auto[0:3]	auto[1]	931	1			T1	2		T2	6		T3	2
auto[4:7]	auto[0]	5868	1			T3	96		T4	1		T5	9
auto[4:7]	auto[1]	18828	1			T1	20		T2	73		T3	256
auto[8:11]	auto[0]	468	1			T5	3		T8	3		T13	6
auto[8:11]	auto[1]	904	1			T1	1		T2	4		T3	4
auto[12:15]	auto[0]	78	1			T5	2		T15	1		T174	2
auto[12:15]	auto[1]	224	1			T1	1		T2	4		T3	2
auto[16:19]	auto[0]	87	1			T3	5		T222	1		T36	2
auto[16:19]	auto[1]	270	1			T1	1		T2	7		T3	2
auto[20:23]	auto[0]	459	1			T3	2		T4	1		T5	2
auto[20:23]	auto[1]	1427	1			T1	5		T2	9		T3	2
auto[24:27]	auto[0]	86	1			T5	2		T13	2		T260	1
auto[24:27]	auto[1]	237	1			T2	1		T3	3		T13	3
auto[28:31]	auto[0]	89	1			T3	1		T13	4		T36	2
auto[28:31]	auto[1]	263	1			T1	2		T2	2		T5	1
auto[32:35]	auto[0]	105	1			T3	5		T11	1		T13	1
auto[32:35]	auto[1]	281	1			T2	2		T3	6		T11	1
auto[36:39]	auto[0]	83	1			T3	1		T13	3		T36	1
auto[36:39]	auto[1]	286	1			T2	3		T8	1		T13	1
auto[40:43]	auto[0]	78	1			T14	1		T36	1		T178	2
auto[40:43]	auto[1]	244	1			T2	4		T3	1		T13	4
auto[44:47]	auto[0]	84	1			T3	1		T5	1		T8	1
auto[44:47]	auto[1]	254	1			T2	3		T8	4		T11	2
auto[48:51]	auto[0]	75	1			T3	2		T13	2		T15	2
auto[48:51]	auto[1]	267	1			T2	1		T8	2		T13	3
auto[52:55]	auto[0]	471	1			T3	1		T5	2		T8	3
auto[52:55]	auto[1]	1382	1			T1	6		T2	11		T3	2
auto[56:59]	auto[0]	516	1			T5	3		T8	4		T11	5
auto[56:59]	auto[1]	905	1			T2	3		T3	4		T5	6
auto[60:63]	auto[0]	74	1			T42	1		T15	3		T225	2
auto[60:63]	auto[1]	260	1			T1	2		T2	5		T13	1
auto[64:67]	auto[0]	90	1			T15	3		T174	2		T178	1
auto[64:67]	auto[1]	269	1			T2	3		T96	1		T181	4
auto[68:71]	auto[0]	75	1			T3	1		T8	2		T13	4
auto[68:71]	auto[1]	256	1			T1	2		T2	1		T162	1
auto[72:75]	auto[0]	96	1			T4	1		T11	1		T42	1
auto[72:75]	auto[1]	253	1			T2	5		T3	3		T4	1
auto[76:79]	auto[0]	81	1			T5	3		T8	1		T13	3
auto[76:79]	auto[1]	258	1			T1	1		T2	3		T5	1
auto[80:83]	auto[0]	88	1			T13	1		T40	3		T42	3
auto[80:83]	auto[1]	263	1			T2	2		T34	1		T25	2
auto[84:87]	auto[0]	63	1			T8	2		T14	2		T260	1
auto[84:87]	auto[1]	248	1			T5	1		T8	2		T14	2
auto[88:91]	auto[0]	447	1			T3	2		T5	2		T8	7
auto[88:91]	auto[1]	1410	1			T1	3		T2	9		T3	3
auto[92:95]	auto[0]	77	1			T5	1		T13	3		T222	2
auto[92:95]	auto[1]	274	1			T1	1		T5	2		T8	1
auto[96:99]	auto[0]	102	1			T8	2		T13	1		T36	3
auto[96:99]	auto[1]	265	1			T1	1		T2	1		T3	3
auto[100:103]	auto[0]	90	1			T3	1		T5	1		T8	2
auto[100:103]	auto[1]	331	1			T2	2		T13	1		T34	1
auto[104:107]	auto[0]	490	1			T3	8		T4	1		T5	12
auto[104:107]	auto[1]	880	1			T1	3		T2	4		T4	1
auto[108:111]	auto[0]	65	1			T222	3		T43	4		T15	3
auto[108:111]	auto[1]	221	1			T2	2		T8	2		T25	5
auto[112:115]	auto[0]	81	1			T4	3		T13	2		T36	1
auto[112:115]	auto[1]	267	1			T1	2		T2	4		T4	3
auto[116:119]	auto[0]	73	1			T8	1		T11	1		T13	1
auto[116:119]	auto[1]	273	1			T1	2		T2	1		T3	1
auto[120:123]	auto[0]	92	1			T8	1		T36	1		T15	2
auto[120:123]	auto[1]	262	1			T1	2		T2	3		T5	1
auto[124:127]	auto[0]	73	1			T3	1		T8	2		T13	1
auto[124:127]	auto[1]	237	1			T1	1		T2	2		T3	1
auto[128:131]	auto[0]	80	1			T8	1		T13	2		T42	2
auto[128:131]	auto[1]	267	1			T1	2		T2	2		T5	2
auto[132:135]	auto[0]	53	1			T11	2		T13	1		T178	1
auto[132:135]	auto[1]	285	1			T2	2		T5	1		T8	5
auto[136:139]	auto[0]	63	1			T8	2		T11	3		T13	1
auto[136:139]	auto[1]	277	1			T3	1		T13	1		T34	1
auto[140:143]	auto[0]	69	1			T8	1		T13	1		T42	1
auto[140:143]	auto[1]	240	1			T2	6		T25	2		T96	7
auto[144:147]	auto[0]	79	1			T120	1		T42	2		T178	1
auto[144:147]	auto[1]	245	1			T2	2		T3	4		T8	1
auto[148:151]	auto[0]	90	1			T3	1		T5	2		T8	1
auto[148:151]	auto[1]	241	1			T1	2		T5	5		T8	3
auto[152:155]	auto[0]	86	1			T5	3		T13	1		T15	1
auto[152:155]	auto[1]	211	1			T34	3		T25	2		T96	3
auto[156:159]	auto[0]	446	1			T3	5		T8	3		T11	1
auto[156:159]	auto[1]	1434	1			T1	3		T2	16		T3	3
auto[160:163]	auto[0]	85	1			T8	1		T13	1		T35	2
auto[160:163]	auto[1]	241	1			T2	1		T3	1		T5	1
auto[164:167]	auto[0]	71	1			T3	1		T13	2		T35	1
auto[164:167]	auto[1]	203	1			T1	1		T2	1		T5	2
auto[168:171]	auto[0]	103	1			T36	1		T15	1		T209	2
auto[168:171]	auto[1]	246	1			T2	4		T5	1		T11	1
auto[172:175]	auto[0]	93	1			T36	1		T178	4		T209	2
auto[172:175]	auto[1]	230	1			T2	2		T8	2		T13	3
auto[176:179]	auto[0]	70	1			T3	2		T5	2		T13	1
auto[176:179]	auto[1]	254	1			T2	4		T3	1		T5	3
auto[180:183]	auto[0]	493	1			T3	4		T5	4		T8	1
auto[180:183]	auto[1]	1325	1			T1	2		T2	10		T3	1
auto[184:187]	auto[0]	456	1			T3	2		T5	2		T8	3
auto[184:187]	auto[1]	881	1			T1	1		T2	3		T3	1
auto[188:191]	auto[0]	86	1			T13	3		T15	2		T178	1
auto[188:191]	auto[1]	278	1			T2	7		T8	2		T11	1
auto[192:195]	auto[0]	90	1			T8	1		T13	2		T42	2
auto[192:195]	auto[1]	238	1			T2	3		T8	3		T11	1
auto[196:199]	auto[0]	77	1			T3	1		T8	1		T13	1
auto[196:199]	auto[1]	221	1			T1	2		T2	1		T5	3
auto[200:203]	auto[0]	88	1			T3	2		T13	1		T36	3
auto[200:203]	auto[1]	291	1			T2	4		T3	1		T5	1
auto[204:207]	auto[0]	79	1			T3	1		T11	1		T13	1
auto[204:207]	auto[1]	262	1			T2	6		T5	2		T25	1
auto[208:211]	auto[0]	90	1			T5	1		T13	1		T36	2
auto[208:211]	auto[1]	251	1			T1	1		T2	4		T3	2
auto[212:215]	auto[0]	70	1			T11	1		T13	5		T45	2
auto[212:215]	auto[1]	211	1			T2	1		T13	2		T25	3
auto[216:219]	auto[0]	89	1			T5	1		T8	1		T13	1
auto[216:219]	auto[1]	279	1			T2	2		T11	2		T25	4
auto[220:223]	auto[0]	107	1			T5	1		T11	1		T90	1
auto[220:223]	auto[1]	260	1			T1	1		T2	1		T5	2
auto[224:227]	auto[0]	85	1			T3	2		T5	1		T8	3
auto[224:227]	auto[1]	242	1			T2	1		T3	1		T162	1
auto[228:231]	auto[0]	79	1			T5	2		T8	1		T11	1
auto[228:231]	auto[1]	279	1			T1	2		T2	5		T5	4
auto[232:235]	auto[0]	870	1			T3	2		T5	9		T8	1
auto[232:235]	auto[1]	2084	1			T1	5		T2	16		T3	3
auto[236:239]	auto[0]	93	1			T11	2		T13	3		T260	1
auto[236:239]	auto[1]	224	1			T2	1		T25	5		T96	1
auto[240:243]	auto[0]	92	1			T13	5		T120	1		T36	1
auto[240:243]	auto[1]	238	1			T1	1		T2	1		T3	1
auto[244:247]	auto[0]	95	1			T5	2		T13	2		T40	1
auto[244:247]	auto[1]	250	1			T2	1		T5	1		T13	1
auto[248:251]	auto[0]	78	1			T15	1		T178	1		T209	1
auto[248:251]	auto[1]	280	1			T3	2		T13	1		T34	1
auto[252:255]	auto[0]	101	1			T8	3		T36	6		T42	3
auto[252:255]	auto[1]	235	1			T1	2		T3	1		T25	5