Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	380	1			T3	2		T5	3		T8	8
auto[ReadAddrCrossIntoMailbox]	322	1			T3	2		T5	6		T8	6
auto[ReadAddrCrossOutOfMailbox]	320	1			T5	8		T8	4		T13	5
auto[ReadAddrCrossAllMailbox]	203	1			T3	1		T5	1		T8	1
auto[ReadAddrOutsideMailbox]	3745	1			T3	17		T4	2		T5	27

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2480

1

T3

11

T4

1

T5

22

auto[1]

2490

1

T3

11

T4

1

T5

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	812	1			T3	4		T5	6		T8	2
read_ops[0x0b]	823	1			T3	2		T5	7		T8	4
read_ops[0x3b]	880	1			T3	4		T5	9		T8	6
read_ops[0x6b]	829	1			T3	7		T4	2		T5	10
read_ops[0xbb]	787	1			T3	2		T5	4		T8	7
read_ops[0xeb]	839	1			T3	3		T5	9		T8	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T3	1		T8	1		T13	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T42	1		T15	1		T175	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T13	1		T97	2		T223	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T8	1		T15	1		T221	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T42	1		T220	1		T144	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T5	1		T15	1		T223	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T13	1		T178	1		T204	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T13	1		T178	1		T223	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	308	1			T3	1		T5	1		T35	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T3	2		T5	4		T11	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T5	1		T8	1		T13	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T45	1		T61	1		T225	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T8	1		T13	1		T15	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T8	1		T97	2		T45	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T5	1		T36	1		T178	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T178	1		T204	1		T241	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T5	1		T13	1		T232	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T210	1		T18	1		T204	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T8	1		T13	2		T162	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T3	2		T5	4		T11	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T36	1		T42	2		T15	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T8	1		T36	1		T223	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T5	1		T11	1		T178	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T3	2		T13	1		T223	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T5	1		T8	1		T13	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T5	1		T13	1		T15	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T209	1		T251	1		T97	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T15	1		T210	1		T209	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	336	1			T5	1		T8	3		T11	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T3	2		T5	5		T8	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T3	1		T5	2		T13	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T8	2		T89	1		T36	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T15	1		T223	1		T206	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T13	1		T174	1		T170	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T5	3		T174	2		T18	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T42	1		T45	2		T206	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T3	1		T210	1		T221	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T8	1		T36	1		T225	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T3	5		T4	1		T5	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T4	1		T5	1		T8	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T223	1		T18	1		T20	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T8	2		T13	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T8	1		T251	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T5	1		T8	2		T13	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T5	1		T8	1		T178	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T13	1		T221	1		T144	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T251	1		T97	1		T18	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T13	1		T251	1		T97	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T3	1		T5	1		T8	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T3	1		T5	1		T13	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T36	1		T42	2		T178	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T8	1		T174	1		T97	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T5	1		T13	1		T174	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T5	3		T15	1		T174	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T15	1		T97	1		T221	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T8	2		T13	2		T210	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T13	2		T18	1		T204	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T178	1		T18	1		T170	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	328	1			T3	1		T5	3		T13	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T3	2		T5	2		T8	2