Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4678	1			T3	63		T5	20		T8	117
values[1]	4074	1			T8	48		T11	24		T13	20
values[2]	4163	1			T3	88		T8	26		T13	20
values[3]	3992	1			T3	49		T11	20		T13	20
values[4]	3581	1			T3	101		T5	40		T8	20
values[5]	3470	1			T8	40		T120	14		T260	12
values[6]	3672	1			T3	78		T5	65		T12	20
values[7]	4220	1			T3	91		T4	14		T5	69

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3675	1			T13	40		T260	12		T258	4
values[1]	3758	1			T3	189		T13	40		T42	21
values[2]	4555	1			T5	49		T8	26		T12	20
values[3]	4127	1			T3	91		T4	14		T5	45
values[4]	3786	1			T13	40		T40	24		T222	24
values[5]	3346	1			T3	112		T5	40		T8	20
values[6]	4225	1			T5	40		T8	118		T11	24
values[7]	4378	1			T3	78		T5	20		T8	67

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31028

1

T3

463

T4

14

T5

188

auto[1]

822

1

T3

7

T5

6

T8

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	473	1			T13	20		T42	46		T261	14
auto[0]	values[0]	values[1]	532	1			T61	18		T233	45		T170	22
auto[0]	values[0]	values[2]	907	1			T178	20		T209	60		T92	20
auto[0]	values[0]	values[3]	446	1			T174	38		T61	60		T204	20
auto[0]	values[0]	values[4]	368	1			T15	32		T221	20		T267	10
auto[0]	values[0]	values[5]	597	1			T3	63		T162	14		T175	10
auto[0]	values[0]	values[6]	714	1			T5	20		T8	48		T223	21
auto[0]	values[0]	values[7]	529	1			T8	67		T35	48		T42	22
auto[0]	values[1]	values[0]	439	1			T61	20		T200	23		T208	20
auto[0]	values[1]	values[1]	518	1			T15	44		T221	16		T204	25
auto[0]	values[1]	values[2]	325	1			T41	10		T45	20		T20	24
auto[0]	values[1]	values[3]	406	1			T14	14		T225	78		T246	12
auto[0]	values[1]	values[4]	411	1			T15	19		T230	6		T216	125
auto[0]	values[1]	values[5]	608	1			T97	40		T45	23		T83	12
auto[0]	values[1]	values[6]	543	1			T8	46		T11	23		T15	48
auto[0]	values[1]	values[7]	733	1			T13	18		T18	45		T240	16
auto[0]	values[2]	values[0]	495	1			T36	31		T223	33		T268	2
auto[0]	values[2]	values[1]	667	1			T3	87		T233	29		T211	46
auto[0]	values[2]	values[2]	450	1			T8	24		T210	137		T18	28
auto[0]	values[2]	values[3]	585	1			T36	16		T248	2		T209	43
auto[0]	values[2]	values[4]	376	1			T13	19		T15	19		T174	19
auto[0]	values[2]	values[5]	474	1			T15	17		T18	27		T269	22
auto[0]	values[2]	values[6]	702	1			T91	24		T36	56		T209	19
auto[0]	values[2]	values[7]	318	1			T15	36		T206	20		T225	20
auto[0]	values[3]	values[0]	576	1			T252	6		T225	20		T270	12
auto[0]	values[3]	values[1]	450	1			T174	27		T209	20		T45	33
auto[0]	values[3]	values[2]	299	1			T178	28		T18	23		T20	20
auto[0]	values[3]	values[3]	470	1			T61	63		T200	23		T170	22
auto[0]	values[3]	values[4]	659	1			T222	24		T36	20		T15	20
auto[0]	values[3]	values[5]	339	1			T3	47		T11	20		T210	33
auto[0]	values[3]	values[6]	641	1			T13	20		T89	2		T42	20
auto[0]	values[3]	values[7]	456	1			T161	10		T178	27		T223	20
auto[0]	values[4]	values[0]	382	1			T209	19		T56	6		T211	20
auto[0]	values[4]	values[1]	498	1			T3	100		T251	8		T97	19
auto[0]	values[4]	values[2]	599	1			T42	20		T178	23		T223	20
auto[0]	values[4]	values[3]	658	1			T8	20		T13	19		T178	17
auto[0]	values[4]	values[4]	424	1			T40	20		T42	22		T97	37
auto[0]	values[4]	values[5]	265	1			T5	20		T15	20		T209	26
auto[0]	values[4]	values[6]	231	1			T271	6		T232	20		T220	20
auto[0]	values[4]	values[7]	418	1			T5	20		T11	25		T178	20
auto[0]	values[5]	values[0]	369	1			T260	12		T174	40		T272	4
auto[0]	values[5]	values[1]	276	1			T139	40		T262	20		T201	28
auto[0]	values[5]	values[2]	477	1			T97	20		T273	8		T139	20
auto[0]	values[5]	values[3]	523	1			T15	20		T209	21		T212	8
auto[0]	values[5]	values[4]	426	1			T36	20		T97	17		T223	20
auto[0]	values[5]	values[5]	242	1			T8	20		T221	40		T144	19
auto[0]	values[5]	values[6]	358	1			T8	20		T120	14		T223	20
auto[0]	values[5]	values[7]	726	1			T36	19		T42	22		T229	22
auto[0]	values[6]	values[0]	416	1			T13	19		T258	4		T204	40
auto[0]	values[6]	values[1]	345	1			T13	36		T42	20		T274	2
auto[0]	values[6]	values[2]	642	1			T5	20		T12	20		T13	40
auto[0]	values[6]	values[3]	461	1			T5	25		T42	27		T18	20
auto[0]	values[6]	values[4]	445	1			T15	24		T18	20		T233	18
auto[0]	values[6]	values[5]	241	1			T5	19		T42	21		T215	6
auto[0]	values[6]	values[6]	246	1			T275	14		T276	20		T46	28
auto[0]	values[6]	values[7]	759	1			T3	78		T221	18		T204	20
auto[0]	values[7]	values[0]	434	1			T210	20		T45	23		T221	20
auto[0]	values[7]	values[1]	366	1			T178	20		T209	21		T97	18
auto[0]	values[7]	values[2]	734	1			T5	28		T13	18		T90	4
auto[0]	values[7]	values[3]	458	1			T3	88		T4	14		T5	17
auto[0]	values[7]	values[4]	584	1			T13	20		T18	40		T204	20
auto[0]	values[7]	values[5]	490	1			T13	18		T178	21		T277	4
auto[0]	values[7]	values[6]	694	1			T5	19		T13	18		T95	8
auto[0]	values[7]	values[7]	335	1			T174	17		T223	22		T250	8
auto[1]	values[0]	values[0]	12	1			T42	2		T261	2		T241	1
auto[1]	values[0]	values[1]	9	1			T61	2		T170	1		T135	1
auto[1]	values[0]	values[2]	29	1			T209	2		T225	4		T278	2
auto[1]	values[0]	values[3]	13	1			T174	2		T61	2		T255	2
auto[1]	values[0]	values[4]	4	1			T241	1		T144	1		T218	1
auto[1]	values[0]	values[5]	16	1			T97	2		T170	2		T211	2
auto[1]	values[0]	values[6]	22	1			T8	2		T170	2		T208	2
auto[1]	values[0]	values[7]	7	1			T43	2		T241	1		T279	1
auto[1]	values[1]	values[0]	15	1			T227	3		T216	4		T266	5
auto[1]	values[1]	values[1]	9	1			T221	4		T145	1		T217	1
auto[1]	values[1]	values[2]	6	1			T41	4		T20	1		T94	1
auto[1]	values[1]	values[3]	11	1			T14	2		T225	1		T255	2
auto[1]	values[1]	values[4]	11	1			T15	1		T145	1		T280	1
auto[1]	values[1]	values[5]	9	1			T281	4		T282	1		T148	1
auto[1]	values[1]	values[6]	18	1			T8	2		T11	1		T15	2
auto[1]	values[1]	values[7]	12	1			T13	2		T18	3		T283	1
auto[1]	values[2]	values[0]	15	1			T36	1		T223	2		T241	1
auto[1]	values[2]	values[1]	16	1			T3	1		T233	2		T211	2
auto[1]	values[2]	values[2]	14	1			T8	2		T210	3		T48	1
auto[1]	values[2]	values[3]	20	1			T36	4		T135	1		T259	1
auto[1]	values[2]	values[4]	5	1			T13	1		T15	1		T174	2
auto[1]	values[2]	values[5]	15	1			T15	3		T255	2		T265	1
auto[1]	values[2]	values[6]	4	1			T36	1		T209	1		T219	1
auto[1]	values[2]	values[7]	7	1			T139	1		T257	1		T46	2
auto[1]	values[3]	values[0]	13	1			T170	1		T241	2		T284	2
auto[1]	values[3]	values[1]	15	1			T174	1		T45	4		T259	2
auto[1]	values[3]	values[2]	9	1			T18	1		T208	2		T145	1
auto[1]	values[3]	values[3]	9	1			T61	1		T200	2		T170	2
auto[1]	values[3]	values[4]	13	1			T206	1		T225	1		T139	2
auto[1]	values[3]	values[5]	13	1			T3	2		T210	1		T214	4
auto[1]	values[3]	values[6]	14	1			T42	2		T210	1		T253	3
auto[1]	values[3]	values[7]	16	1			T178	3		T221	1		T204	1
auto[1]	values[4]	values[0]	6	1			T209	1		T208	1		T285	2
auto[1]	values[4]	values[1]	12	1			T3	1		T97	1		T61	5
auto[1]	values[4]	values[2]	16	1			T45	1		T234	1		T286	5
auto[1]	values[4]	values[3]	24	1			T13	1		T178	3		T209	1
auto[1]	values[4]	values[4]	18	1			T40	4		T42	4		T97	3
auto[1]	values[4]	values[5]	6	1			T15	2		T209	1		T225	1
auto[1]	values[4]	values[6]	9	1			T287	4		T242	1		T213	1
auto[1]	values[4]	values[7]	15	1			T11	2		T178	3		T288	2
auto[1]	values[5]	values[0]	6	1			T174	2		T217	1		T289	1
auto[1]	values[5]	values[1]	8	1			T262	1		T290	2		T263	2
auto[1]	values[5]	values[2]	5	1			T237	1		T291	4		-	-
auto[1]	values[5]	values[3]	14	1			T209	1		T286	1		T292	3
auto[1]	values[5]	values[4]	8	1			T97	3		T61	3		T227	2
auto[1]	values[5]	values[5]	9	1			T144	2		T255	2		T265	1
auto[1]	values[5]	values[6]	4	1			T293	1		T294	3		-	-
auto[1]	values[5]	values[7]	19	1			T36	1		T42	2		T170	3
auto[1]	values[6]	values[0]	18	1			T13	1		T204	5		T227	2
auto[1]	values[6]	values[1]	16	1			T13	4		T42	1		T221	2
auto[1]	values[6]	values[2]	25	1			T295	2		T255	1		T257	4
auto[1]	values[6]	values[3]	12	1			T42	1		T18	1		T144	1
auto[1]	values[6]	values[4]	19	1			T233	2		T296	1		T289	1
auto[1]	values[6]	values[5]	6	1			T5	1		T94	1		T297	2
auto[1]	values[6]	values[6]	5	1			T46	1		T280	3		T298	1
auto[1]	values[6]	values[7]	16	1			T221	2		T216	1		T255	1
auto[1]	values[7]	values[0]	6	1			T45	1		T208	2		T48	2
auto[1]	values[7]	values[1]	21	1			T209	4		T97	2		T221	1
auto[1]	values[7]	values[2]	18	1			T5	1		T13	2		T18	1
auto[1]	values[7]	values[3]	17	1			T3	3		T5	3		T42	1
auto[1]	values[7]	values[4]	15	1			T255	2		T257	2		T299	2
auto[1]	values[7]	values[5]	16	1			T13	2		T178	1		T200	2
auto[1]	values[7]	values[6]	20	1			T5	1		T13	2		T209	2
auto[1]	values[7]	values[7]	12	1			T174	3		T220	1		T204	2