Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	815	1			T15	10		T16	4		T17	14
all_values[1]	815	1			T15	10		T16	4		T17	14
all_values[2]	815	1			T15	10		T16	4		T17	14
all_values[3]	815	1			T15	10		T16	4		T17	14
all_values[4]	815	1			T15	10		T16	4		T17	14
all_values[5]	815	1			T15	10		T16	4		T17	14
all_values[6]	815	1			T15	10		T16	4		T17	14
all_values[7]	815	1			T15	10		T16	4		T17	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3446

1

T15

51

T16

16

T17

56

auto[1]

3074

1

T15

29

T16

16

T17

56

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2693

1

T15

37

T16

20

T17

41

auto[1]

3827

1

T15

43

T16

12

T17

71

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3778

1

T15

48

T16

22

T17

61

auto[1]

2742

1

T15

32

T16

10

T17

51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	151	1			T15	3		T16	2		T17	1
all_values[0]	auto[0]	auto[0]	auto[1]	66	1			T15	2		T17	1		T21	1
all_values[0]	auto[0]	auto[1]	auto[0]	160	1			T15	1		T17	6		T19	4
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T18	3		T19	2		T30	1
all_values[0]	auto[1]	auto[0]	auto[1]	188	1			T15	4		T16	2		T17	4
all_values[0]	auto[1]	auto[1]	auto[1]	167	1			T17	2		T18	3		T19	3
all_values[1]	auto[0]	auto[0]	auto[0]	182	1			T15	3		T16	1		T18	2
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T15	1		T17	1		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	146	1			T15	3		T16	1		T17	3
all_values[1]	auto[0]	auto[1]	auto[1]	87	1			T16	1		T17	2		T18	1
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T15	2		T17	8		T18	1
all_values[1]	auto[1]	auto[1]	auto[1]	139	1			T15	1		T16	1		T18	3
all_values[2]	auto[0]	auto[0]	auto[0]	180	1			T15	6		T16	2		T17	2
all_values[2]	auto[0]	auto[0]	auto[1]	64	1			T18	1		T19	2		T22	1
all_values[2]	auto[0]	auto[1]	auto[0]	134	1			T15	3		T17	2		T18	1
all_values[2]	auto[0]	auto[1]	auto[1]	87	1			T17	4		T18	1		T22	1
all_values[2]	auto[1]	auto[0]	auto[1]	181	1			T15	1		T16	2		T17	1
all_values[2]	auto[1]	auto[1]	auto[1]	169	1			T17	5		T18	2		T19	1
all_values[3]	auto[0]	auto[0]	auto[0]	168	1			T15	1		T16	1		T17	2
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T17	4		T18	1		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T15	1		T17	3		T18	3
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T15	2		T16	1		T30	2
all_values[3]	auto[1]	auto[0]	auto[1]	210	1			T15	6		T17	4		T18	2
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T16	2		T17	1		T21	1
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T15	1		T16	1		T17	1
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T15	3		T17	1		T18	2
all_values[4]	auto[0]	auto[1]	auto[0]	146	1			T15	1		T16	2		T17	2
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T15	1		T17	2		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	176	1			T15	3		T16	1		T17	4
all_values[4]	auto[1]	auto[1]	auto[1]	158	1			T15	1		T17	4		T18	3
all_values[5]	auto[0]	auto[0]	auto[0]	226	1			T15	3		T17	5		T18	4
all_values[5]	auto[0]	auto[1]	auto[0]	229	1			T15	2		T16	2		T17	2
all_values[5]	auto[1]	auto[0]	auto[1]	183	1			T15	4		T16	2		T17	6
all_values[5]	auto[1]	auto[1]	auto[1]	177	1			T15	1		T17	1		T18	2
all_values[6]	auto[0]	auto[0]	auto[0]	192	1			T15	1		T16	1		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T18	1		T19	1		T22	1
all_values[6]	auto[0]	auto[1]	auto[0]	165	1			T15	2		T16	3		T17	4
all_values[6]	auto[0]	auto[1]	auto[1]	66	1			T15	1		T17	2		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	177	1			T17	1		T18	1		T19	4
all_values[6]	auto[1]	auto[1]	auto[1]	144	1			T15	6		T17	4		T18	1
all_values[7]	auto[0]	auto[0]	auto[0]	168	1			T15	5		T16	1		T17	2
all_values[7]	auto[0]	auto[0]	auto[1]	100	1			T17	1		T18	2		T19	1
all_values[7]	auto[0]	auto[1]	auto[0]	136	1			T15	1		T16	3		T17	3
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T15	1		T17	2		T18	3
all_values[7]	auto[1]	auto[0]	auto[1]	174	1			T15	2		T17	4		T18	2
all_values[7]	auto[1]	auto[1]	auto[1]	161	1			T15	1		T17	2		T18	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal