Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1692

1

T1

15

T2

8

T7

3

auto[1]

1574

1

T1

8

T2

6

T7

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1841

1

T1

23

T2

14

T7

8

auto[1]

1425

1

T7

4

T9

10

T24

26

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2575

1

T1

15

T2

13

T7

9

auto[1]

691

1

T1

8

T2

1

T7

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	662	1			T1	6		T2	2		T7	3
valid[1]	643	1			T1	3		T2	2		T7	4
valid[2]	649	1			T1	10		T2	2		T7	3
valid[3]	638	1			T1	1		T2	4		T7	1
valid[4]	674	1			T1	3		T2	4		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	129	1			T1	3		T25	1		T29	3
auto[0]	auto[0]	valid[0]	auto[1]	143	1			T7	1		T9	1		T24	4
auto[0]	auto[0]	valid[1]	auto[0]	116	1			T1	2		T2	2		T7	1
auto[0]	auto[0]	valid[1]	auto[1]	132	1			T9	3		T24	4		T25	1
auto[0]	auto[0]	valid[2]	auto[0]	130	1			T1	3		T2	2		T29	1
auto[0]	auto[0]	valid[2]	auto[1]	142	1			T7	1		T9	2		T24	2
auto[0]	auto[0]	valid[3]	auto[0]	97	1			T1	1		T2	2		T11	1
auto[0]	auto[0]	valid[3]	auto[1]	143	1			T24	4		T27	1		T28	2
auto[0]	auto[0]	valid[4]	auto[0]	137	1			T1	1		T2	2		T29	1
auto[0]	auto[0]	valid[4]	auto[1]	153	1			T9	1		T24	1		T25	1
auto[0]	auto[1]	valid[0]	auto[0]	107	1			T1	1		T2	1		T7	1
auto[0]	auto[1]	valid[0]	auto[1]	142	1			T9	1		T24	6		T27	1
auto[0]	auto[1]	valid[1]	auto[0]	124	1			T1	1		T7	2		T11	1
auto[0]	auto[1]	valid[1]	auto[1]	156	1			T7	1		T24	1		T27	1
auto[0]	auto[1]	valid[2]	auto[0]	95	1			T1	2		T11	1		T25	1
auto[0]	auto[1]	valid[2]	auto[1]	127	1			T24	2		T25	1		T27	6
auto[0]	auto[1]	valid[3]	auto[0]	116	1			T2	2		T7	1		T11	1
auto[0]	auto[1]	valid[3]	auto[1]	138	1			T9	2		T24	2		T25	2
auto[0]	auto[1]	valid[4]	auto[0]	99	1			T1	1		T2	2		T11	1
auto[0]	auto[1]	valid[4]	auto[1]	149	1			T7	1		T25	2		T27	2
auto[1]	auto[0]	valid[0]	auto[0]	70	1			T1	1		T11	1		T25	1
auto[1]	auto[0]	valid[1]	auto[0]	63	1			T25	2		T29	1		T43	2
auto[1]	auto[0]	valid[2]	auto[0]	84	1			T1	3		T25	1		T44	1
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T25	1		T42	1		T177	1
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T1	1		T25	2		T43	1
auto[1]	auto[1]	valid[0]	auto[0]	71	1			T1	1		T2	1		T7	1
auto[1]	auto[1]	valid[1]	auto[0]	52	1			T25	1		T29	1		T43	1
auto[1]	auto[1]	valid[2]	auto[0]	71	1			T1	2		T7	2		T11	2
auto[1]	auto[1]	valid[3]	auto[0]	68	1			T11	1		T29	1		T43	1
auto[1]	auto[1]	valid[4]	auto[0]	59	1			T25	1		T29	1		T42	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal