Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47432

1

T1

430

T2

459

T7

245

auto[1]

15100

1

T7

71

T9

10

T24

447

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45393

1

T1

288

T2

296

T7

195

auto[1]

17139

1

T1

142

T2

163

T7

121

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32237	1			T1	207		T2	236		T7	156
others[1]	5357	1			T1	37		T2	32		T7	28
others[2]	5240	1			T1	42		T2	35		T7	30
others[3]	6025	1			T1	38		T2	48		T7	35
interest[1]	3388	1			T1	29		T2	32		T7	13
interest[4]	21188	1			T1	132		T2	140		T7	98
interest[64]	10285	1			T1	77		T2	76		T7	54

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15514	1			T1	140		T2	156		T7	57
auto[0]	auto[0]	others[1]	2644	1			T1	22		T2	19		T7	12
auto[0]	auto[0]	others[2]	2586	1			T1	29		T2	24		T7	16
auto[0]	auto[0]	others[3]	2967	1			T1	29		T2	30		T7	12
auto[0]	auto[0]	interest[1]	1698	1			T1	20		T2	24		T7	3
auto[0]	auto[0]	interest[4]	10010	1			T1	88		T2	94		T7	33
auto[0]	auto[0]	interest[64]	4884	1			T1	48		T2	43		T7	24
auto[0]	auto[1]	others[0]	7853	1			T7	38		T9	10		T24	244
auto[0]	auto[1]	others[1]	1226	1			T7	4		T24	37		T25	5
auto[0]	auto[1]	others[2]	1281	1			T7	4		T24	35		T25	6
auto[0]	auto[1]	others[3]	1441	1			T7	10		T24	46		T25	11
auto[0]	auto[1]	interest[1]	787	1			T7	4		T24	20		T25	5
auto[0]	auto[1]	interest[4]	5264	1			T7	24		T9	10		T24	160
auto[0]	auto[1]	interest[64]	2512	1			T7	11		T24	65		T25	16
auto[1]	auto[0]	others[0]	8870	1			T1	67		T2	80		T7	61
auto[1]	auto[0]	others[1]	1487	1			T1	15		T2	13		T7	12
auto[1]	auto[0]	others[2]	1373	1			T1	13		T2	11		T7	10
auto[1]	auto[0]	others[3]	1617	1			T1	9		T2	18		T7	13
auto[1]	auto[0]	interest[1]	903	1			T1	9		T2	8		T7	6
auto[1]	auto[0]	interest[4]	5914	1			T1	44		T2	46		T7	41
auto[1]	auto[0]	interest[64]	2889	1			T1	29		T2	33		T7	19

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal