Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1038 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.67419136 Aug 09 07:50:38 PM PDT 24 Aug 09 07:50:39 PM PDT 24 90903443 ps
T1039 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1247360052 Aug 09 07:50:12 PM PDT 24 Aug 09 07:50:14 PM PDT 24 89710257 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2039250085 Aug 09 07:50:12 PM PDT 24 Aug 09 07:50:15 PM PDT 24 36791990 ps
T1041 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1260419105 Aug 09 07:50:14 PM PDT 24 Aug 09 07:50:14 PM PDT 24 10245835 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3152845719 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:12 PM PDT 24 16680347 ps
T105 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3024189122 Aug 09 07:50:22 PM PDT 24 Aug 09 07:50:26 PM PDT 24 140994927 ps
T1043 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2875569703 Aug 09 07:50:28 PM PDT 24 Aug 09 07:50:34 PM PDT 24 114336975 ps
T1044 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1752903615 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:37 PM PDT 24 154221613 ps
T193 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4060435125 Aug 09 07:50:26 PM PDT 24 Aug 09 07:50:34 PM PDT 24 298035728 ps
T166 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4138056641 Aug 09 07:50:09 PM PDT 24 Aug 09 07:50:11 PM PDT 24 59337598 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3490066608 Aug 09 07:50:16 PM PDT 24 Aug 09 07:50:16 PM PDT 24 12736482 ps
T127 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2956229907 Aug 09 07:50:25 PM PDT 24 Aug 09 07:50:28 PM PDT 24 1096156775 ps
T128 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1029916810 Aug 09 07:50:14 PM PDT 24 Aug 09 07:50:16 PM PDT 24 33540038 ps
T84 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3418436702 Aug 09 07:50:08 PM PDT 24 Aug 09 07:50:09 PM PDT 24 20801778 ps
T167 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1949545162 Aug 09 07:50:18 PM PDT 24 Aug 09 07:50:21 PM PDT 24 133546056 ps
T130 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2072255692 Aug 09 07:50:07 PM PDT 24 Aug 09 07:50:19 PM PDT 24 754921550 ps
T1046 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.670868762 Aug 09 07:50:31 PM PDT 24 Aug 09 07:50:33 PM PDT 24 50941098 ps
T1047 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3545103474 Aug 09 07:50:21 PM PDT 24 Aug 09 07:50:22 PM PDT 24 13097857 ps
T168 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3393740085 Aug 09 07:50:16 PM PDT 24 Aug 09 07:50:19 PM PDT 24 251363062 ps
T169 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3462990133 Aug 09 07:50:23 PM PDT 24 Aug 09 07:50:27 PM PDT 24 197841535 ps
T129 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2093750732 Aug 09 07:50:16 PM PDT 24 Aug 09 07:50:19 PM PDT 24 129224812 ps
T1048 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2150986581 Aug 09 07:50:23 PM PDT 24 Aug 09 07:50:25 PM PDT 24 144818753 ps
T111 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3838560353 Aug 09 07:50:22 PM PDT 24 Aug 09 07:50:36 PM PDT 24 2246875580 ps
T1049 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2410749130 Aug 09 07:50:16 PM PDT 24 Aug 09 07:50:17 PM PDT 24 29770992 ps
T85 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.449777903 Aug 09 07:50:09 PM PDT 24 Aug 09 07:50:11 PM PDT 24 47320581 ps
T131 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4268443275 Aug 09 07:50:25 PM PDT 24 Aug 09 07:50:28 PM PDT 24 39097219 ps
T109 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2217837238 Aug 09 07:50:16 PM PDT 24 Aug 09 07:50:20 PM PDT 24 149770677 ps
T1050 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.617317282 Aug 09 07:50:22 PM PDT 24 Aug 09 07:50:25 PM PDT 24 295418883 ps
T186 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1010323689 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:24 PM PDT 24 201539428 ps
T1051 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1397360861 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:34 PM PDT 24 192284043 ps
T1052 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2869416637 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:34 PM PDT 24 111192010 ps
T106 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2436941286 Aug 09 07:50:09 PM PDT 24 Aug 09 07:50:12 PM PDT 24 406732533 ps
T187 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4242995603 Aug 09 07:50:22 PM PDT 24 Aug 09 07:50:29 PM PDT 24 419515906 ps
T1053 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2811332190 Aug 09 07:50:35 PM PDT 24 Aug 09 07:50:36 PM PDT 24 44598296 ps
T1054 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2464013187 Aug 09 07:50:24 PM PDT 24 Aug 09 07:50:27 PM PDT 24 452520597 ps
T132 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1594786340 Aug 09 07:50:08 PM PDT 24 Aug 09 07:50:11 PM PDT 24 94860113 ps
T1055 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1445168872 Aug 09 07:50:35 PM PDT 24 Aug 09 07:50:36 PM PDT 24 84142341 ps
T110 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1242842189 Aug 09 07:50:28 PM PDT 24 Aug 09 07:50:34 PM PDT 24 952463293 ps
T133 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.236463632 Aug 09 07:50:12 PM PDT 24 Aug 09 07:50:27 PM PDT 24 624184564 ps
T1056 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2267138630 Aug 09 07:50:40 PM PDT 24 Aug 09 07:50:41 PM PDT 24 65083792 ps
T86 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.589617875 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:13 PM PDT 24 86308822 ps
T1057 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3262489890 Aug 09 07:50:30 PM PDT 24 Aug 09 07:50:34 PM PDT 24 167795653 ps
T107 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.887615495 Aug 09 07:50:09 PM PDT 24 Aug 09 07:50:11 PM PDT 24 168866999 ps
T87 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.819461541 Aug 09 07:50:17 PM PDT 24 Aug 09 07:50:18 PM PDT 24 174051362 ps
T115 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2677509847 Aug 09 07:50:26 PM PDT 24 Aug 09 07:50:28 PM PDT 24 47046357 ps
T108 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2244100438 Aug 09 07:50:25 PM PDT 24 Aug 09 07:50:30 PM PDT 24 169591092 ps
T1058 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2384688854 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:34 PM PDT 24 15323705 ps
T1059 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3842535844 Aug 09 07:50:12 PM PDT 24 Aug 09 07:50:13 PM PDT 24 30791290 ps
T191 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3492547647 Aug 09 07:50:15 PM PDT 24 Aug 09 07:50:22 PM PDT 24 106093689 ps
T114 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.689003003 Aug 09 07:50:14 PM PDT 24 Aug 09 07:50:18 PM PDT 24 116021496 ps
T1060 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2973976518 Aug 09 07:50:09 PM PDT 24 Aug 09 07:50:12 PM PDT 24 106699708 ps
T1061 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.873092760 Aug 09 07:50:35 PM PDT 24 Aug 09 07:50:35 PM PDT 24 17333209 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3056402125 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:13 PM PDT 24 97464410 ps
T1063 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3355497527 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:15 PM PDT 24 674741215 ps
T113 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2360471833 Aug 09 07:50:16 PM PDT 24 Aug 09 07:50:20 PM PDT 24 146765014 ps
T184 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.126057254 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:39 PM PDT 24 468324210 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2566986866 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:18 PM PDT 24 423790450 ps
T1065 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2061450763 Aug 09 07:50:26 PM PDT 24 Aug 09 07:50:29 PM PDT 24 40358897 ps
T1066 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.916149854 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:34 PM PDT 24 26612509 ps
T1067 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2944541081 Aug 09 07:50:24 PM PDT 24 Aug 09 07:50:26 PM PDT 24 218895227 ps
T194 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1679914901 Aug 09 07:50:24 PM PDT 24 Aug 09 07:50:30 PM PDT 24 102166764 ps
T116 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3266097026 Aug 09 07:50:30 PM PDT 24 Aug 09 07:50:35 PM PDT 24 197124339 ps
T1068 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3273420182 Aug 09 07:50:34 PM PDT 24 Aug 09 07:50:35 PM PDT 24 40377130 ps
T1069 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3412152850 Aug 09 07:50:26 PM PDT 24 Aug 09 07:50:28 PM PDT 24 285723004 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4265621773 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:13 PM PDT 24 82194460 ps
T1071 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2459208263 Aug 09 07:50:32 PM PDT 24 Aug 09 07:50:33 PM PDT 24 20946995 ps
T1072 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1346786583 Aug 09 07:50:31 PM PDT 24 Aug 09 07:50:31 PM PDT 24 58622049 ps
T1073 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3681092371 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:35 PM PDT 24 58149340 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2474957935 Aug 09 07:50:12 PM PDT 24 Aug 09 07:50:14 PM PDT 24 273294520 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2735329277 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:11 PM PDT 24 53939213 ps
T1076 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3549513188 Aug 09 07:50:24 PM PDT 24 Aug 09 07:50:27 PM PDT 24 312702684 ps
T1077 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4063721424 Aug 09 07:50:40 PM PDT 24 Aug 09 07:50:40 PM PDT 24 57442945 ps
T1078 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2441325558 Aug 09 07:50:05 PM PDT 24 Aug 09 07:50:06 PM PDT 24 23319154 ps
T1079 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1124223837 Aug 09 07:50:26 PM PDT 24 Aug 09 07:50:27 PM PDT 24 21078886 ps
T1080 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3028346285 Aug 09 07:50:15 PM PDT 24 Aug 09 07:50:19 PM PDT 24 239519955 ps
T188 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2993299668 Aug 09 07:50:12 PM PDT 24 Aug 09 07:50:27 PM PDT 24 5442606259 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1989188150 Aug 09 07:50:09 PM PDT 24 Aug 09 07:50:11 PM PDT 24 75301428 ps
T1082 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3968941467 Aug 09 07:50:24 PM PDT 24 Aug 09 07:50:25 PM PDT 24 50244422 ps
T1083 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2964766574 Aug 09 07:50:22 PM PDT 24 Aug 09 07:50:24 PM PDT 24 55599098 ps
T1084 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2851935614 Aug 09 07:50:27 PM PDT 24 Aug 09 07:50:28 PM PDT 24 53517486 ps
T1085 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.676891299 Aug 09 07:50:24 PM PDT 24 Aug 09 07:50:34 PM PDT 24 659945532 ps
T1086 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.233535653 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:13 PM PDT 24 61317514 ps
T1087 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.974316461 Aug 09 07:50:31 PM PDT 24 Aug 09 07:50:34 PM PDT 24 130093960 ps
T1088 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.532239118 Aug 09 07:50:16 PM PDT 24 Aug 09 07:50:23 PM PDT 24 345933537 ps
T1089 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3971651936 Aug 09 07:50:16 PM PDT 24 Aug 09 07:50:18 PM PDT 24 155213087 ps
T1090 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.567643216 Aug 09 07:50:27 PM PDT 24 Aug 09 07:50:29 PM PDT 24 68057661 ps
T1091 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3759411135 Aug 09 07:50:17 PM PDT 24 Aug 09 07:50:32 PM PDT 24 1962186142 ps
T1092 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1569637424 Aug 09 07:50:15 PM PDT 24 Aug 09 07:50:16 PM PDT 24 123945485 ps
T1093 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4207060377 Aug 09 07:50:26 PM PDT 24 Aug 09 07:50:27 PM PDT 24 32849355 ps
T1094 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1086001684 Aug 09 07:50:15 PM PDT 24 Aug 09 07:50:17 PM PDT 24 565425691 ps
T1095 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3074932949 Aug 09 07:50:17 PM PDT 24 Aug 09 07:50:20 PM PDT 24 40818947 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2276447818 Aug 09 07:50:10 PM PDT 24 Aug 09 07:50:10 PM PDT 24 11080724 ps
T189 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2898055179 Aug 09 07:50:15 PM PDT 24 Aug 09 07:50:23 PM PDT 24 1453052328 ps
T1097 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1862755601 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:37 PM PDT 24 128583827 ps
T1098 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3815959860 Aug 09 07:50:12 PM PDT 24 Aug 09 07:50:16 PM PDT 24 155625489 ps
T190 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3216771887 Aug 09 07:50:15 PM PDT 24 Aug 09 07:50:33 PM PDT 24 306352994 ps
T1099 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4074866740 Aug 09 07:50:22 PM PDT 24 Aug 09 07:50:25 PM PDT 24 101363878 ps
T1100 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1919276349 Aug 09 07:50:23 PM PDT 24 Aug 09 07:50:26 PM PDT 24 462712573 ps
T1101 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4058974971 Aug 09 07:50:26 PM PDT 24 Aug 09 07:50:28 PM PDT 24 107255806 ps
T1102 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.983539819 Aug 09 07:50:39 PM PDT 24 Aug 09 07:50:42 PM PDT 24 252731133 ps
T1103 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1266966598 Aug 09 07:50:12 PM PDT 24 Aug 09 07:50:13 PM PDT 24 27260434 ps
T1104 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3793568368 Aug 09 07:50:09 PM PDT 24 Aug 09 07:50:18 PM PDT 24 874453516 ps
T1105 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4080600565 Aug 09 07:50:35 PM PDT 24 Aug 09 07:50:35 PM PDT 24 41732082 ps
T1106 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.30091695 Aug 09 07:50:28 PM PDT 24 Aug 09 07:50:31 PM PDT 24 102550901 ps
T1107 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.257183843 Aug 09 07:50:31 PM PDT 24 Aug 09 07:50:35 PM PDT 24 52637847 ps
T1108 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3480561209 Aug 09 07:50:34 PM PDT 24 Aug 09 07:50:36 PM PDT 24 94072310 ps
T1109 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3781620927 Aug 09 07:50:24 PM PDT 24 Aug 09 07:50:48 PM PDT 24 363650375 ps
T1110 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.951026711 Aug 09 07:50:16 PM PDT 24 Aug 09 07:50:17 PM PDT 24 45203529 ps
T1111 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1014292696 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:34 PM PDT 24 19413767 ps
T1112 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1590446932 Aug 09 07:50:15 PM PDT 24 Aug 09 07:50:16 PM PDT 24 19503475 ps
T185 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3839910113 Aug 09 07:50:24 PM PDT 24 Aug 09 07:50:39 PM PDT 24 3275078184 ps
T1113 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1023109647 Aug 09 07:50:25 PM PDT 24 Aug 09 07:50:28 PM PDT 24 123932535 ps
T1114 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1482116916 Aug 09 07:50:09 PM PDT 24 Aug 09 07:50:11 PM PDT 24 63090087 ps
T1115 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4270061571 Aug 09 07:50:15 PM PDT 24 Aug 09 07:50:17 PM PDT 24 285320679 ps
T1116 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.190270917 Aug 09 07:50:31 PM PDT 24 Aug 09 07:50:32 PM PDT 24 40375645 ps
T1117 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4035484781 Aug 09 07:50:04 PM PDT 24 Aug 09 07:50:16 PM PDT 24 717129756 ps
T1118 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2490418352 Aug 09 07:50:28 PM PDT 24 Aug 09 07:50:29 PM PDT 24 12263938 ps
T1119 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4135870851 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:34 PM PDT 24 38930088 ps
T1120 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1056962942 Aug 09 07:50:33 PM PDT 24 Aug 09 07:50:34 PM PDT 24 20314792 ps
T1121 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4157958972 Aug 09 07:50:40 PM PDT 24 Aug 09 07:50:41 PM PDT 24 17235833 ps
T1122 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4074395488 Aug 09 07:50:32 PM PDT 24 Aug 09 07:50:33 PM PDT 24 23336886 ps
T1123 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.748784038 Aug 09 07:50:36 PM PDT 24 Aug 09 07:50:36 PM PDT 24 14645454 ps
T1124 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1993065779 Aug 09 07:50:25 PM PDT 24 Aug 09 07:50:29 PM PDT 24 208113281 ps
T1125 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.650768921 Aug 09 07:50:11 PM PDT 24 Aug 09 07:50:25 PM PDT 24 982344587 ps
T1126 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2335137140 Aug 09 07:50:10 PM PDT 24 Aug 09 07:50:10 PM PDT 24 16416527 ps
T1127 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1624162194 Aug 09 07:50:28 PM PDT 24 Aug 09 07:50:29 PM PDT 24 26406827 ps
T192 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1958994926 Aug 09 07:50:17 PM PDT 24 Aug 09 07:50:31 PM PDT 24 414393294 ps
T1128 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2215207499 Aug 09 07:50:27 PM PDT 24 Aug 09 07:50:29 PM PDT 24 269993602 ps
T1129 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.89410053 Aug 09 07:50:23 PM PDT 24 Aug 09 07:50:23 PM PDT 24 102964707 ps
T1130 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.32732091 Aug 09 07:50:35 PM PDT 24 Aug 09 07:50:36 PM PDT 24 23020643 ps

Test location /workspace/coverage/default/17.spi_device_stress_all.2011525321
Short name T2
Test name
Test status
Simulation time 46244259246 ps
CPU time 351.69 seconds
Started Aug 09 07:55:06 PM PDT 24
Finished Aug 09 08:00:58 PM PDT 24
Peak memory 267484 kb
Host smart-ff38b508-9d26-4202-a16a-9ce26c7eccb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011525321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2011525321
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.4115118646
Short name T13
Test name
Test status
Simulation time 292404568130 ps
CPU time 542.41 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 08:04:41 PM PDT 24
Peak memory 257776 kb
Host smart-75a8d1a8-2b08-4ee5-bea2-ebdc0318b789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115118646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.4115118646
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3038463012
Short name T15
Test name
Test status
Simulation time 76232222593 ps
CPU time 751.91 seconds
Started Aug 09 07:55:37 PM PDT 24
Finished Aug 09 08:08:09 PM PDT 24
Peak memory 273844 kb
Host smart-cf9c19e2-c31f-42b7-b10b-d1df36df7def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038463012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3038463012
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1209686241
Short name T99
Test name
Test status
Simulation time 998328043 ps
CPU time 7.6 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 215232 kb
Host smart-7e2448b7-36ce-4cc8-a5b5-d6983649770f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209686241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1209686241
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1045554082
Short name T42
Test name
Test status
Simulation time 92263431482 ps
CPU time 502.72 seconds
Started Aug 09 07:54:43 PM PDT 24
Finished Aug 09 08:03:05 PM PDT 24
Peak memory 269424 kb
Host smart-30079b78-8d12-44ac-ab86-1279c823653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045554082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1045554082
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1089266425
Short name T69
Test name
Test status
Simulation time 18682903 ps
CPU time 0.75 seconds
Started Aug 09 07:54:02 PM PDT 24
Finished Aug 09 07:54:03 PM PDT 24
Peak memory 216472 kb
Host smart-48bb8d0f-c3d0-4809-a1b9-3855b318fbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089266425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1089266425
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2865057509
Short name T170
Test name
Test status
Simulation time 45880814049 ps
CPU time 477.85 seconds
Started Aug 09 07:56:50 PM PDT 24
Finished Aug 09 08:04:48 PM PDT 24
Peak memory 268260 kb
Host smart-812fb2ee-8a55-4ca1-a32b-4137a8634871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865057509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2865057509
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1437414986
Short name T18
Test name
Test status
Simulation time 160705875377 ps
CPU time 200.35 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:58:09 PM PDT 24
Peak memory 256052 kb
Host smart-e2675d4b-0b31-4297-b0f8-c45f7e1e402e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437414986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1437414986
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2879996467
Short name T255
Test name
Test status
Simulation time 401162375735 ps
CPU time 838.49 seconds
Started Aug 09 07:55:07 PM PDT 24
Finished Aug 09 08:09:05 PM PDT 24
Peak memory 290596 kb
Host smart-f129fdd2-ddf4-46aa-b4e8-92b199010cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879996467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2879996467
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2996785126
Short name T98
Test name
Test status
Simulation time 93827821 ps
CPU time 4.03 seconds
Started Aug 09 07:50:22 PM PDT 24
Finished Aug 09 07:50:26 PM PDT 24
Peak memory 216256 kb
Host smart-0a0fd395-0eb8-46ab-80ba-5704283cbc8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996785126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2996785126
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4045053101
Short name T139
Test name
Test status
Simulation time 238576340342 ps
CPU time 561.64 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 08:04:48 PM PDT 24
Peak memory 254012 kb
Host smart-258f3d0e-55da-47b0-a1a3-8b321b243d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045053101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4045053101
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1008588534
Short name T10
Test name
Test status
Simulation time 16846987 ps
CPU time 0.69 seconds
Started Aug 09 07:55:48 PM PDT 24
Finished Aug 09 07:55:48 PM PDT 24
Peak memory 205816 kb
Host smart-f6ba3c48-15b8-4a94-bb82-a601f4d768e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008588534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1008588534
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2002201970
Short name T39
Test name
Test status
Simulation time 1358440081 ps
CPU time 20.88 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:55 PM PDT 24
Peak memory 233120 kb
Host smart-c9f7f6d5-529d-46ed-91d7-0e28cd4e043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002201970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2002201970
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1650023775
Short name T178
Test name
Test status
Simulation time 65113911602 ps
CPU time 338.87 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 08:01:07 PM PDT 24
Peak memory 257740 kb
Host smart-1d24289a-ec4d-4d6c-9f66-aed4ff99f3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650023775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1650023775
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2112090632
Short name T16
Test name
Test status
Simulation time 13154133511 ps
CPU time 191.12 seconds
Started Aug 09 07:56:10 PM PDT 24
Finished Aug 09 07:59:22 PM PDT 24
Peak memory 270156 kb
Host smart-453a33cd-5aa9-42de-b666-dcea25f51624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112090632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2112090632
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3478349770
Short name T122
Test name
Test status
Simulation time 472322064 ps
CPU time 3.02 seconds
Started Aug 09 07:50:25 PM PDT 24
Finished Aug 09 07:50:28 PM PDT 24
Peak memory 215148 kb
Host smart-6d3c66f9-ddcb-4445-9362-d88e5d41fc9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478349770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3478349770
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.606596173
Short name T208
Test name
Test status
Simulation time 7494255761 ps
CPU time 96.33 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:56:25 PM PDT 24
Peak memory 263620 kb
Host smart-4f761891-eeec-4113-bce3-5f475227eb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606596173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.606596173
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4162852332
Short name T209
Test name
Test status
Simulation time 15771537868 ps
CPU time 106.38 seconds
Started Aug 09 07:55:59 PM PDT 24
Finished Aug 09 07:57:45 PM PDT 24
Peak memory 265964 kb
Host smart-3ef97232-a368-40c2-b08b-6e73785331aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162852332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4162852332
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.410705750
Short name T94
Test name
Test status
Simulation time 17746621574 ps
CPU time 182.85 seconds
Started Aug 09 07:55:31 PM PDT 24
Finished Aug 09 07:58:34 PM PDT 24
Peak memory 264228 kb
Host smart-63549d34-a0d3-4cc2-a22c-16d6a5fd79af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410705750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.410705750
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.547176813
Short name T70
Test name
Test status
Simulation time 36078529 ps
CPU time 0.96 seconds
Started Aug 09 07:54:19 PM PDT 24
Finished Aug 09 07:54:20 PM PDT 24
Peak memory 236220 kb
Host smart-17b43ead-3ea0-4df7-93ea-5a765e029e7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547176813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.547176813
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2489050688
Short name T8
Test name
Test status
Simulation time 74265047161 ps
CPU time 244.23 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:58:48 PM PDT 24
Peak memory 251940 kb
Host smart-94f952c1-b0c1-4e6e-801c-2a5894d91fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489050688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2489050688
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1315306676
Short name T292
Test name
Test status
Simulation time 40550156093 ps
CPU time 190.28 seconds
Started Aug 09 07:55:01 PM PDT 24
Finished Aug 09 07:58:11 PM PDT 24
Peak memory 257820 kb
Host smart-aa085a5d-a136-4013-97d4-45ab0c76ca17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315306676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1315306676
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.655408244
Short name T45
Test name
Test status
Simulation time 72195365116 ps
CPU time 179.56 seconds
Started Aug 09 07:55:24 PM PDT 24
Finished Aug 09 07:58:23 PM PDT 24
Peak memory 257728 kb
Host smart-6553d68d-d27b-453a-b8b9-be5406677486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655408244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.655408244
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.785196936
Short name T174
Test name
Test status
Simulation time 5865884968 ps
CPU time 75.86 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 272368 kb
Host smart-4f60962c-83e9-4882-ab6c-efcd031a0c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785196936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
785196936
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3315204558
Short name T213
Test name
Test status
Simulation time 244329321167 ps
CPU time 445.15 seconds
Started Aug 09 07:56:42 PM PDT 24
Finished Aug 09 08:04:07 PM PDT 24
Peak memory 267072 kb
Host smart-8e727ffd-c8b1-40eb-a79c-efff4f4f8600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315204558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3315204558
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2782293882
Short name T134
Test name
Test status
Simulation time 5629480053 ps
CPU time 79.67 seconds
Started Aug 09 07:56:36 PM PDT 24
Finished Aug 09 07:57:56 PM PDT 24
Peak memory 249528 kb
Host smart-61b5f142-8eaa-4cbd-b7c0-6cbf743d217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782293882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2782293882
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1240994701
Short name T164
Test name
Test status
Simulation time 645156016 ps
CPU time 14.81 seconds
Started Aug 09 07:50:14 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 215260 kb
Host smart-23d65ac3-304b-4daa-90d0-0899e5ef2c00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240994701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1240994701
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2360471833
Short name T113
Test name
Test status
Simulation time 146765014 ps
CPU time 3.67 seconds
Started Aug 09 07:50:16 PM PDT 24
Finished Aug 09 07:50:20 PM PDT 24
Peak memory 215208 kb
Host smart-6844763b-053b-49d2-a040-27fb59226a24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360471833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
360471833
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4227586003
Short name T298
Test name
Test status
Simulation time 19000593566 ps
CPU time 130.78 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:56:41 PM PDT 24
Peak memory 249672 kb
Host smart-5d79bd2f-b2fd-4754-9f7c-d2b39917922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227586003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4227586003
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.372008762
Short name T216
Test name
Test status
Simulation time 47084211521 ps
CPU time 189.96 seconds
Started Aug 09 07:55:15 PM PDT 24
Finished Aug 09 07:58:25 PM PDT 24
Peak memory 269336 kb
Host smart-77cedec3-f74c-4510-9ef4-e61efda785fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372008762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.372008762
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.4144858834
Short name T301
Test name
Test status
Simulation time 9507658579 ps
CPU time 38.73 seconds
Started Aug 09 07:55:19 PM PDT 24
Finished Aug 09 07:55:58 PM PDT 24
Peak memory 233132 kb
Host smart-248e4b9d-6e5a-454d-897c-4ba797ae1e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144858834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4144858834
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2816232439
Short name T30
Test name
Test status
Simulation time 30737612730 ps
CPU time 174.7 seconds
Started Aug 09 07:56:17 PM PDT 24
Finished Aug 09 07:59:12 PM PDT 24
Peak memory 282408 kb
Host smart-19eb4d52-471c-46df-8bab-a014381f795d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816232439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2816232439
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1438062779
Short name T241
Test name
Test status
Simulation time 50576759367 ps
CPU time 353.7 seconds
Started Aug 09 07:56:58 PM PDT 24
Finished Aug 09 08:02:52 PM PDT 24
Peak memory 255312 kb
Host smart-7380f373-6969-492f-a6ed-479a55c0832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438062779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1438062779
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4242995603
Short name T187
Test name
Test status
Simulation time 419515906 ps
CPU time 6.74 seconds
Started Aug 09 07:50:22 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 215216 kb
Host smart-c8e20b93-0311-4ee3-a398-1891a1fc0e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242995603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4242995603
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1984270490
Short name T851
Test name
Test status
Simulation time 4551994624 ps
CPU time 21.42 seconds
Started Aug 09 07:54:18 PM PDT 24
Finished Aug 09 07:54:39 PM PDT 24
Peak memory 225004 kb
Host smart-8e5e9106-7fac-4f52-88de-3e43bc108284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984270490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1984270490
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3514410383
Short name T88
Test name
Test status
Simulation time 9909117487 ps
CPU time 20.44 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:55:05 PM PDT 24
Peak memory 216720 kb
Host smart-11321b3b-e223-4186-93bb-1dec9347c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514410383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3514410383
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2437998908
Short name T312
Test name
Test status
Simulation time 117252087782 ps
CPU time 254.68 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 07:59:43 PM PDT 24
Peak memory 253284 kb
Host smart-9d9f6a9f-24a7-4eb2-a876-3c8dd1f4def5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437998908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2437998908
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4072469431
Short name T294
Test name
Test status
Simulation time 73279234436 ps
CPU time 109.52 seconds
Started Aug 09 07:55:31 PM PDT 24
Finished Aug 09 07:57:21 PM PDT 24
Peak memory 248608 kb
Host smart-f4dc9428-565a-4d45-944e-c168e0200f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072469431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4072469431
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.713163758
Short name T296
Test name
Test status
Simulation time 25728307775 ps
CPU time 234.73 seconds
Started Aug 09 07:55:43 PM PDT 24
Finished Aug 09 07:59:38 PM PDT 24
Peak memory 266320 kb
Host smart-990ecbc6-8ab2-4977-8bf1-a3288df5b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713163758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.713163758
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1958994926
Short name T192
Test name
Test status
Simulation time 414393294 ps
CPU time 14.53 seconds
Started Aug 09 07:50:17 PM PDT 24
Finished Aug 09 07:50:31 PM PDT 24
Peak memory 215180 kb
Host smart-e63dae23-0dd7-4bd8-a131-9faba35d99ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958994926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1958994926
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.126057254
Short name T184
Test name
Test status
Simulation time 468324210 ps
CPU time 6.65 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:39 PM PDT 24
Peak memory 215296 kb
Host smart-aa2f74f6-7ca8-417f-98f7-bc9a3b1a1cef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126057254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.126057254
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3216771887
Short name T190
Test name
Test status
Simulation time 306352994 ps
CPU time 18.1 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:33 PM PDT 24
Peak memory 215296 kb
Host smart-647e148b-d955-4ded-af4c-5b4de3894f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216771887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3216771887
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2305567796
Short name T92
Test name
Test status
Simulation time 408302087 ps
CPU time 5.62 seconds
Started Aug 09 07:54:17 PM PDT 24
Finished Aug 09 07:54:23 PM PDT 24
Peak memory 224964 kb
Host smart-6916f745-e2d1-406e-976b-87d3c4cdaea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305567796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2305567796
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3327275089
Short name T237
Test name
Test status
Simulation time 3092926892 ps
CPU time 23.33 seconds
Started Aug 09 07:54:07 PM PDT 24
Finished Aug 09 07:54:30 PM PDT 24
Peak memory 255380 kb
Host smart-c8e0abf0-e475-4def-942e-0261ce2078a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327275089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3327275089
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2922517789
Short name T203
Test name
Test status
Simulation time 106350778931 ps
CPU time 115.85 seconds
Started Aug 09 07:55:14 PM PDT 24
Finished Aug 09 07:57:10 PM PDT 24
Peak memory 241408 kb
Host smart-3fc3bc8c-99ff-4a46-8342-c7b0e8fac046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922517789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2922517789
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1918763688
Short name T227
Test name
Test status
Simulation time 12445001037 ps
CPU time 117.64 seconds
Started Aug 09 07:56:43 PM PDT 24
Finished Aug 09 07:58:41 PM PDT 24
Peak memory 261368 kb
Host smart-3bf1c1e2-c6bd-43b2-adc9-a1ec49ecae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918763688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1918763688
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.732348670
Short name T222
Test name
Test status
Simulation time 7521195763 ps
CPU time 10.87 seconds
Started Aug 09 07:54:43 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 233168 kb
Host smart-65570d77-0917-40e3-b1b4-e9f11f7d4c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732348670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.732348670
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.951026711
Short name T1110
Test name
Test status
Simulation time 45203529 ps
CPU time 1.34 seconds
Started Aug 09 07:50:16 PM PDT 24
Finished Aug 09 07:50:17 PM PDT 24
Peak memory 206936 kb
Host smart-b17b03d5-20a8-433f-98b0-e30f05053cab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951026711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.951026711
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2536590977
Short name T31
Test name
Test status
Simulation time 85585300128 ps
CPU time 280.64 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 08:00:00 PM PDT 24
Peak memory 254708 kb
Host smart-577a7118-8b4c-410a-929e-bf1b32a18652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536590977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2536590977
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2566986866
Short name T1064
Test name
Test status
Simulation time 423790450 ps
CPU time 7.56 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:18 PM PDT 24
Peak memory 206872 kb
Host smart-d0b559f4-5cd2-48e0-882d-7f78c52b5587
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566986866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2566986866
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4035484781
Short name T1117
Test name
Test status
Simulation time 717129756 ps
CPU time 12.25 seconds
Started Aug 09 07:50:04 PM PDT 24
Finished Aug 09 07:50:16 PM PDT 24
Peak memory 215180 kb
Host smart-c77b0a40-fdfd-4d08-8bec-b3dbd3001434
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035484781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4035484781
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2039250085
Short name T1040
Test name
Test status
Simulation time 36791990 ps
CPU time 2.38 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:15 PM PDT 24
Peak memory 216884 kb
Host smart-10f71bec-8c26-4aca-8b2a-ee6423789cfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039250085 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2039250085
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2441325558
Short name T1078
Test name
Test status
Simulation time 23319154 ps
CPU time 1.24 seconds
Started Aug 09 07:50:05 PM PDT 24
Finished Aug 09 07:50:06 PM PDT 24
Peak memory 206896 kb
Host smart-ebf9027e-a7af-4b2c-b5f0-bf34cebbb0f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441325558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
441325558
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3842535844
Short name T1059
Test name
Test status
Simulation time 30791290 ps
CPU time 0.7 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:13 PM PDT 24
Peak memory 203608 kb
Host smart-b29482df-e087-4dd3-a8db-ff57dcbbc6d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842535844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
842535844
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.833811384
Short name T126
Test name
Test status
Simulation time 56244933 ps
CPU time 1.29 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:12 PM PDT 24
Peak memory 215096 kb
Host smart-9d4d2547-c300-4879-b497-0b95ea3584e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833811384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.833811384
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2276447818
Short name T1096
Test name
Test status
Simulation time 11080724 ps
CPU time 0.65 seconds
Started Aug 09 07:50:10 PM PDT 24
Finished Aug 09 07:50:10 PM PDT 24
Peak memory 203600 kb
Host smart-1f3b3ad0-c69e-4027-bfc8-218100ee6d55
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276447818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2276447818
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3070161906
Short name T1036
Test name
Test status
Simulation time 608924553 ps
CPU time 3.82 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:16 PM PDT 24
Peak memory 215192 kb
Host smart-5b3bf3fc-f903-419f-82e5-533bbb72d49f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070161906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3070161906
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2436941286
Short name T106
Test name
Test status
Simulation time 406732533 ps
CPU time 2.79 seconds
Started Aug 09 07:50:09 PM PDT 24
Finished Aug 09 07:50:12 PM PDT 24
Peak memory 215240 kb
Host smart-45380313-bcc6-4e01-a10b-975cd8a49a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436941286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
436941286
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1010323689
Short name T186
Test name
Test status
Simulation time 201539428 ps
CPU time 13.02 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:24 PM PDT 24
Peak memory 215432 kb
Host smart-03de28ce-822a-4f34-948b-cc9ad09ca450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010323689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1010323689
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.236463632
Short name T133
Test name
Test status
Simulation time 624184564 ps
CPU time 15.59 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:27 PM PDT 24
Peak memory 215244 kb
Host smart-8e52252c-fcd6-4800-b2ae-a75060f1f16f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236463632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.236463632
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.675725765
Short name T163
Test name
Test status
Simulation time 3618734081 ps
CPU time 14.72 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:26 PM PDT 24
Peak memory 207220 kb
Host smart-cd6db766-2ac6-44b0-9a77-5a0686344958
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675725765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.675725765
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3418436702
Short name T84
Test name
Test status
Simulation time 20801778 ps
CPU time 0.96 seconds
Started Aug 09 07:50:08 PM PDT 24
Finished Aug 09 07:50:09 PM PDT 24
Peak memory 206856 kb
Host smart-a618bc41-9662-42d9-8932-26ab53079058
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418436702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3418436702
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4138056641
Short name T166
Test name
Test status
Simulation time 59337598 ps
CPU time 1.79 seconds
Started Aug 09 07:50:09 PM PDT 24
Finished Aug 09 07:50:11 PM PDT 24
Peak memory 215316 kb
Host smart-88a2ad13-e070-4e38-9980-b287b49929bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138056641 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4138056641
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1594786340
Short name T132
Test name
Test status
Simulation time 94860113 ps
CPU time 2.72 seconds
Started Aug 09 07:50:08 PM PDT 24
Finished Aug 09 07:50:11 PM PDT 24
Peak memory 206944 kb
Host smart-e044fc1b-4bcf-453d-81da-c1e003905087
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594786340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
594786340
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3152845719
Short name T1042
Test name
Test status
Simulation time 16680347 ps
CPU time 0.72 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:12 PM PDT 24
Peak memory 203684 kb
Host smart-da465067-0409-44e4-9552-5a4fe12bfd83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152845719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
152845719
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2249219400
Short name T123
Test name
Test status
Simulation time 111042971 ps
CPU time 1.78 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:17 PM PDT 24
Peak memory 215092 kb
Host smart-053d64d9-bae0-4b39-a546-96ced3c37fb3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249219400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2249219400
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2735329277
Short name T1075
Test name
Test status
Simulation time 53939213 ps
CPU time 0.64 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:11 PM PDT 24
Peak memory 203692 kb
Host smart-3bc58437-5bed-4b89-82e3-81b4bb98586b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735329277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2735329277
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3056402125
Short name T1062
Test name
Test status
Simulation time 97464410 ps
CPU time 1.77 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:13 PM PDT 24
Peak memory 215148 kb
Host smart-aff46959-990d-4135-b815-1c5bf9908a5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056402125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3056402125
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2474957935
Short name T1074
Test name
Test status
Simulation time 273294520 ps
CPU time 2.01 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:14 PM PDT 24
Peak memory 215236 kb
Host smart-2196916a-633c-4048-a7e6-becc4e11a039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474957935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
474957935
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.291977626
Short name T101
Test name
Test status
Simulation time 911906154 ps
CPU time 7.04 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:18 PM PDT 24
Peak memory 215464 kb
Host smart-c66f9ca8-c0b7-410f-9248-070b6c469e32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291977626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.291977626
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.257183843
Short name T1107
Test name
Test status
Simulation time 52637847 ps
CPU time 3.76 seconds
Started Aug 09 07:50:31 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 218524 kb
Host smart-9d8fdeb8-869d-4bc1-b555-fb53edc2127e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257183843 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.257183843
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4268443275
Short name T131
Test name
Test status
Simulation time 39097219 ps
CPU time 2.41 seconds
Started Aug 09 07:50:25 PM PDT 24
Finished Aug 09 07:50:28 PM PDT 24
Peak memory 215160 kb
Host smart-0e7f52b8-0633-4087-ada8-5d92d092946f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268443275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4268443275
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1750250078
Short name T1027
Test name
Test status
Simulation time 26549960 ps
CPU time 0.72 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:25 PM PDT 24
Peak memory 203620 kb
Host smart-6253b9e3-072f-45d0-bb39-896e66323133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750250078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1750250078
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1993065779
Short name T1124
Test name
Test status
Simulation time 208113281 ps
CPU time 4.32 seconds
Started Aug 09 07:50:25 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 215256 kb
Host smart-7da49d63-1649-4f3c-9d1e-98567bfa0449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993065779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1993065779
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2244100438
Short name T108
Test name
Test status
Simulation time 169591092 ps
CPU time 4.74 seconds
Started Aug 09 07:50:25 PM PDT 24
Finished Aug 09 07:50:30 PM PDT 24
Peak memory 215284 kb
Host smart-13337f4e-299a-4ff6-b4fc-13e662bdb24c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244100438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2244100438
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1679914901
Short name T194
Test name
Test status
Simulation time 102166764 ps
CPU time 6.06 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:30 PM PDT 24
Peak memory 215196 kb
Host smart-3edc0ae6-d9a3-48aa-b401-1c848bce9a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679914901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1679914901
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3262489890
Short name T1057
Test name
Test status
Simulation time 167795653 ps
CPU time 3 seconds
Started Aug 09 07:50:30 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 216740 kb
Host smart-72bbf064-b75f-4f08-a98d-9eb211537c8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262489890 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3262489890
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2956229907
Short name T127
Test name
Test status
Simulation time 1096156775 ps
CPU time 2.75 seconds
Started Aug 09 07:50:25 PM PDT 24
Finished Aug 09 07:50:28 PM PDT 24
Peak memory 215144 kb
Host smart-9172b6cb-139e-4532-9d2e-cae618936297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956229907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2956229907
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1002171586
Short name T1017
Test name
Test status
Simulation time 38807736 ps
CPU time 0.75 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:25 PM PDT 24
Peak memory 203668 kb
Host smart-63ec4a5d-3622-4c8f-a2ae-0b0d1d73d662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002171586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1002171586
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2464013187
Short name T1054
Test name
Test status
Simulation time 452520597 ps
CPU time 3.11 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:27 PM PDT 24
Peak memory 215156 kb
Host smart-442ab3f9-b8c8-46c4-80c8-cd92056649f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464013187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2464013187
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1919276349
Short name T1100
Test name
Test status
Simulation time 462712573 ps
CPU time 3.37 seconds
Started Aug 09 07:50:23 PM PDT 24
Finished Aug 09 07:50:26 PM PDT 24
Peak memory 215356 kb
Host smart-7fb2f8b6-b35a-43c7-b4ce-413cc3645b19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919276349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1919276349
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3855459407
Short name T67
Test name
Test status
Simulation time 42123236 ps
CPU time 2.74 seconds
Started Aug 09 07:50:20 PM PDT 24
Finished Aug 09 07:50:23 PM PDT 24
Peak memory 216356 kb
Host smart-7cd55b94-cb70-444e-a652-b4a6116f1826
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855459407 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3855459407
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2150986581
Short name T1048
Test name
Test status
Simulation time 144818753 ps
CPU time 1.39 seconds
Started Aug 09 07:50:23 PM PDT 24
Finished Aug 09 07:50:25 PM PDT 24
Peak memory 207032 kb
Host smart-43af0589-d713-4239-a8e3-13698994adf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150986581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2150986581
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.89410053
Short name T1129
Test name
Test status
Simulation time 102964707 ps
CPU time 0.7 seconds
Started Aug 09 07:50:23 PM PDT 24
Finished Aug 09 07:50:23 PM PDT 24
Peak memory 203668 kb
Host smart-adf68edb-c9cf-4cec-b564-112da0d2ed6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89410053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.89410053
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.858719145
Short name T1031
Test name
Test status
Simulation time 112431193 ps
CPU time 1.95 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:26 PM PDT 24
Peak memory 215220 kb
Host smart-52f23aaf-38a7-4456-91ef-ae4f7d147450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858719145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.858719145
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2970719257
Short name T104
Test name
Test status
Simulation time 195360268 ps
CPU time 2.75 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 215144 kb
Host smart-6328933f-ac34-4e12-ac46-64f7bf7de79c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970719257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2970719257
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.676891299
Short name T1085
Test name
Test status
Simulation time 659945532 ps
CPU time 9.84 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 215252 kb
Host smart-48e4084d-3298-45c4-9c48-41bc9b34b662
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676891299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.676891299
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2677509847
Short name T115
Test name
Test status
Simulation time 47046357 ps
CPU time 1.57 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:28 PM PDT 24
Peak memory 215272 kb
Host smart-2772c166-3883-4794-8ee4-a050035344a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677509847 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2677509847
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1273541083
Short name T165
Test name
Test status
Simulation time 150880388 ps
CPU time 1.4 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:27 PM PDT 24
Peak memory 215056 kb
Host smart-9c1c3c67-c316-40b4-94cd-d359d00b8655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273541083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1273541083
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3968941467
Short name T1082
Test name
Test status
Simulation time 50244422 ps
CPU time 0.8 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:25 PM PDT 24
Peak memory 203668 kb
Host smart-2a6b2abe-9ab6-4c62-8bfa-7e8efc9275cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968941467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3968941467
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.657859416
Short name T1024
Test name
Test status
Simulation time 180983930 ps
CPU time 1.89 seconds
Started Aug 09 07:50:25 PM PDT 24
Finished Aug 09 07:50:27 PM PDT 24
Peak memory 206952 kb
Host smart-612464ec-a5a1-4a41-8771-a40de880e343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657859416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.657859416
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4074866740
Short name T1099
Test name
Test status
Simulation time 101363878 ps
CPU time 2.71 seconds
Started Aug 09 07:50:22 PM PDT 24
Finished Aug 09 07:50:25 PM PDT 24
Peak memory 215308 kb
Host smart-4cd8110b-f45e-4dcd-b7e5-b81588da1cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074866740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4074866740
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3838560353
Short name T111
Test name
Test status
Simulation time 2246875580 ps
CPU time 13.46 seconds
Started Aug 09 07:50:22 PM PDT 24
Finished Aug 09 07:50:36 PM PDT 24
Peak memory 215540 kb
Host smart-7a1cdc85-d1a9-433b-9733-06c3c4b95775
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838560353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3838560353
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2479311698
Short name T1037
Test name
Test status
Simulation time 40855345 ps
CPU time 1.6 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 215472 kb
Host smart-3861312a-143e-45f4-88de-d1a135fdb4b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479311698 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2479311698
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.567643216
Short name T1090
Test name
Test status
Simulation time 68057661 ps
CPU time 2.05 seconds
Started Aug 09 07:50:27 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 215152 kb
Host smart-d7feb7ef-72c7-4d2e-9339-5976bdfd722f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567643216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.567643216
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2851935614
Short name T1084
Test name
Test status
Simulation time 53517486 ps
CPU time 0.75 seconds
Started Aug 09 07:50:27 PM PDT 24
Finished Aug 09 07:50:28 PM PDT 24
Peak memory 203688 kb
Host smart-467d4016-07b7-4c77-b399-6848361dffc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851935614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2851935614
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3412152850
Short name T1069
Test name
Test status
Simulation time 285723004 ps
CPU time 1.96 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:28 PM PDT 24
Peak memory 206916 kb
Host smart-4d6d245b-b97d-4b20-a52f-5bf497c0e19f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412152850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3412152850
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3514137671
Short name T118
Test name
Test status
Simulation time 3624658784 ps
CPU time 22.88 seconds
Started Aug 09 07:50:27 PM PDT 24
Finished Aug 09 07:50:50 PM PDT 24
Peak memory 215312 kb
Host smart-7bd78aad-8ace-4883-a0e8-39de116c0825
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514137671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3514137671
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1859766245
Short name T68
Test name
Test status
Simulation time 26592115 ps
CPU time 1.71 seconds
Started Aug 09 07:50:28 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 216164 kb
Host smart-726594b6-2669-4511-8c56-9941e651efe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859766245 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1859766245
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.30091695
Short name T1106
Test name
Test status
Simulation time 102550901 ps
CPU time 2.57 seconds
Started Aug 09 07:50:28 PM PDT 24
Finished Aug 09 07:50:31 PM PDT 24
Peak memory 215364 kb
Host smart-2c4eaffb-7f07-43b0-821b-e8145398f3dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30091695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.30091695
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1624162194
Short name T1127
Test name
Test status
Simulation time 26406827 ps
CPU time 0.73 seconds
Started Aug 09 07:50:28 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 203956 kb
Host smart-1d840c51-5851-4951-9750-4ee1ce1c457b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624162194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1624162194
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2215207499
Short name T1128
Test name
Test status
Simulation time 269993602 ps
CPU time 1.81 seconds
Started Aug 09 07:50:27 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 207000 kb
Host smart-e081d68c-e0cb-4856-b2fd-aa14ed0df710
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215207499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2215207499
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4058974971
Short name T1101
Test name
Test status
Simulation time 107255806 ps
CPU time 1.86 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:28 PM PDT 24
Peak memory 216300 kb
Host smart-c79c1fd8-b013-4673-9801-0732b4577d68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058974971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4058974971
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2875569703
Short name T1043
Test name
Test status
Simulation time 114336975 ps
CPU time 6.15 seconds
Started Aug 09 07:50:28 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 215240 kb
Host smart-1cbbf56f-1728-4ddc-b540-fd82132e3928
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875569703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2875569703
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1397360861
Short name T1051
Test name
Test status
Simulation time 192284043 ps
CPU time 1.7 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 215164 kb
Host smart-0bf4934e-63bf-4207-a659-89381fa3c3e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397360861 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1397360861
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1124223837
Short name T1079
Test name
Test status
Simulation time 21078886 ps
CPU time 0.73 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:27 PM PDT 24
Peak memory 203620 kb
Host smart-f12f34c8-1519-4e2e-b1ea-e02a76138477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124223837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1124223837
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.974316461
Short name T1087
Test name
Test status
Simulation time 130093960 ps
CPU time 2.99 seconds
Started Aug 09 07:50:31 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 215124 kb
Host smart-59beb946-3bd5-47bd-92d9-13113b34a782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974316461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.974316461
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4005846703
Short name T103
Test name
Test status
Simulation time 113223485 ps
CPU time 1.9 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 215280 kb
Host smart-062a285d-8805-4541-baa4-8e15dfdf02d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005846703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4005846703
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4060435125
Short name T193
Test name
Test status
Simulation time 298035728 ps
CPU time 6.95 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 215360 kb
Host smart-355c29a4-1614-4b8d-a9bc-eff8d75ce330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060435125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4060435125
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.670868762
Short name T1046
Test name
Test status
Simulation time 50941098 ps
CPU time 1.77 seconds
Started Aug 09 07:50:31 PM PDT 24
Finished Aug 09 07:50:33 PM PDT 24
Peak memory 216608 kb
Host smart-480a3a00-8157-4388-8b68-8f7be12d8fb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670868762 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.670868762
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.504628559
Short name T150
Test name
Test status
Simulation time 77261154 ps
CPU time 1.33 seconds
Started Aug 09 07:50:28 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 207164 kb
Host smart-fc11b2bf-d1d2-4992-8417-02ca271cec9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504628559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.504628559
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2490418352
Short name T1118
Test name
Test status
Simulation time 12263938 ps
CPU time 0.75 seconds
Started Aug 09 07:50:28 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 203644 kb
Host smart-f3396b48-309c-4129-9784-822a7648469d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490418352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2490418352
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2061450763
Short name T1065
Test name
Test status
Simulation time 40358897 ps
CPU time 2.8 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:29 PM PDT 24
Peak memory 215232 kb
Host smart-bef64d54-2e50-4721-9f03-aec3e3087865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061450763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2061450763
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3266097026
Short name T116
Test name
Test status
Simulation time 197124339 ps
CPU time 5.28 seconds
Started Aug 09 07:50:30 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 214132 kb
Host smart-cd3d71fa-1e14-40f7-b314-87f69feb8e50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266097026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3266097026
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1847962711
Short name T100
Test name
Test status
Simulation time 2491678896 ps
CPU time 13.99 seconds
Started Aug 09 07:50:28 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 214284 kb
Host smart-862a8fe5-595b-49cd-857a-2bfb302b0e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847962711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1847962711
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3480561209
Short name T1108
Test name
Test status
Simulation time 94072310 ps
CPU time 1.57 seconds
Started Aug 09 07:50:34 PM PDT 24
Finished Aug 09 07:50:36 PM PDT 24
Peak memory 215404 kb
Host smart-50ef5ad2-2ad8-4d02-8000-f4f8938df918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480561209 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3480561209
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1428812288
Short name T124
Test name
Test status
Simulation time 20663993 ps
CPU time 1.31 seconds
Started Aug 09 07:50:27 PM PDT 24
Finished Aug 09 07:50:28 PM PDT 24
Peak memory 215112 kb
Host smart-e96e5bfd-e6ac-4b8c-a260-76a53c229bb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428812288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1428812288
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4207060377
Short name T1093
Test name
Test status
Simulation time 32849355 ps
CPU time 0.74 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:27 PM PDT 24
Peak memory 203672 kb
Host smart-9a6284a1-553f-4de0-875a-2d9d75fd7846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207060377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4207060377
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1752903615
Short name T1044
Test name
Test status
Simulation time 154221613 ps
CPU time 4.29 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:37 PM PDT 24
Peak memory 215736 kb
Host smart-518c6182-bdf1-4e49-b11f-1ef5fb6f7870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752903615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1752903615
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1242842189
Short name T110
Test name
Test status
Simulation time 952463293 ps
CPU time 5.65 seconds
Started Aug 09 07:50:28 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 215252 kb
Host smart-e0014209-8dd4-403e-8baa-5735046deabc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242842189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1242842189
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1527715771
Short name T112
Test name
Test status
Simulation time 86259259 ps
CPU time 1.79 seconds
Started Aug 09 07:50:32 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 216256 kb
Host smart-51f27913-ba5c-4865-9ebb-f15016302b91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527715771 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1527715771
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3681092371
Short name T1073
Test name
Test status
Simulation time 58149340 ps
CPU time 2.02 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 207092 kb
Host smart-3a1570fd-0d2c-4569-82e3-8dac5cea4f64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681092371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3681092371
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1346786583
Short name T1072
Test name
Test status
Simulation time 58622049 ps
CPU time 0.76 seconds
Started Aug 09 07:50:31 PM PDT 24
Finished Aug 09 07:50:31 PM PDT 24
Peak memory 203656 kb
Host smart-3377a5d1-740e-4a28-b38a-f7bc0836ce48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346786583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1346786583
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.983539819
Short name T1102
Test name
Test status
Simulation time 252731133 ps
CPU time 3.72 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 215152 kb
Host smart-d2415e9b-2666-423f-9ad9-4ca3da00e4f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983539819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.983539819
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1862755601
Short name T1097
Test name
Test status
Simulation time 128583827 ps
CPU time 3.72 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:37 PM PDT 24
Peak memory 215252 kb
Host smart-b69068c2-08be-4cde-a14f-4c7f8c374edf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862755601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1862755601
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3793568368
Short name T1104
Test name
Test status
Simulation time 874453516 ps
CPU time 9.68 seconds
Started Aug 09 07:50:09 PM PDT 24
Finished Aug 09 07:50:18 PM PDT 24
Peak memory 215148 kb
Host smart-f81a7445-7b7b-454f-9c44-d6a037ae342a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793568368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3793568368
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.650768921
Short name T1125
Test name
Test status
Simulation time 982344587 ps
CPU time 13.33 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:25 PM PDT 24
Peak memory 207200 kb
Host smart-960b9b19-74a3-498c-bd28-c0cb95c3d45f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650768921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.650768921
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.589617875
Short name T86
Test name
Test status
Simulation time 86308822 ps
CPU time 1.37 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:13 PM PDT 24
Peak memory 216212 kb
Host smart-b5c0abe8-c08c-460c-b221-35f939db556e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589617875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.589617875
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3355497527
Short name T1063
Test name
Test status
Simulation time 674741215 ps
CPU time 3.91 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:15 PM PDT 24
Peak memory 218300 kb
Host smart-07a1ddde-c136-4225-9786-4fc7a0d75df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355497527 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3355497527
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1989188150
Short name T1081
Test name
Test status
Simulation time 75301428 ps
CPU time 1.22 seconds
Started Aug 09 07:50:09 PM PDT 24
Finished Aug 09 07:50:11 PM PDT 24
Peak memory 206892 kb
Host smart-e03e0340-85a7-411e-ad53-b0833ca8742d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989188150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
989188150
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1266966598
Short name T1103
Test name
Test status
Simulation time 27260434 ps
CPU time 0.8 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:13 PM PDT 24
Peak memory 203636 kb
Host smart-9640b66c-a027-40ca-8a5f-be1b0d21abee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266966598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
266966598
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.233535653
Short name T1086
Test name
Test status
Simulation time 61317514 ps
CPU time 2.15 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:13 PM PDT 24
Peak memory 215144 kb
Host smart-ce7695cc-069a-49d7-9ae0-70ae48f90540
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233535653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.233535653
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2335137140
Short name T1126
Test name
Test status
Simulation time 16416527 ps
CPU time 0.66 seconds
Started Aug 09 07:50:10 PM PDT 24
Finished Aug 09 07:50:10 PM PDT 24
Peak memory 203608 kb
Host smart-02144a1f-9b22-49ad-9530-3b30de8304ed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335137140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2335137140
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2973976518
Short name T1060
Test name
Test status
Simulation time 106699708 ps
CPU time 3.12 seconds
Started Aug 09 07:50:09 PM PDT 24
Finished Aug 09 07:50:12 PM PDT 24
Peak memory 215196 kb
Host smart-9709b923-9e05-41be-9db4-77a3f77e5a2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973976518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2973976518
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.887615495
Short name T107
Test name
Test status
Simulation time 168866999 ps
CPU time 2.4 seconds
Started Aug 09 07:50:09 PM PDT 24
Finished Aug 09 07:50:11 PM PDT 24
Peak memory 215220 kb
Host smart-e39b415a-88ed-4f27-abd5-5f57fea3067f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887615495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.887615495
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2993299668
Short name T188
Test name
Test status
Simulation time 5442606259 ps
CPU time 15.1 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:27 PM PDT 24
Peak memory 215452 kb
Host smart-78219f22-f4d0-422a-8c06-90a256ffa603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993299668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2993299668
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2869416637
Short name T1052
Test name
Test status
Simulation time 111192010 ps
CPU time 0.72 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 203660 kb
Host smart-c860f926-4c7d-45b2-a65a-57252e33d911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869416637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2869416637
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.377084857
Short name T1023
Test name
Test status
Simulation time 12372211 ps
CPU time 0.7 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 203684 kb
Host smart-2c156d0b-b484-4c92-8b2c-49d319814587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377084857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.377084857
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1056962942
Short name T1120
Test name
Test status
Simulation time 20314792 ps
CPU time 0.71 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 203668 kb
Host smart-be64937d-a20f-4fee-915e-2a3dec7e21f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056962942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1056962942
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1014292696
Short name T1111
Test name
Test status
Simulation time 19413767 ps
CPU time 0.75 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 203652 kb
Host smart-1118040d-bfd9-4898-a652-522091b50df0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014292696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1014292696
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1445168872
Short name T1055
Test name
Test status
Simulation time 84142341 ps
CPU time 0.7 seconds
Started Aug 09 07:50:35 PM PDT 24
Finished Aug 09 07:50:36 PM PDT 24
Peak memory 203972 kb
Host smart-60b5f178-5e5d-403d-8ace-f134ae96b863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445168872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1445168872
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4080600565
Short name T1105
Test name
Test status
Simulation time 41732082 ps
CPU time 0.76 seconds
Started Aug 09 07:50:35 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 203996 kb
Host smart-b4417e25-b107-40d3-9ffe-e9dd14aeb5e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080600565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4080600565
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3061630972
Short name T1021
Test name
Test status
Simulation time 30193057 ps
CPU time 0.77 seconds
Started Aug 09 07:50:34 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 203648 kb
Host smart-ab88a5e9-aacf-43c0-8976-eabaedada539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061630972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3061630972
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.748784038
Short name T1123
Test name
Test status
Simulation time 14645454 ps
CPU time 0.75 seconds
Started Aug 09 07:50:36 PM PDT 24
Finished Aug 09 07:50:36 PM PDT 24
Peak memory 203668 kb
Host smart-d52d4ff9-bc0c-4595-a3f7-32aad8bf8331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748784038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.748784038
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2384688854
Short name T1058
Test name
Test status
Simulation time 15323705 ps
CPU time 0.73 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 203948 kb
Host smart-eebdb240-3df1-45db-ae1e-f84fcbe30598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384688854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2384688854
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3273420182
Short name T1068
Test name
Test status
Simulation time 40377130 ps
CPU time 0.72 seconds
Started Aug 09 07:50:34 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 202564 kb
Host smart-79406030-0f73-4095-a1b6-3245cb8e93ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273420182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3273420182
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2822085865
Short name T121
Test name
Test status
Simulation time 610314931 ps
CPU time 16.36 seconds
Started Aug 09 07:50:14 PM PDT 24
Finished Aug 09 07:50:30 PM PDT 24
Peak memory 215212 kb
Host smart-955d3aef-a2a5-4135-9923-35e5da16a0f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822085865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2822085865
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2072255692
Short name T130
Test name
Test status
Simulation time 754921550 ps
CPU time 11.35 seconds
Started Aug 09 07:50:07 PM PDT 24
Finished Aug 09 07:50:19 PM PDT 24
Peak memory 207076 kb
Host smart-98fbfd0d-621f-4cee-ad62-338f2ef97cbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072255692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2072255692
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.449777903
Short name T85
Test name
Test status
Simulation time 47320581 ps
CPU time 1.43 seconds
Started Aug 09 07:50:09 PM PDT 24
Finished Aug 09 07:50:11 PM PDT 24
Peak memory 206960 kb
Host smart-b04820fe-4ff7-411c-beac-5e0659e258cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449777903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.449777903
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3224041852
Short name T117
Test name
Test status
Simulation time 94569434 ps
CPU time 1.85 seconds
Started Aug 09 07:50:09 PM PDT 24
Finished Aug 09 07:50:11 PM PDT 24
Peak memory 216412 kb
Host smart-5b27af5b-f510-49ca-ab42-9b6aa6342fad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224041852 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3224041852
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1482116916
Short name T1114
Test name
Test status
Simulation time 63090087 ps
CPU time 1.83 seconds
Started Aug 09 07:50:09 PM PDT 24
Finished Aug 09 07:50:11 PM PDT 24
Peak memory 215096 kb
Host smart-ad6b7d31-489e-44dc-a141-1c8aec8f2d01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482116916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
482116916
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.444448231
Short name T1022
Test name
Test status
Simulation time 22351425 ps
CPU time 0.76 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:13 PM PDT 24
Peak memory 203644 kb
Host smart-297fc183-a640-4147-ba7f-829a936d9606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444448231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.444448231
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4265621773
Short name T1070
Test name
Test status
Simulation time 82194460 ps
CPU time 1.94 seconds
Started Aug 09 07:50:11 PM PDT 24
Finished Aug 09 07:50:13 PM PDT 24
Peak memory 215068 kb
Host smart-c434aa3c-38fd-4148-9984-536b8115f584
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265621773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4265621773
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1260419105
Short name T1041
Test name
Test status
Simulation time 10245835 ps
CPU time 0.71 seconds
Started Aug 09 07:50:14 PM PDT 24
Finished Aug 09 07:50:14 PM PDT 24
Peak memory 203920 kb
Host smart-3472eb53-e1fc-43a1-b86b-71ea1e37d387
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260419105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1260419105
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3815959860
Short name T1098
Test name
Test status
Simulation time 155625489 ps
CPU time 4.42 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:16 PM PDT 24
Peak memory 215172 kb
Host smart-bde67830-9c84-459a-a98f-d218220541e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815959860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3815959860
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.689003003
Short name T114
Test name
Test status
Simulation time 116021496 ps
CPU time 3.63 seconds
Started Aug 09 07:50:14 PM PDT 24
Finished Aug 09 07:50:18 PM PDT 24
Peak memory 215288 kb
Host smart-61fc52df-044c-48fc-bb7a-0ac55ed2405c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689003003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.689003003
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2811332190
Short name T1053
Test name
Test status
Simulation time 44598296 ps
CPU time 0.77 seconds
Started Aug 09 07:50:35 PM PDT 24
Finished Aug 09 07:50:36 PM PDT 24
Peak memory 203508 kb
Host smart-c6a0280a-2b5e-47e8-9e3c-623a8b2da1f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811332190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2811332190
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.190270917
Short name T1116
Test name
Test status
Simulation time 40375645 ps
CPU time 0.69 seconds
Started Aug 09 07:50:31 PM PDT 24
Finished Aug 09 07:50:32 PM PDT 24
Peak memory 203672 kb
Host smart-04988888-09d2-4e5f-ba50-b38dd3b44b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190270917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.190270917
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.457456251
Short name T1029
Test name
Test status
Simulation time 28013647 ps
CPU time 0.81 seconds
Started Aug 09 07:50:35 PM PDT 24
Finished Aug 09 07:50:36 PM PDT 24
Peak memory 203556 kb
Host smart-88d8de45-68aa-45f5-863d-385e038028ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457456251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.457456251
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2459208263
Short name T1071
Test name
Test status
Simulation time 20946995 ps
CPU time 0.73 seconds
Started Aug 09 07:50:32 PM PDT 24
Finished Aug 09 07:50:33 PM PDT 24
Peak memory 203948 kb
Host smart-954f0336-c63f-4f43-8d82-2067b2020d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459208263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2459208263
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2141671293
Short name T1034
Test name
Test status
Simulation time 42514000 ps
CPU time 0.74 seconds
Started Aug 09 07:50:38 PM PDT 24
Finished Aug 09 07:50:39 PM PDT 24
Peak memory 203688 kb
Host smart-59ca1dd3-b1a1-44b9-84c9-ba6333b3d31b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141671293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2141671293
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2673939172
Short name T1035
Test name
Test status
Simulation time 13398165 ps
CPU time 0.7 seconds
Started Aug 09 07:50:35 PM PDT 24
Finished Aug 09 07:50:36 PM PDT 24
Peak memory 203672 kb
Host smart-eb1eebc0-5b75-48ba-9767-9af008abc5df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673939172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2673939172
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4135870851
Short name T1119
Test name
Test status
Simulation time 38930088 ps
CPU time 0.73 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 203948 kb
Host smart-f82f5870-a2ba-4501-9408-a38c977a2635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135870851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4135870851
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4157958972
Short name T1121
Test name
Test status
Simulation time 17235833 ps
CPU time 0.73 seconds
Started Aug 09 07:50:40 PM PDT 24
Finished Aug 09 07:50:41 PM PDT 24
Peak memory 203820 kb
Host smart-5f59e2c5-2f93-42c5-927c-ae701a1a0036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157958972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4157958972
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.32732091
Short name T1130
Test name
Test status
Simulation time 23020643 ps
CPU time 0.73 seconds
Started Aug 09 07:50:35 PM PDT 24
Finished Aug 09 07:50:36 PM PDT 24
Peak memory 203680 kb
Host smart-ac463d3a-5f3e-413a-a915-a0113d7bad4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32732091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.32732091
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4074395488
Short name T1122
Test name
Test status
Simulation time 23336886 ps
CPU time 0.73 seconds
Started Aug 09 07:50:32 PM PDT 24
Finished Aug 09 07:50:33 PM PDT 24
Peak memory 203960 kb
Host smart-ddab1c0f-2dee-4c45-99a9-0bc4fecd4d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074395488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
4074395488
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3759411135
Short name T1091
Test name
Test status
Simulation time 1962186142 ps
CPU time 14.42 seconds
Started Aug 09 07:50:17 PM PDT 24
Finished Aug 09 07:50:32 PM PDT 24
Peak memory 215172 kb
Host smart-e92db546-e460-4a12-8b70-5499357afa58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759411135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3759411135
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3781620927
Short name T1109
Test name
Test status
Simulation time 363650375 ps
CPU time 23.97 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:48 PM PDT 24
Peak memory 206988 kb
Host smart-f808eddf-5d65-4a65-8f30-d2bd3f037c0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781620927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3781620927
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.819461541
Short name T87
Test name
Test status
Simulation time 174051362 ps
CPU time 0.98 seconds
Started Aug 09 07:50:17 PM PDT 24
Finished Aug 09 07:50:18 PM PDT 24
Peak memory 206744 kb
Host smart-5cbe847f-f83b-49f4-a26f-19dba7d40f30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819461541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.819461541
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3074932949
Short name T1095
Test name
Test status
Simulation time 40818947 ps
CPU time 2.58 seconds
Started Aug 09 07:50:17 PM PDT 24
Finished Aug 09 07:50:20 PM PDT 24
Peak memory 217112 kb
Host smart-03b665c8-9421-4856-8589-c5af12dd235a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074932949 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3074932949
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1029916810
Short name T128
Test name
Test status
Simulation time 33540038 ps
CPU time 1.24 seconds
Started Aug 09 07:50:14 PM PDT 24
Finished Aug 09 07:50:16 PM PDT 24
Peak memory 206952 kb
Host smart-07f807a3-f70a-4844-8723-47b1db29937d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029916810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
029916810
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3490066608
Short name T1045
Test name
Test status
Simulation time 12736482 ps
CPU time 0.7 seconds
Started Aug 09 07:50:16 PM PDT 24
Finished Aug 09 07:50:16 PM PDT 24
Peak memory 203668 kb
Host smart-f2b0b463-4a2b-4910-a95b-ef07f3ef7767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490066608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
490066608
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3600190333
Short name T125
Test name
Test status
Simulation time 76759952 ps
CPU time 1.73 seconds
Started Aug 09 07:50:19 PM PDT 24
Finished Aug 09 07:50:21 PM PDT 24
Peak memory 215144 kb
Host smart-07c747b5-1100-49a6-b254-c5974625da5d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600190333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3600190333
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1590446932
Short name T1112
Test name
Test status
Simulation time 19503475 ps
CPU time 0.66 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:16 PM PDT 24
Peak memory 203676 kb
Host smart-59a17a0e-eb2d-4798-9210-bb9921908f1a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590446932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1590446932
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4043923823
Short name T1019
Test name
Test status
Simulation time 605133335 ps
CPU time 4.28 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:19 PM PDT 24
Peak memory 215160 kb
Host smart-7613905f-6d81-48d6-85d2-acdd916cfc83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043923823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4043923823
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1247360052
Short name T1039
Test name
Test status
Simulation time 89710257 ps
CPU time 1.6 seconds
Started Aug 09 07:50:12 PM PDT 24
Finished Aug 09 07:50:14 PM PDT 24
Peak memory 215244 kb
Host smart-e5d3c081-4c0c-4062-8f1c-bbae5ea3f751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247360052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
247360052
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2898055179
Short name T189
Test name
Test status
Simulation time 1453052328 ps
CPU time 8.38 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:23 PM PDT 24
Peak memory 215624 kb
Host smart-7599aee0-d469-4200-8794-33acf2953bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898055179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2898055179
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.916149854
Short name T1066
Test name
Test status
Simulation time 26612509 ps
CPU time 0.71 seconds
Started Aug 09 07:50:33 PM PDT 24
Finished Aug 09 07:50:34 PM PDT 24
Peak memory 203676 kb
Host smart-88c5d76d-e549-4f75-be94-e45334140734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916149854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.916149854
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.860900736
Short name T1033
Test name
Test status
Simulation time 25214862 ps
CPU time 0.81 seconds
Started Aug 09 07:50:35 PM PDT 24
Finished Aug 09 07:50:36 PM PDT 24
Peak memory 203628 kb
Host smart-6bd323cb-3295-40d4-80d8-06ba52fd0d02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860900736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.860900736
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1145425251
Short name T1020
Test name
Test status
Simulation time 53588374 ps
CPU time 0.76 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:39 PM PDT 24
Peak memory 203692 kb
Host smart-b1d924b8-774e-4b78-b603-d46d0dd252fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145425251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1145425251
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2267138630
Short name T1056
Test name
Test status
Simulation time 65083792 ps
CPU time 0.72 seconds
Started Aug 09 07:50:40 PM PDT 24
Finished Aug 09 07:50:41 PM PDT 24
Peak memory 203816 kb
Host smart-06323001-c7c9-4186-baea-59098c2fe14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267138630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2267138630
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1120635659
Short name T1030
Test name
Test status
Simulation time 30301169 ps
CPU time 0.73 seconds
Started Aug 09 07:50:32 PM PDT 24
Finished Aug 09 07:50:33 PM PDT 24
Peak memory 203652 kb
Host smart-bb8f5218-5276-4eaf-83a4-268deef4c727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120635659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1120635659
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.873092760
Short name T1061
Test name
Test status
Simulation time 17333209 ps
CPU time 0.77 seconds
Started Aug 09 07:50:35 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 203648 kb
Host smart-20fb95af-d6a0-4330-af90-aff5bf2d160b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873092760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.873092760
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2290232470
Short name T1026
Test name
Test status
Simulation time 26545219 ps
CPU time 0.79 seconds
Started Aug 09 07:50:37 PM PDT 24
Finished Aug 09 07:50:38 PM PDT 24
Peak memory 203628 kb
Host smart-471ad44e-2028-4d98-b1c3-5eb11c2a433d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290232470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2290232470
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4063721424
Short name T1077
Test name
Test status
Simulation time 57442945 ps
CPU time 0.72 seconds
Started Aug 09 07:50:40 PM PDT 24
Finished Aug 09 07:50:40 PM PDT 24
Peak memory 203820 kb
Host smart-f97a113f-67fd-42bf-8ec9-9fd25107651b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063721424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4063721424
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.159156594
Short name T1025
Test name
Test status
Simulation time 21683870 ps
CPU time 0.7 seconds
Started Aug 09 07:50:34 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 203964 kb
Host smart-417eacbf-5197-4769-9226-25fb20ab4c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159156594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.159156594
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.67419136
Short name T1038
Test name
Test status
Simulation time 90903443 ps
CPU time 0.81 seconds
Started Aug 09 07:50:38 PM PDT 24
Finished Aug 09 07:50:39 PM PDT 24
Peak memory 203644 kb
Host smart-c1e59e83-a33c-48ba-a93b-b5a3c57ae747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67419136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.67419136
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3360583410
Short name T66
Test name
Test status
Simulation time 54536144 ps
CPU time 3.78 seconds
Started Aug 09 07:50:17 PM PDT 24
Finished Aug 09 07:50:21 PM PDT 24
Peak memory 217472 kb
Host smart-54a1ca87-b77a-4c76-9f72-02267bff52ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360583410 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3360583410
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2093750732
Short name T129
Test name
Test status
Simulation time 129224812 ps
CPU time 2.74 seconds
Started Aug 09 07:50:16 PM PDT 24
Finished Aug 09 07:50:19 PM PDT 24
Peak memory 215180 kb
Host smart-393894d8-389e-46d5-8993-5b415c72fc12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093750732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
093750732
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3027377876
Short name T1018
Test name
Test status
Simulation time 30587942 ps
CPU time 0.78 seconds
Started Aug 09 07:50:23 PM PDT 24
Finished Aug 09 07:50:24 PM PDT 24
Peak memory 203688 kb
Host smart-2df96e3b-679c-4732-bcf9-ded013f1bfd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027377876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
027377876
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3462990133
Short name T169
Test name
Test status
Simulation time 197841535 ps
CPU time 4.03 seconds
Started Aug 09 07:50:23 PM PDT 24
Finished Aug 09 07:50:27 PM PDT 24
Peak memory 215240 kb
Host smart-4acb857d-c5b9-45ff-ba14-c179a41c8618
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462990133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3462990133
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3024189122
Short name T105
Test name
Test status
Simulation time 140994927 ps
CPU time 3.51 seconds
Started Aug 09 07:50:22 PM PDT 24
Finished Aug 09 07:50:26 PM PDT 24
Peak memory 215168 kb
Host smart-632c2e6d-4fe5-4a7d-ab37-89317be57030
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024189122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
024189122
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3492547647
Short name T191
Test name
Test status
Simulation time 106093689 ps
CPU time 6.98 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:22 PM PDT 24
Peak memory 215224 kb
Host smart-c962f6fd-d7d2-426d-951f-5abcfc0bb9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492547647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3492547647
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3028346285
Short name T1080
Test name
Test status
Simulation time 239519955 ps
CPU time 3.36 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:19 PM PDT 24
Peak memory 217620 kb
Host smart-45bb2fa0-c125-4e29-ae29-2aeab336c79a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028346285 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3028346285
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3971651936
Short name T1089
Test name
Test status
Simulation time 155213087 ps
CPU time 1.33 seconds
Started Aug 09 07:50:16 PM PDT 24
Finished Aug 09 07:50:18 PM PDT 24
Peak memory 215180 kb
Host smart-43ee2444-19f2-49ed-b7b2-fd533eeea00b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971651936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
971651936
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1569637424
Short name T1092
Test name
Test status
Simulation time 123945485 ps
CPU time 0.78 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:16 PM PDT 24
Peak memory 203632 kb
Host smart-92a648e6-de86-4e12-ae1a-f3cf517c619d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569637424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
569637424
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3393740085
Short name T168
Test name
Test status
Simulation time 251363062 ps
CPU time 3.03 seconds
Started Aug 09 07:50:16 PM PDT 24
Finished Aug 09 07:50:19 PM PDT 24
Peak memory 215112 kb
Host smart-ccbbcdb6-4a97-4e2c-b907-ae308475335f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393740085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3393740085
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2964766574
Short name T1083
Test name
Test status
Simulation time 55599098 ps
CPU time 1.72 seconds
Started Aug 09 07:50:22 PM PDT 24
Finished Aug 09 07:50:24 PM PDT 24
Peak memory 215308 kb
Host smart-f8ab9fdd-4e05-49a6-aeed-e9474922cb7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964766574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
964766574
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.363003793
Short name T1032
Test name
Test status
Simulation time 25440303 ps
CPU time 1.65 seconds
Started Aug 09 07:50:22 PM PDT 24
Finished Aug 09 07:50:24 PM PDT 24
Peak memory 215080 kb
Host smart-2128c6e1-464a-4d0f-b44e-e02b9fd95332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363003793 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.363003793
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4270061571
Short name T1115
Test name
Test status
Simulation time 285320679 ps
CPU time 2.07 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:17 PM PDT 24
Peak memory 215136 kb
Host smart-b0e8dc58-b638-4ad0-9e2d-b957f98c1e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270061571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
270061571
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2410749130
Short name T1049
Test name
Test status
Simulation time 29770992 ps
CPU time 0.73 seconds
Started Aug 09 07:50:16 PM PDT 24
Finished Aug 09 07:50:17 PM PDT 24
Peak memory 203628 kb
Host smart-c94a39ca-5860-43cc-98c9-9e6f5fd83a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410749130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
410749130
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1949545162
Short name T167
Test name
Test status
Simulation time 133546056 ps
CPU time 3.06 seconds
Started Aug 09 07:50:18 PM PDT 24
Finished Aug 09 07:50:21 PM PDT 24
Peak memory 215192 kb
Host smart-238af763-8632-4bbf-a5e8-d1a19b64ea88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949545162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1949545162
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2217837238
Short name T109
Test name
Test status
Simulation time 149770677 ps
CPU time 4.27 seconds
Started Aug 09 07:50:16 PM PDT 24
Finished Aug 09 07:50:20 PM PDT 24
Peak memory 215316 kb
Host smart-4c0089b5-09ae-4cc6-ab7e-7bf255cf8806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217837238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
217837238
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.532239118
Short name T1088
Test name
Test status
Simulation time 345933537 ps
CPU time 7.45 seconds
Started Aug 09 07:50:16 PM PDT 24
Finished Aug 09 07:50:23 PM PDT 24
Peak memory 215604 kb
Host smart-d527c661-8156-4d60-b73d-f31349f2e66a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532239118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.532239118
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2944541081
Short name T1067
Test name
Test status
Simulation time 218895227 ps
CPU time 1.79 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:26 PM PDT 24
Peak memory 215284 kb
Host smart-af0ae2da-41bd-4911-98e1-848f5cc0e7dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944541081 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2944541081
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1086001684
Short name T1094
Test name
Test status
Simulation time 565425691 ps
CPU time 1.52 seconds
Started Aug 09 07:50:15 PM PDT 24
Finished Aug 09 07:50:17 PM PDT 24
Peak memory 206984 kb
Host smart-522fd95b-a696-4769-8c9a-812b0529afa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086001684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
086001684
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3545103474
Short name T1047
Test name
Test status
Simulation time 13097857 ps
CPU time 0.74 seconds
Started Aug 09 07:50:21 PM PDT 24
Finished Aug 09 07:50:22 PM PDT 24
Peak memory 203988 kb
Host smart-b26a90f1-7839-4b3b-a92f-51c1d8f80c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545103474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
545103474
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.617317282
Short name T1050
Test name
Test status
Simulation time 295418883 ps
CPU time 3.3 seconds
Started Aug 09 07:50:22 PM PDT 24
Finished Aug 09 07:50:25 PM PDT 24
Peak memory 215180 kb
Host smart-6fe0704c-7844-42f5-8521-60bca42b1e91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617317282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.617317282
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3549513188
Short name T1076
Test name
Test status
Simulation time 312702684 ps
CPU time 2.82 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:27 PM PDT 24
Peak memory 216436 kb
Host smart-01cb3c10-a181-43e2-89c0-04c6a95408a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549513188 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3549513188
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1023109647
Short name T1113
Test name
Test status
Simulation time 123932535 ps
CPU time 2.22 seconds
Started Aug 09 07:50:25 PM PDT 24
Finished Aug 09 07:50:28 PM PDT 24
Peak memory 215240 kb
Host smart-128ce685-c14c-4781-a67f-58381d907238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023109647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
023109647
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3075594674
Short name T1028
Test name
Test status
Simulation time 51492497 ps
CPU time 0.71 seconds
Started Aug 09 07:50:26 PM PDT 24
Finished Aug 09 07:50:26 PM PDT 24
Peak memory 203652 kb
Host smart-819e86bc-fd61-46c4-ba5d-b1f2c8782103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075594674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
075594674
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2026353504
Short name T151
Test name
Test status
Simulation time 342705379 ps
CPU time 3.55 seconds
Started Aug 09 07:50:28 PM PDT 24
Finished Aug 09 07:50:31 PM PDT 24
Peak memory 215052 kb
Host smart-2d5eb9db-4ad7-4de1-8a4e-da5ceb742328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026353504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2026353504
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3440295110
Short name T102
Test name
Test status
Simulation time 173869548 ps
CPU time 3.07 seconds
Started Aug 09 07:50:23 PM PDT 24
Finished Aug 09 07:50:26 PM PDT 24
Peak memory 215404 kb
Host smart-81a93ac5-e32a-42a5-b023-98e67e8778ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440295110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
440295110
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3839910113
Short name T185
Test name
Test status
Simulation time 3275078184 ps
CPU time 14.48 seconds
Started Aug 09 07:50:24 PM PDT 24
Finished Aug 09 07:50:39 PM PDT 24
Peak memory 215224 kb
Host smart-474cccae-7872-46f1-a9a9-10d06aa2718a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839910113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3839910113
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2245418726
Short name T424
Test name
Test status
Simulation time 14089885 ps
CPU time 0.72 seconds
Started Aug 09 07:54:16 PM PDT 24
Finished Aug 09 07:54:17 PM PDT 24
Peak memory 205256 kb
Host smart-d7360276-a40e-4053-b08f-7208636e0eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245418726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
245418726
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3425442965
Short name T697
Test name
Test status
Simulation time 21063076 ps
CPU time 0.77 seconds
Started Aug 09 07:54:00 PM PDT 24
Finished Aug 09 07:54:00 PM PDT 24
Peak memory 207344 kb
Host smart-dea63598-f02c-45be-a580-5c12653ec97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425442965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3425442965
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3854856845
Short name T197
Test name
Test status
Simulation time 44597133405 ps
CPU time 75.57 seconds
Started Aug 09 07:54:12 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 263552 kb
Host smart-f6bf91a6-e7ee-4bfc-8a85-68de4ecd51a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854856845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3854856845
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3402648362
Short name T721
Test name
Test status
Simulation time 39597584133 ps
CPU time 157.46 seconds
Started Aug 09 07:54:16 PM PDT 24
Finished Aug 09 07:56:54 PM PDT 24
Peak memory 256956 kb
Host smart-2168d608-13ff-4730-9429-cf0a8437d13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402648362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3402648362
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3631602499
Short name T235
Test name
Test status
Simulation time 1587964502 ps
CPU time 5.24 seconds
Started Aug 09 07:54:09 PM PDT 24
Finished Aug 09 07:54:14 PM PDT 24
Peak memory 234364 kb
Host smart-a0fff829-5589-478f-be97-15508e246b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631602499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3631602499
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1627221317
Short name T668
Test name
Test status
Simulation time 95994673 ps
CPU time 0.84 seconds
Started Aug 09 07:54:08 PM PDT 24
Finished Aug 09 07:54:09 PM PDT 24
Peak memory 216324 kb
Host smart-1e87f7a4-2ec8-4960-99a8-20542959c3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627221317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1627221317
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3402113403
Short name T454
Test name
Test status
Simulation time 276828219 ps
CPU time 2.53 seconds
Started Aug 09 07:54:06 PM PDT 24
Finished Aug 09 07:54:09 PM PDT 24
Peak memory 224176 kb
Host smart-003361dc-7719-49c0-b611-106655c02f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402113403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3402113403
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2532312889
Short name T272
Test name
Test status
Simulation time 6874798071 ps
CPU time 28.71 seconds
Started Aug 09 07:54:08 PM PDT 24
Finished Aug 09 07:54:37 PM PDT 24
Peak memory 233200 kb
Host smart-1e70a14c-b7c1-4ade-b5c2-035bd47d8848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532312889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2532312889
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3723613800
Short name T870
Test name
Test status
Simulation time 10414367915 ps
CPU time 6.44 seconds
Started Aug 09 07:54:05 PM PDT 24
Finished Aug 09 07:54:12 PM PDT 24
Peak memory 233160 kb
Host smart-bef17251-e241-46c4-954b-f31062a678f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723613800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3723613800
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1977320195
Short name T959
Test name
Test status
Simulation time 1228367447 ps
CPU time 9.12 seconds
Started Aug 09 07:54:11 PM PDT 24
Finished Aug 09 07:54:21 PM PDT 24
Peak memory 238960 kb
Host smart-90db72fb-6fb3-4162-b1f6-839948e1514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977320195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1977320195
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2836707765
Short name T606
Test name
Test status
Simulation time 205581819 ps
CPU time 5.68 seconds
Started Aug 09 07:54:18 PM PDT 24
Finished Aug 09 07:54:24 PM PDT 24
Peak memory 223544 kb
Host smart-6c4cfa1a-f4d7-449e-9e36-f3396352d5ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2836707765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2836707765
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3084931012
Short name T21
Test name
Test status
Simulation time 291600920 ps
CPU time 1.07 seconds
Started Aug 09 07:54:08 PM PDT 24
Finished Aug 09 07:54:09 PM PDT 24
Peak memory 207500 kb
Host smart-6e9a2b29-e935-422f-ae02-bf686b1a1606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084931012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3084931012
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2965304174
Short name T44
Test name
Test status
Simulation time 2945324233 ps
CPU time 7.52 seconds
Started Aug 09 07:54:03 PM PDT 24
Finished Aug 09 07:54:11 PM PDT 24
Peak memory 217012 kb
Host smart-fa61c98d-2e82-4166-9654-8c50f3b99fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965304174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2965304174
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4072765448
Short name T325
Test name
Test status
Simulation time 72541507 ps
CPU time 0.7 seconds
Started Aug 09 07:53:58 PM PDT 24
Finished Aug 09 07:53:59 PM PDT 24
Peak memory 206068 kb
Host smart-b64f8850-0012-4544-9be0-2ef0279824b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072765448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4072765448
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2299114172
Short name T489
Test name
Test status
Simulation time 36210571 ps
CPU time 0.68 seconds
Started Aug 09 07:54:18 PM PDT 24
Finished Aug 09 07:54:19 PM PDT 24
Peak memory 206028 kb
Host smart-8a24893f-5f9f-43cc-8eb0-ab371bcbf6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299114172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2299114172
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1582798053
Short name T482
Test name
Test status
Simulation time 153274010 ps
CPU time 0.92 seconds
Started Aug 09 07:54:00 PM PDT 24
Finished Aug 09 07:54:01 PM PDT 24
Peak memory 206332 kb
Host smart-681ce1ae-4c08-4ec1-93cc-4605a945e294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582798053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1582798053
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1324660792
Short name T246
Test name
Test status
Simulation time 14344034871 ps
CPU time 11.58 seconds
Started Aug 09 07:54:06 PM PDT 24
Finished Aug 09 07:54:18 PM PDT 24
Peak memory 224968 kb
Host smart-8282a836-2ac4-462d-838a-35c3fe4c9f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324660792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1324660792
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4134302943
Short name T471
Test name
Test status
Simulation time 13423243 ps
CPU time 0.7 seconds
Started Aug 09 07:54:18 PM PDT 24
Finished Aug 09 07:54:19 PM PDT 24
Peak memory 205856 kb
Host smart-8b83e04a-4f9b-489b-9b02-89c666553006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134302943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
134302943
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2556896196
Short name T460
Test name
Test status
Simulation time 146638618 ps
CPU time 2.24 seconds
Started Aug 09 07:54:19 PM PDT 24
Finished Aug 09 07:54:21 PM PDT 24
Peak memory 224832 kb
Host smart-001b9007-90e7-48d8-a9fb-5ba82386d9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556896196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2556896196
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2911551794
Short name T335
Test name
Test status
Simulation time 16780535 ps
CPU time 0.8 seconds
Started Aug 09 07:54:17 PM PDT 24
Finished Aug 09 07:54:18 PM PDT 24
Peak memory 206924 kb
Host smart-0a5e6950-8464-4855-9cfb-8dc7fca03d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911551794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2911551794
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2893751031
Short name T691
Test name
Test status
Simulation time 107439279473 ps
CPU time 340.72 seconds
Started Aug 09 07:54:17 PM PDT 24
Finished Aug 09 07:59:59 PM PDT 24
Peak memory 261824 kb
Host smart-0f533b9b-7dfc-43db-949d-849902a3efe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893751031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2893751031
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3102353535
Short name T871
Test name
Test status
Simulation time 1187760998 ps
CPU time 19.58 seconds
Started Aug 09 07:54:17 PM PDT 24
Finished Aug 09 07:54:37 PM PDT 24
Peak memory 219764 kb
Host smart-c01f1db2-129a-4dd6-822e-2724d5756e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102353535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3102353535
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3178354414
Short name T534
Test name
Test status
Simulation time 85556674661 ps
CPU time 287.39 seconds
Started Aug 09 07:54:24 PM PDT 24
Finished Aug 09 07:59:11 PM PDT 24
Peak memory 246204 kb
Host smart-8160cd0d-4553-4a56-bf3f-f484be708236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178354414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3178354414
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.327582434
Short name T974
Test name
Test status
Simulation time 15330521730 ps
CPU time 53.19 seconds
Started Aug 09 07:54:16 PM PDT 24
Finished Aug 09 07:55:10 PM PDT 24
Peak memory 249560 kb
Host smart-41690be1-69db-4ce6-a0e1-2302210c4608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327582434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
327582434
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3134089633
Short name T528
Test name
Test status
Simulation time 501396550 ps
CPU time 2.88 seconds
Started Aug 09 07:54:24 PM PDT 24
Finished Aug 09 07:54:27 PM PDT 24
Peak memory 224968 kb
Host smart-e7395c2d-4640-4e50-b17d-db00fd02324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134089633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3134089633
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3167807399
Short name T739
Test name
Test status
Simulation time 9971136531 ps
CPU time 11.41 seconds
Started Aug 09 07:54:14 PM PDT 24
Finished Aug 09 07:54:26 PM PDT 24
Peak memory 233036 kb
Host smart-76123696-c27e-4d2e-b6c2-b854323fcfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167807399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3167807399
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2144792621
Short name T924
Test name
Test status
Simulation time 4047086940 ps
CPU time 14.17 seconds
Started Aug 09 07:54:24 PM PDT 24
Finished Aug 09 07:54:38 PM PDT 24
Peak memory 238996 kb
Host smart-29e2d2ba-df0f-4ba4-b600-253f7b50bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144792621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2144792621
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2760968676
Short name T648
Test name
Test status
Simulation time 16088258876 ps
CPU time 16.12 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:46 PM PDT 24
Peak memory 240484 kb
Host smart-44e06e61-19bd-4fd4-9fc9-f0216c85504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760968676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2760968676
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1503511910
Short name T156
Test name
Test status
Simulation time 1137403919 ps
CPU time 7.21 seconds
Started Aug 09 07:54:17 PM PDT 24
Finished Aug 09 07:54:24 PM PDT 24
Peak memory 223184 kb
Host smart-f86a45d0-0c31-49e3-9c10-e807a637b6b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1503511910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1503511910
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2831539069
Short name T71
Test name
Test status
Simulation time 228278149 ps
CPU time 1.08 seconds
Started Aug 09 07:54:16 PM PDT 24
Finished Aug 09 07:54:18 PM PDT 24
Peak memory 236948 kb
Host smart-c7b221fe-f647-4c01-a5a6-9db3899c2963
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831539069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2831539069
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1859679304
Short name T930
Test name
Test status
Simulation time 153191237 ps
CPU time 0.95 seconds
Started Aug 09 07:54:18 PM PDT 24
Finished Aug 09 07:54:19 PM PDT 24
Peak memory 206992 kb
Host smart-ab915b11-128b-499d-b697-37fdb8a38f12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859679304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1859679304
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3585580631
Short name T781
Test name
Test status
Simulation time 4817928911 ps
CPU time 25.92 seconds
Started Aug 09 07:54:24 PM PDT 24
Finished Aug 09 07:54:50 PM PDT 24
Peak memory 216620 kb
Host smart-7124fc20-b3f8-495e-ae1c-fd4ac24c6473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585580631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3585580631
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2165623122
Short name T708
Test name
Test status
Simulation time 260791684 ps
CPU time 3.12 seconds
Started Aug 09 07:54:21 PM PDT 24
Finished Aug 09 07:54:25 PM PDT 24
Peak memory 216652 kb
Host smart-0d0ce290-6590-47cb-8381-f2caa0cdff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165623122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2165623122
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3092332382
Short name T912
Test name
Test status
Simulation time 669158464 ps
CPU time 1.48 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 07:54:30 PM PDT 24
Peak memory 208368 kb
Host smart-5ba40a6a-abc5-4c0b-83d4-2256df6b5a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092332382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3092332382
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.858229678
Short name T841
Test name
Test status
Simulation time 164234213 ps
CPU time 0.92 seconds
Started Aug 09 07:54:16 PM PDT 24
Finished Aug 09 07:54:18 PM PDT 24
Peak memory 206352 kb
Host smart-7a7d9573-bcf9-414b-bff3-d99c23b31817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858229678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.858229678
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.501262884
Short name T380
Test name
Test status
Simulation time 300244292 ps
CPU time 5.74 seconds
Started Aug 09 07:54:16 PM PDT 24
Finished Aug 09 07:54:22 PM PDT 24
Peak memory 233096 kb
Host smart-ea4e8435-a74d-42e5-940b-90c9fdc16fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501262884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.501262884
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1127983798
Short name T358
Test name
Test status
Simulation time 14872651 ps
CPU time 0.73 seconds
Started Aug 09 07:54:42 PM PDT 24
Finished Aug 09 07:54:43 PM PDT 24
Peak memory 205260 kb
Host smart-c917b23b-3f3f-4563-acd6-a22b678f100d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127983798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1127983798
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1002411915
Short name T377
Test name
Test status
Simulation time 2558717166 ps
CPU time 11.49 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 233116 kb
Host smart-73dea9ca-518b-4c6b-95c7-9368ed7b3fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002411915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1002411915
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3743235445
Short name T955
Test name
Test status
Simulation time 15086602 ps
CPU time 0.77 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:54:45 PM PDT 24
Peak memory 206916 kb
Host smart-7628e777-9f01-4d5b-a536-1bd1677c76c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743235445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3743235445
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4281294002
Short name T892
Test name
Test status
Simulation time 85429566251 ps
CPU time 323.61 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 08:00:09 PM PDT 24
Peak memory 258876 kb
Host smart-2eea3015-60f4-4d16-a1ec-0b682bf69c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281294002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4281294002
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.212151771
Short name T50
Test name
Test status
Simulation time 45040757620 ps
CPU time 391.76 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 08:01:18 PM PDT 24
Peak memory 255800 kb
Host smart-f75e1e71-fc41-4cd5-a337-b42286202970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212151771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.212151771
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1190131968
Short name T283
Test name
Test status
Simulation time 28849358231 ps
CPU time 267.13 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:59:12 PM PDT 24
Peak memory 249728 kb
Host smart-08ed41a9-abb1-4e85-9d0b-0485fb4f9f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190131968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1190131968
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1052011972
Short name T78
Test name
Test status
Simulation time 3636602345 ps
CPU time 55.73 seconds
Started Aug 09 07:54:42 PM PDT 24
Finished Aug 09 07:55:37 PM PDT 24
Peak memory 249624 kb
Host smart-3501878f-a729-4cd3-a8ce-33852a7819a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052011972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1052011972
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3895970469
Short name T529
Test name
Test status
Simulation time 6183546742 ps
CPU time 55.72 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:55:42 PM PDT 24
Peak memory 249544 kb
Host smart-fd8d5e13-817b-4594-84fa-1c7a9419d391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895970469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3895970469
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2659213174
Short name T486
Test name
Test status
Simulation time 2203363039 ps
CPU time 11.49 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:54:52 PM PDT 24
Peak memory 225044 kb
Host smart-139365b9-8575-4fcb-b136-f5f31a24c028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659213174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2659213174
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2194026684
Short name T834
Test name
Test status
Simulation time 1511292922 ps
CPU time 11.03 seconds
Started Aug 09 07:54:42 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 233108 kb
Host smart-60bd7001-5094-4845-b3e3-d8fe7da5e12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194026684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2194026684
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3724861239
Short name T261
Test name
Test status
Simulation time 2243260789 ps
CPU time 7.75 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:54:53 PM PDT 24
Peak memory 233112 kb
Host smart-c9cb5414-e967-46bc-acd4-beee7bc898f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724861239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3724861239
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3813715562
Short name T499
Test name
Test status
Simulation time 6180612648 ps
CPU time 14.73 seconds
Started Aug 09 07:54:43 PM PDT 24
Finished Aug 09 07:54:58 PM PDT 24
Peak memory 233184 kb
Host smart-377a1f21-4720-4862-aca5-e4df4b1822f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813715562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3813715562
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3361620472
Short name T558
Test name
Test status
Simulation time 1000216847 ps
CPU time 8.51 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 222812 kb
Host smart-3e178763-54e2-4ad1-91ad-ca67bb6e42df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3361620472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3361620472
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1690573097
Short name T20
Test name
Test status
Simulation time 68565171772 ps
CPU time 313.87 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:59:59 PM PDT 24
Peak memory 265828 kb
Host smart-69322601-2edd-42e9-a523-fdf58a4a3dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690573097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1690573097
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3687273352
Short name T810
Test name
Test status
Simulation time 2286300792 ps
CPU time 16.76 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:55:02 PM PDT 24
Peak memory 216776 kb
Host smart-b3b21059-921d-4e0c-ac2a-ab7fa7d19062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687273352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3687273352
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.823478658
Short name T464
Test name
Test status
Simulation time 2454141803 ps
CPU time 7.51 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:54:48 PM PDT 24
Peak memory 216912 kb
Host smart-a4295c0e-9953-419f-ba51-2fbd99410ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823478658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.823478658
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1865660081
Short name T625
Test name
Test status
Simulation time 107591353 ps
CPU time 1.28 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:54:50 PM PDT 24
Peak memory 216708 kb
Host smart-5604c6e3-2910-43ef-a9f5-fd517527ab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865660081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1865660081
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2353062736
Short name T362
Test name
Test status
Simulation time 316961538 ps
CPU time 1.05 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:54:41 PM PDT 24
Peak memory 206316 kb
Host smart-7ff3e1d7-5e1c-4a4b-9f5d-3d65547d39ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353062736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2353062736
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1557798379
Short name T713
Test name
Test status
Simulation time 353070558 ps
CPU time 5.06 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:54:49 PM PDT 24
Peak memory 233060 kb
Host smart-c92b912b-95c4-4ffb-830f-451d7f55c44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557798379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1557798379
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2968255569
Short name T339
Test name
Test status
Simulation time 16287030 ps
CPU time 0.74 seconds
Started Aug 09 07:54:50 PM PDT 24
Finished Aug 09 07:54:51 PM PDT 24
Peak memory 205240 kb
Host smart-cdd904ef-b385-439e-9e91-e0c1602f9b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968255569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2968255569
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.499407267
Short name T254
Test name
Test status
Simulation time 280158393 ps
CPU time 5.82 seconds
Started Aug 09 07:54:54 PM PDT 24
Finished Aug 09 07:55:00 PM PDT 24
Peak memory 233036 kb
Host smart-e67af017-a4bf-4844-89cd-5c84acceaad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499407267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.499407267
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1312559913
Short name T632
Test name
Test status
Simulation time 34759669 ps
CPU time 0.82 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 206980 kb
Host smart-fba67b1f-51be-4eaf-bba5-11c704790ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312559913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1312559913
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4096668630
Short name T219
Test name
Test status
Simulation time 91014696572 ps
CPU time 152.01 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:57:18 PM PDT 24
Peak memory 249564 kb
Host smart-ca0b4149-2b5f-494c-ab75-8bd85f015fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096668630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4096668630
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3031611598
Short name T593
Test name
Test status
Simulation time 73709018814 ps
CPU time 268.66 seconds
Started Aug 09 07:54:50 PM PDT 24
Finished Aug 09 07:59:19 PM PDT 24
Peak memory 254676 kb
Host smart-17ca00a1-5ac2-4366-8848-59087500eaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031611598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3031611598
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1184135898
Short name T412
Test name
Test status
Simulation time 32699601518 ps
CPU time 277.52 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:59:31 PM PDT 24
Peak memory 257044 kb
Host smart-529694e6-839e-4f09-bb5e-a458385e7924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184135898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1184135898
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1016932661
Short name T154
Test name
Test status
Simulation time 44284190742 ps
CPU time 25.78 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:55:12 PM PDT 24
Peak memory 233196 kb
Host smart-91253ed9-4be0-4106-b04b-3b500d67fce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016932661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1016932661
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2375437500
Short name T1002
Test name
Test status
Simulation time 170776403784 ps
CPU time 284.58 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:59:31 PM PDT 24
Peak memory 252460 kb
Host smart-a4bf7c87-3fb8-456c-9171-3b19f5a32a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375437500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2375437500
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1157544532
Short name T609
Test name
Test status
Simulation time 759359362 ps
CPU time 2.95 seconds
Started Aug 09 07:54:53 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 224956 kb
Host smart-3e7c8874-8df7-46cc-ab6e-a05f59b925c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157544532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1157544532
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3021474587
Short name T23
Test name
Test status
Simulation time 42219471 ps
CPU time 2.46 seconds
Started Aug 09 07:54:54 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 232776 kb
Host smart-d1e90433-56cd-4ab5-b3e8-c3377367a257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021474587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3021474587
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3816772111
Short name T672
Test name
Test status
Simulation time 2082478330 ps
CPU time 5.22 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:54:45 PM PDT 24
Peak memory 224916 kb
Host smart-8cf4c78d-782e-4251-a566-0f2fba7ab09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816772111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3816772111
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1124882729
Short name T453
Test name
Test status
Simulation time 437908861 ps
CPU time 2.69 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:41 PM PDT 24
Peak memory 224912 kb
Host smart-daca1bca-9456-4b9d-a28d-733cd5887383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124882729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1124882729
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1618075797
Short name T381
Test name
Test status
Simulation time 5044508555 ps
CPU time 14.5 seconds
Started Aug 09 07:54:50 PM PDT 24
Finished Aug 09 07:55:05 PM PDT 24
Peak memory 222516 kb
Host smart-002f9954-ba17-4ef1-be3c-26f098b62aa4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1618075797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1618075797
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2335089536
Short name T673
Test name
Test status
Simulation time 23175644077 ps
CPU time 209.9 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:58:19 PM PDT 24
Peak memory 249428 kb
Host smart-98c47827-a975-49fd-996c-b4c35d7fd8fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335089536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2335089536
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3240491055
Short name T794
Test name
Test status
Simulation time 1040029157 ps
CPU time 9.84 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:54:53 PM PDT 24
Peak memory 216852 kb
Host smart-22381a96-c94a-442a-a9c3-1362e56591b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240491055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3240491055
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3717356388
Short name T1015
Test name
Test status
Simulation time 86239875 ps
CPU time 1.14 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 208204 kb
Host smart-81578750-e034-4ef0-8bee-cac2018f6b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717356388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3717356388
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3489492111
Short name T679
Test name
Test status
Simulation time 152027984 ps
CPU time 0.79 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:54:45 PM PDT 24
Peak memory 206340 kb
Host smart-dc0e5b96-542b-41b8-bab7-ee6eaca4d4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489492111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3489492111
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3636562305
Short name T562
Test name
Test status
Simulation time 1078033496 ps
CPU time 7.06 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 232980 kb
Host smart-e7661f6f-031f-42ba-8b49-fa74f1d27266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636562305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3636562305
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1523621982
Short name T807
Test name
Test status
Simulation time 15371597 ps
CPU time 0.74 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:54:50 PM PDT 24
Peak memory 205844 kb
Host smart-6c5499a1-44b0-4556-a51c-1700656d0e1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523621982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1523621982
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.4182630961
Short name T83
Test name
Test status
Simulation time 396191064 ps
CPU time 6.43 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:54:50 PM PDT 24
Peak memory 233028 kb
Host smart-90eab99d-718d-4aee-a881-5385edb3aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182630961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4182630961
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.349956929
Short name T996
Test name
Test status
Simulation time 24362172 ps
CPU time 0.74 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:54:48 PM PDT 24
Peak memory 206836 kb
Host smart-f18e1bdc-364f-4fe7-8adc-1927633f0773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349956929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.349956929
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.239155167
Short name T787
Test name
Test status
Simulation time 27789741894 ps
CPU time 52.07 seconds
Started Aug 09 07:54:43 PM PDT 24
Finished Aug 09 07:55:35 PM PDT 24
Peak memory 249576 kb
Host smart-e18d8541-b40a-42c5-899e-19e03af49b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239155167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.239155167
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2012653295
Short name T732
Test name
Test status
Simulation time 7707999811 ps
CPU time 99.55 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:56:28 PM PDT 24
Peak memory 255232 kb
Host smart-8b6741da-28f4-4fc0-a3c4-a5eb30894009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012653295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2012653295
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.216672749
Short name T688
Test name
Test status
Simulation time 1571393772 ps
CPU time 6.27 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:54:53 PM PDT 24
Peak memory 233156 kb
Host smart-b0d9e23f-5ea5-4904-a703-5b8c6bcd64de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216672749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.216672749
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.283271059
Short name T57
Test name
Test status
Simulation time 219637800752 ps
CPU time 195.65 seconds
Started Aug 09 07:54:43 PM PDT 24
Finished Aug 09 07:57:59 PM PDT 24
Peak memory 254212 kb
Host smart-715d8e91-4dcf-4506-9e9c-7a1b940e6cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283271059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.283271059
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2199325348
Short name T432
Test name
Test status
Simulation time 281052468 ps
CPU time 3.12 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 233152 kb
Host smart-4abce0e3-0c86-4d23-b97c-cdda91907e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199325348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2199325348
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3097032650
Short name T886
Test name
Test status
Simulation time 300358489 ps
CPU time 3.93 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 233124 kb
Host smart-9c465628-5e9d-4117-9ca0-894d0fc93a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097032650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3097032650
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.66365499
Short name T270
Test name
Test status
Simulation time 865905489 ps
CPU time 7.24 seconds
Started Aug 09 07:54:48 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 224896 kb
Host smart-3e7c12e4-821b-459a-b61b-99c9b8556329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66365499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.66365499
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.526733458
Short name T546
Test name
Test status
Simulation time 1301138137 ps
CPU time 4.89 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:52 PM PDT 24
Peak memory 219816 kb
Host smart-012c04e4-54c1-40f0-8f88-fd8311d80ae1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=526733458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.526733458
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1223925695
Short name T171
Test name
Test status
Simulation time 124566981521 ps
CPU time 243.26 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:58:50 PM PDT 24
Peak memory 257816 kb
Host smart-46dc93d3-a1bc-4691-87b7-880ed5325ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223925695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1223925695
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1364134619
Short name T738
Test name
Test status
Simulation time 616836272 ps
CPU time 11.55 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:55:03 PM PDT 24
Peak memory 216600 kb
Host smart-35e1a0f0-6bb9-47f9-b033-4cedfb07f64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364134619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1364134619
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1873870665
Short name T141
Test name
Test status
Simulation time 1184404092 ps
CPU time 1.48 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:54:49 PM PDT 24
Peak memory 207316 kb
Host smart-71555ff9-145d-47c8-95dc-5015f37ae691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873870665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1873870665
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3786785713
Short name T856
Test name
Test status
Simulation time 16732575 ps
CPU time 0.78 seconds
Started Aug 09 07:54:51 PM PDT 24
Finished Aug 09 07:54:52 PM PDT 24
Peak memory 206344 kb
Host smart-55ca9d35-b677-45e6-83b6-a6d0edd16ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786785713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3786785713
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3214519210
Short name T478
Test name
Test status
Simulation time 12428501 ps
CPU time 0.72 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:54:53 PM PDT 24
Peak memory 205972 kb
Host smart-5a041c8e-bcd7-4524-a8ff-99b7699094d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214519210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3214519210
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2525510400
Short name T527
Test name
Test status
Simulation time 153872679 ps
CPU time 4.7 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:54:52 PM PDT 24
Peak memory 233108 kb
Host smart-63688d86-a2eb-4eb8-9268-fd9b1871361e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525510400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2525510400
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1314968495
Short name T819
Test name
Test status
Simulation time 12476253 ps
CPU time 0.72 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:54:41 PM PDT 24
Peak memory 205208 kb
Host smart-bb160554-ba8b-4eaa-b9c8-e4d066d4508a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314968495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1314968495
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3686715020
Short name T506
Test name
Test status
Simulation time 3222721376 ps
CPU time 11.81 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:58 PM PDT 24
Peak memory 233136 kb
Host smart-e71ad410-8145-44bc-b765-0a5750ee808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686715020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3686715020
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1478389254
Short name T569
Test name
Test status
Simulation time 35820298 ps
CPU time 0.76 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:54:46 PM PDT 24
Peak memory 207324 kb
Host smart-88c858bc-53ca-4615-a510-8bec177f88ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478389254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1478389254
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1148039429
Short name T634
Test name
Test status
Simulation time 41308497571 ps
CPU time 108.95 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:56:34 PM PDT 24
Peak memory 252084 kb
Host smart-7771f50b-9cd5-494f-83da-d8fe48f1ba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148039429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1148039429
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.387326438
Short name T286
Test name
Test status
Simulation time 2573520352 ps
CPU time 59.95 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:55:44 PM PDT 24
Peak memory 272836 kb
Host smart-31cb16b1-8712-416b-94d8-868994caed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387326438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.387326438
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1474427580
Short name T159
Test name
Test status
Simulation time 1757063998 ps
CPU time 14.34 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:55:01 PM PDT 24
Peak memory 241284 kb
Host smart-f7739b50-e9ec-4e99-b47c-8e18a422c2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474427580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1474427580
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.566342216
Short name T257
Test name
Test status
Simulation time 9051154466 ps
CPU time 113.51 seconds
Started Aug 09 07:54:51 PM PDT 24
Finished Aug 09 07:56:44 PM PDT 24
Peak memory 265400 kb
Host smart-88f8c006-235c-455a-91c0-507fda2926e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566342216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.566342216
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2512309688
Short name T76
Test name
Test status
Simulation time 1925319520 ps
CPU time 11.98 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:58 PM PDT 24
Peak memory 233076 kb
Host smart-4434a44e-6d28-43e8-b31f-1ced5e782800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512309688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2512309688
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3004784408
Short name T438
Test name
Test status
Simulation time 254016095 ps
CPU time 4.41 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:50 PM PDT 24
Peak memory 224904 kb
Host smart-b8662a1d-f0da-4a35-bee6-19fdd06b095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004784408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3004784408
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3062926719
Short name T354
Test name
Test status
Simulation time 530146262 ps
CPU time 3.88 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:54:48 PM PDT 24
Peak memory 233044 kb
Host smart-e27e3037-8cee-4ade-acc8-72dc2e50720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062926719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3062926719
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2968683909
Short name T997
Test name
Test status
Simulation time 379595701 ps
CPU time 3.4 seconds
Started Aug 09 07:54:39 PM PDT 24
Finished Aug 09 07:54:43 PM PDT 24
Peak memory 233144 kb
Host smart-1eaf6802-4ace-4e86-aa62-833044f74af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968683909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2968683909
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.316765091
Short name T157
Test name
Test status
Simulation time 425093203 ps
CPU time 4.22 seconds
Started Aug 09 07:54:43 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 221000 kb
Host smart-9adf4cc5-6c14-49de-a88b-76d8364ff5ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=316765091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.316765091
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1399445527
Short name T913
Test name
Test status
Simulation time 10668601734 ps
CPU time 18.96 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:57 PM PDT 24
Peak memory 216744 kb
Host smart-d582fbba-68ac-49b0-bb52-c4b830d52bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399445527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1399445527
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1964047896
Short name T949
Test name
Test status
Simulation time 8467266387 ps
CPU time 6.46 seconds
Started Aug 09 07:54:43 PM PDT 24
Finished Aug 09 07:54:50 PM PDT 24
Peak memory 216600 kb
Host smart-2ec2376e-6b28-478c-ae28-e449b74d5dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964047896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1964047896
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2446063300
Short name T989
Test name
Test status
Simulation time 24823346 ps
CPU time 0.69 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:54:51 PM PDT 24
Peak memory 206016 kb
Host smart-139463e7-3041-47c3-bc4d-4a9e7ca62e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446063300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2446063300
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1196511487
Short name T409
Test name
Test status
Simulation time 35729899 ps
CPU time 0.69 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:54:46 PM PDT 24
Peak memory 206352 kb
Host smart-9f6f6dd9-ca99-4132-9da5-59d423dfc8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196511487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1196511487
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.43056207
Short name T723
Test name
Test status
Simulation time 1319301176 ps
CPU time 5.91 seconds
Started Aug 09 07:54:45 PM PDT 24
Finished Aug 09 07:54:51 PM PDT 24
Peak memory 233084 kb
Host smart-7495b01e-c301-45be-abee-26f73defa59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43056207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.43056207
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2301291944
Short name T361
Test name
Test status
Simulation time 54792659 ps
CPU time 0.74 seconds
Started Aug 09 07:54:48 PM PDT 24
Finished Aug 09 07:54:49 PM PDT 24
Peak memory 205852 kb
Host smart-79186a33-2bb0-439f-ae4b-3cba0e37f3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301291944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2301291944
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.395936809
Short name T602
Test name
Test status
Simulation time 193544014 ps
CPU time 2.54 seconds
Started Aug 09 07:54:54 PM PDT 24
Finished Aug 09 07:54:57 PM PDT 24
Peak memory 233016 kb
Host smart-1d1709e2-c6a6-43f2-ab59-7f6821047054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395936809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.395936809
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2591340201
Short name T560
Test name
Test status
Simulation time 56238908 ps
CPU time 0.78 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:54:41 PM PDT 24
Peak memory 205956 kb
Host smart-1af85546-df9a-4250-9dd3-6bbe900eb5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591340201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2591340201
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.424350216
Short name T493
Test name
Test status
Simulation time 736527706 ps
CPU time 3.71 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:54:51 PM PDT 24
Peak memory 224832 kb
Host smart-e64042c4-8c41-4d7e-a9e8-a1295fc775d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424350216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.424350216
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2704694051
Short name T314
Test name
Test status
Simulation time 12142446582 ps
CPU time 47.79 seconds
Started Aug 09 07:54:51 PM PDT 24
Finished Aug 09 07:55:39 PM PDT 24
Peak memory 241440 kb
Host smart-a3c01d47-a8b9-4876-a7de-48a7a6dd6152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704694051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2704694051
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3139887228
Short name T826
Test name
Test status
Simulation time 77170040173 ps
CPU time 142.47 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:57:10 PM PDT 24
Peak memory 249508 kb
Host smart-9772a364-8619-4f16-9853-cc2498d953d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139887228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3139887228
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4018995388
Short name T802
Test name
Test status
Simulation time 2500242547 ps
CPU time 39.67 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:55:31 PM PDT 24
Peak memory 233168 kb
Host smart-b80982df-2e0b-4c07-b78c-3b6d19ba5665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018995388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4018995388
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2357171522
Short name T852
Test name
Test status
Simulation time 14490575670 ps
CPU time 109.74 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:56:37 PM PDT 24
Peak memory 249452 kb
Host smart-5ffc980c-e9ce-4aa4-889c-eb38a35e36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357171522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2357171522
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1946499111
Short name T175
Test name
Test status
Simulation time 6194271194 ps
CPU time 23.85 seconds
Started Aug 09 07:54:50 PM PDT 24
Finished Aug 09 07:55:14 PM PDT 24
Peak memory 219296 kb
Host smart-aa9db414-d412-462f-ab2c-9eaa66250875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946499111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1946499111
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1479944205
Short name T459
Test name
Test status
Simulation time 200901897 ps
CPU time 5.13 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 232964 kb
Host smart-2194b999-ec36-4478-9ed7-7ce1bea0ae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479944205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1479944205
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2419602290
Short name T590
Test name
Test status
Simulation time 2613431163 ps
CPU time 4.11 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:54:51 PM PDT 24
Peak memory 224912 kb
Host smart-dc331106-cada-471e-8cf9-cec24e6ca464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419602290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2419602290
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.749956226
Short name T398
Test name
Test status
Simulation time 26620863797 ps
CPU time 23.7 seconds
Started Aug 09 07:54:56 PM PDT 24
Finished Aug 09 07:55:20 PM PDT 24
Peak memory 233140 kb
Host smart-7bac00b0-f4de-415c-8841-b6e88ed86a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749956226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.749956226
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3796175866
Short name T789
Test name
Test status
Simulation time 496703116 ps
CPU time 8.03 seconds
Started Aug 09 07:54:50 PM PDT 24
Finished Aug 09 07:54:59 PM PDT 24
Peak memory 220200 kb
Host smart-143de1a2-90d9-4407-a80a-ec3adb78d2c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3796175866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3796175866
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3879605345
Short name T624
Test name
Test status
Simulation time 19045692782 ps
CPU time 123.51 seconds
Started Aug 09 07:54:51 PM PDT 24
Finished Aug 09 07:56:54 PM PDT 24
Peak memory 239784 kb
Host smart-a28da1ff-f711-4ced-877f-cdde43e6bd9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879605345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3879605345
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2558011563
Short name T890
Test name
Test status
Simulation time 17721606211 ps
CPU time 32.43 seconds
Started Aug 09 07:54:50 PM PDT 24
Finished Aug 09 07:55:23 PM PDT 24
Peak memory 220808 kb
Host smart-c1d4e84d-c16d-4cfb-8cc6-aee2ad7d30df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558011563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2558011563
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2412218820
Short name T669
Test name
Test status
Simulation time 1565923691 ps
CPU time 8.09 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:55 PM PDT 24
Peak memory 216632 kb
Host smart-a5e01b5e-c7df-4e6c-a575-e14f944ad718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412218820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2412218820
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1958079551
Short name T979
Test name
Test status
Simulation time 123540077 ps
CPU time 1.13 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:48 PM PDT 24
Peak memory 208212 kb
Host smart-7186afd9-3863-4675-81a4-5da853fd1f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958079551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1958079551
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2962014071
Short name T336
Test name
Test status
Simulation time 18715413 ps
CPU time 0.72 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 206344 kb
Host smart-7da5fa5c-1b16-4a16-bf64-fe6f927cfe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962014071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2962014071
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1060943391
Short name T243
Test name
Test status
Simulation time 33946691572 ps
CPU time 21.77 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:55:11 PM PDT 24
Peak memory 225008 kb
Host smart-fda06c8d-f8f5-44b4-b0f1-7e957ccbda85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060943391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1060943391
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3701624641
Short name T345
Test name
Test status
Simulation time 36282198 ps
CPU time 0.72 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:54:53 PM PDT 24
Peak memory 205788 kb
Host smart-d077cad6-e2a1-4881-aba1-6f6046bc176b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701624641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3701624641
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1193782347
Short name T643
Test name
Test status
Simulation time 1031515791 ps
CPU time 5.9 seconds
Started Aug 09 07:54:48 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 224836 kb
Host smart-acb712a5-3a08-4ec6-9c1d-88834954bd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193782347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1193782347
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3906383262
Short name T393
Test name
Test status
Simulation time 25985518 ps
CPU time 0.78 seconds
Started Aug 09 07:54:53 PM PDT 24
Finished Aug 09 07:54:53 PM PDT 24
Peak memory 204744 kb
Host smart-e1fc74a8-3dd8-4e04-b0d1-2b210657a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906383262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3906383262
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2993241701
Short name T948
Test name
Test status
Simulation time 134030993927 ps
CPU time 120.29 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:56:52 PM PDT 24
Peak memory 232376 kb
Host smart-6ca126ff-8890-4a03-9b25-309d6757ac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993241701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2993241701
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.273957594
Short name T47
Test name
Test status
Simulation time 116728938179 ps
CPU time 268.17 seconds
Started Aug 09 07:55:06 PM PDT 24
Finished Aug 09 07:59:34 PM PDT 24
Peak memory 253780 kb
Host smart-95443b45-b571-48ea-a413-c6339d852c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273957594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.273957594
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3164596412
Short name T278
Test name
Test status
Simulation time 4898954343 ps
CPU time 24.04 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:55:16 PM PDT 24
Peak memory 233252 kb
Host smart-80929e21-34d8-4735-8ab3-53fad3ec23b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164596412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3164596412
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1303984684
Short name T303
Test name
Test status
Simulation time 777694891 ps
CPU time 13.56 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:55:05 PM PDT 24
Peak memory 224916 kb
Host smart-cdf42bfd-d2d0-4a9b-a973-5934c07c0bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303984684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1303984684
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1173603568
Short name T266
Test name
Test status
Simulation time 57785627696 ps
CPU time 86.88 seconds
Started Aug 09 07:55:04 PM PDT 24
Finished Aug 09 07:56:31 PM PDT 24
Peak memory 254496 kb
Host smart-ca887104-d2b6-4e26-963c-08ebd417c5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173603568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1173603568
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2883959194
Short name T488
Test name
Test status
Simulation time 30023836 ps
CPU time 1.99 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:54:49 PM PDT 24
Peak memory 224224 kb
Host smart-640a39ad-b3b8-4dbb-ab9b-572df519aeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883959194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2883959194
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.78417222
Short name T566
Test name
Test status
Simulation time 4785517847 ps
CPU time 20.71 seconds
Started Aug 09 07:54:48 PM PDT 24
Finished Aug 09 07:55:09 PM PDT 24
Peak memory 233176 kb
Host smart-207715e7-5553-4469-8c9c-256ceab6636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78417222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.78417222
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1072753499
Short name T287
Test name
Test status
Simulation time 415373214 ps
CPU time 6.57 seconds
Started Aug 09 07:54:50 PM PDT 24
Finished Aug 09 07:54:57 PM PDT 24
Peak memory 233140 kb
Host smart-2d802dac-4790-40bc-b5c3-c80427cfb558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072753499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1072753499
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1220998736
Short name T681
Test name
Test status
Simulation time 376727849 ps
CPU time 3.21 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:55:14 PM PDT 24
Peak memory 233080 kb
Host smart-15eed11f-d745-4c90-8244-b675e00c4c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220998736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1220998736
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2162227731
Short name T513
Test name
Test status
Simulation time 2050025944 ps
CPU time 7.39 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 223140 kb
Host smart-a4b155df-8d68-4531-becf-655d4e4e3762
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2162227731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2162227731
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.885422922
Short name T775
Test name
Test status
Simulation time 683720540 ps
CPU time 5.34 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:55:15 PM PDT 24
Peak memory 216732 kb
Host smart-65403330-0106-42d7-9558-57a149abb9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885422922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.885422922
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1747425614
Short name T898
Test name
Test status
Simulation time 790238574 ps
CPU time 5.97 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 216596 kb
Host smart-6aa1f228-b543-4670-922b-504363937e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747425614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1747425614
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3872120891
Short name T82
Test name
Test status
Simulation time 123121675 ps
CPU time 2.48 seconds
Started Aug 09 07:54:47 PM PDT 24
Finished Aug 09 07:54:49 PM PDT 24
Peak memory 216676 kb
Host smart-145eb6ea-3dc7-449a-a585-3f875e8cd2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872120891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3872120891
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.119914131
Short name T640
Test name
Test status
Simulation time 42218597 ps
CPU time 0.81 seconds
Started Aug 09 07:54:53 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 206324 kb
Host smart-51d48da8-0d23-4f29-8a25-8e4aecd77cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119914131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.119914131
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.699930106
Short name T428
Test name
Test status
Simulation time 405459270 ps
CPU time 3.38 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:54:53 PM PDT 24
Peak memory 218856 kb
Host smart-4538b6fa-62d8-4718-9504-f54c3e16295a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699930106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.699930106
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.447393408
Short name T525
Test name
Test status
Simulation time 40016990 ps
CPU time 0.74 seconds
Started Aug 09 07:54:54 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 205848 kb
Host smart-db24ec6e-99cb-4ede-801d-c896b67672d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447393408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.447393408
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2217939099
Short name T687
Test name
Test status
Simulation time 318393571 ps
CPU time 4.49 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:54:57 PM PDT 24
Peak memory 233108 kb
Host smart-bede1ef1-5475-4041-8c75-9baf832623e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217939099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2217939099
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3169511279
Short name T853
Test name
Test status
Simulation time 119303515 ps
CPU time 0.87 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:55:11 PM PDT 24
Peak memory 206976 kb
Host smart-608150dd-a48c-4dd3-8f5a-27798dbc8092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169511279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3169511279
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4272859667
Short name T549
Test name
Test status
Simulation time 7582330335 ps
CPU time 56.36 seconds
Started Aug 09 07:55:04 PM PDT 24
Finished Aug 09 07:56:01 PM PDT 24
Peak memory 257180 kb
Host smart-a6107b9b-d5a1-4f47-b5a5-0224c6ec2f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272859667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4272859667
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.480135316
Short name T507
Test name
Test status
Simulation time 2652358755 ps
CPU time 8.58 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:55:01 PM PDT 24
Peak memory 231976 kb
Host smart-bfce49c5-6d5d-49d5-8ea1-9d3d6695d973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480135316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.480135316
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2672617836
Short name T542
Test name
Test status
Simulation time 32872103911 ps
CPU time 90.73 seconds
Started Aug 09 07:54:46 PM PDT 24
Finished Aug 09 07:56:16 PM PDT 24
Peak memory 256388 kb
Host smart-ef9685d7-13b1-4f18-90a3-986b6e07119c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672617836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2672617836
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3832500083
Short name T302
Test name
Test status
Simulation time 11173803616 ps
CPU time 45.35 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:55:56 PM PDT 24
Peak memory 238272 kb
Host smart-0c0d6bf1-d6ea-4e1d-81dd-446a653ec964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832500083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3832500083
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.453093988
Short name T215
Test name
Test status
Simulation time 2997873945 ps
CPU time 8.52 seconds
Started Aug 09 07:54:48 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 233228 kb
Host smart-0ed72185-a3fc-492a-a359-2747d16c08d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453093988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.453093988
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3429209890
Short name T355
Test name
Test status
Simulation time 32719296493 ps
CPU time 52.22 seconds
Started Aug 09 07:54:56 PM PDT 24
Finished Aug 09 07:55:48 PM PDT 24
Peak memory 249592 kb
Host smart-2ff65091-f2af-4c37-8cee-e8c555e8208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429209890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3429209890
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3458548695
Short name T226
Test name
Test status
Simulation time 1288834324 ps
CPU time 7.58 seconds
Started Aug 09 07:54:51 PM PDT 24
Finished Aug 09 07:54:59 PM PDT 24
Peak memory 223696 kb
Host smart-d958c8af-2437-4d93-8edc-11f670d936e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458548695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3458548695
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1195880870
Short name T447
Test name
Test status
Simulation time 3715229022 ps
CPU time 13.58 seconds
Started Aug 09 07:55:05 PM PDT 24
Finished Aug 09 07:55:19 PM PDT 24
Peak memory 233092 kb
Host smart-13c1122c-c766-4583-aa22-7f61d7780c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195880870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1195880870
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3722316463
Short name T38
Test name
Test status
Simulation time 1558304620 ps
CPU time 21.13 seconds
Started Aug 09 07:55:06 PM PDT 24
Finished Aug 09 07:55:27 PM PDT 24
Peak memory 221072 kb
Host smart-0422ad26-cc9a-48d6-8bbc-c23e8609aaf1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3722316463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3722316463
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1191938183
Short name T803
Test name
Test status
Simulation time 520954013706 ps
CPU time 503.46 seconds
Started Aug 09 07:55:02 PM PDT 24
Finished Aug 09 08:03:25 PM PDT 24
Peak memory 265268 kb
Host smart-f8214f24-019c-46d3-9f7f-fb269804a3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191938183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1191938183
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1652044122
Short name T926
Test name
Test status
Simulation time 8744524572 ps
CPU time 41.95 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 216752 kb
Host smart-5979025e-1d73-4213-96f0-820aa609f77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652044122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1652044122
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2420908049
Short name T389
Test name
Test status
Simulation time 8210821560 ps
CPU time 4.85 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 216716 kb
Host smart-12ee6225-f4f9-43bc-a548-b21d36be91c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420908049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2420908049
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2688911225
Short name T944
Test name
Test status
Simulation time 22147604 ps
CPU time 0.69 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:54:57 PM PDT 24
Peak memory 204852 kb
Host smart-7a1874df-1c69-433e-961c-659584bb0958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688911225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2688911225
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3673875780
Short name T533
Test name
Test status
Simulation time 254952464 ps
CPU time 0.87 seconds
Started Aug 09 07:54:48 PM PDT 24
Finished Aug 09 07:54:49 PM PDT 24
Peak memory 206272 kb
Host smart-8dd13b51-75d7-4d66-98db-ab4793347e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673875780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3673875780
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1852227510
Short name T990
Test name
Test status
Simulation time 744698787 ps
CPU time 6.07 seconds
Started Aug 09 07:54:59 PM PDT 24
Finished Aug 09 07:55:05 PM PDT 24
Peak memory 224928 kb
Host smart-1a45f6c8-cde8-4fe9-9c95-a9b21f488370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852227510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1852227510
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1003502153
Short name T865
Test name
Test status
Simulation time 47723006 ps
CPU time 0.75 seconds
Started Aug 09 07:54:56 PM PDT 24
Finished Aug 09 07:54:57 PM PDT 24
Peak memory 205844 kb
Host smart-08a778ff-5131-411c-b0f3-ccc4d3ff5276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003502153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1003502153
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3518609022
Short name T93
Test name
Test status
Simulation time 7290629456 ps
CPU time 20.21 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:55:30 PM PDT 24
Peak memory 233156 kb
Host smart-2b003b74-be17-40fa-ba45-793b7486d3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518609022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3518609022
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3324927983
Short name T550
Test name
Test status
Simulation time 13233551 ps
CPU time 0.75 seconds
Started Aug 09 07:54:59 PM PDT 24
Finished Aug 09 07:54:59 PM PDT 24
Peak memory 205944 kb
Host smart-8bdbc3e9-5b9d-41ce-a8ab-b34f2ebe4bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324927983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3324927983
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1241254444
Short name T837
Test name
Test status
Simulation time 11674758997 ps
CPU time 76.13 seconds
Started Aug 09 07:55:01 PM PDT 24
Finished Aug 09 07:56:17 PM PDT 24
Peak memory 248876 kb
Host smart-c7bc5c34-3d7b-4f08-ae93-cac6aea485f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241254444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1241254444
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1747646010
Short name T445
Test name
Test status
Simulation time 15414460494 ps
CPU time 48.85 seconds
Started Aug 09 07:55:06 PM PDT 24
Finished Aug 09 07:55:55 PM PDT 24
Peak memory 249576 kb
Host smart-86289e54-1750-49d7-a23c-0ba2a6575917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747646010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1747646010
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.806488722
Short name T510
Test name
Test status
Simulation time 3122321647 ps
CPU time 81.89 seconds
Started Aug 09 07:55:06 PM PDT 24
Finished Aug 09 07:56:28 PM PDT 24
Peak memory 257320 kb
Host smart-6c9cc4b6-45c8-4ebd-b16c-4cc4421a3298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806488722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.806488722
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1565456943
Short name T882
Test name
Test status
Simulation time 5238343395 ps
CPU time 13.32 seconds
Started Aug 09 07:55:01 PM PDT 24
Finished Aug 09 07:55:15 PM PDT 24
Peak memory 233148 kb
Host smart-708fc2be-16ed-4721-a964-e46ed67aec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565456943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1565456943
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.973266783
Short name T920
Test name
Test status
Simulation time 39007927519 ps
CPU time 256.28 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:59:26 PM PDT 24
Peak memory 265440 kb
Host smart-60592d69-b8cb-4a81-b715-2c845b19cdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973266783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.973266783
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.966506081
Short name T953
Test name
Test status
Simulation time 418384599 ps
CPU time 3.54 seconds
Started Aug 09 07:55:02 PM PDT 24
Finished Aug 09 07:55:05 PM PDT 24
Peak memory 224860 kb
Host smart-00aefc0f-ef28-444a-80c0-016133246ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966506081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.966506081
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1977236119
Short name T251
Test name
Test status
Simulation time 498088935 ps
CPU time 10.45 seconds
Started Aug 09 07:55:09 PM PDT 24
Finished Aug 09 07:55:19 PM PDT 24
Peak memory 233132 kb
Host smart-428a7459-3478-43f9-820e-02acb58a96a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977236119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1977236119
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.952212350
Short name T935
Test name
Test status
Simulation time 999171920 ps
CPU time 6.86 seconds
Started Aug 09 07:54:58 PM PDT 24
Finished Aug 09 07:55:05 PM PDT 24
Peak memory 238756 kb
Host smart-1ec109ae-b025-4645-a6cc-862a0271cfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952212350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.952212350
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3800316837
Short name T911
Test name
Test status
Simulation time 160960152534 ps
CPU time 27.38 seconds
Started Aug 09 07:54:52 PM PDT 24
Finished Aug 09 07:55:19 PM PDT 24
Peak memory 241340 kb
Host smart-b4a28fa0-03bf-4d93-a5ab-f19112d94663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800316837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3800316837
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.496023031
Short name T825
Test name
Test status
Simulation time 2922754809 ps
CPU time 7.27 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:55:18 PM PDT 24
Peak memory 219888 kb
Host smart-ac5f4c42-2473-4e49-9659-5d37d5e1671b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=496023031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.496023031
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4062619961
Short name T59
Test name
Test status
Simulation time 786586763 ps
CPU time 6.27 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:54:55 PM PDT 24
Peak memory 216856 kb
Host smart-09f12988-d478-4236-b57b-c0818ce8622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062619961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4062619961
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2769868245
Short name T327
Test name
Test status
Simulation time 828695940 ps
CPU time 5.39 seconds
Started Aug 09 07:54:51 PM PDT 24
Finished Aug 09 07:54:57 PM PDT 24
Peak memory 216588 kb
Host smart-bb467f01-ace3-45c1-903e-940f4210c29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769868245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2769868245
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1742938010
Short name T745
Test name
Test status
Simulation time 1274588569 ps
CPU time 1.91 seconds
Started Aug 09 07:54:59 PM PDT 24
Finished Aug 09 07:55:01 PM PDT 24
Peak memory 216656 kb
Host smart-dc49d154-a100-4948-ac9d-d39f366b6e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742938010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1742938010
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1214749960
Short name T28
Test name
Test status
Simulation time 82270886 ps
CPU time 0.91 seconds
Started Aug 09 07:55:07 PM PDT 24
Finished Aug 09 07:55:08 PM PDT 24
Peak memory 206356 kb
Host smart-e81479fb-aed9-4c8f-aec0-5dc9891478f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214749960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1214749960
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3348099584
Short name T523
Test name
Test status
Simulation time 1163384513 ps
CPU time 6.93 seconds
Started Aug 09 07:55:06 PM PDT 24
Finished Aug 09 07:55:13 PM PDT 24
Peak memory 224872 kb
Host smart-2edb92ff-9d53-4ebf-b851-ae804e824a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348099584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3348099584
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.888038996
Short name T452
Test name
Test status
Simulation time 12041366 ps
CPU time 0.73 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:55:11 PM PDT 24
Peak memory 206124 kb
Host smart-882c2d3a-f74f-4750-b31f-e27661162a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888038996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.888038996
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1010480829
Short name T772
Test name
Test status
Simulation time 443761432 ps
CPU time 5.33 seconds
Started Aug 09 07:55:09 PM PDT 24
Finished Aug 09 07:55:14 PM PDT 24
Peak memory 224900 kb
Host smart-8ee183dc-1642-4b09-838d-e6738480d9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010480829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1010480829
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2980938586
Short name T538
Test name
Test status
Simulation time 58401587 ps
CPU time 0.76 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:55:11 PM PDT 24
Peak memory 205920 kb
Host smart-97564152-252a-4903-8ffa-8ff3021c65c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980938586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2980938586
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3802322775
Short name T975
Test name
Test status
Simulation time 22551457884 ps
CPU time 84.21 seconds
Started Aug 09 07:55:08 PM PDT 24
Finished Aug 09 07:56:32 PM PDT 24
Peak memory 256236 kb
Host smart-88635d28-763b-422a-9727-494c1df53785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802322775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3802322775
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2667313938
Short name T868
Test name
Test status
Simulation time 15615614562 ps
CPU time 85.39 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:56:35 PM PDT 24
Peak memory 257832 kb
Host smart-e693ad26-2257-45ee-9787-9eb779bee17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667313938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2667313938
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3760328897
Short name T245
Test name
Test status
Simulation time 29826189839 ps
CPU time 122.48 seconds
Started Aug 09 07:55:13 PM PDT 24
Finished Aug 09 07:57:15 PM PDT 24
Peak memory 266008 kb
Host smart-14813323-2df0-4fbe-b573-9268f56bc693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760328897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3760328897
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4261438190
Short name T598
Test name
Test status
Simulation time 18856341214 ps
CPU time 14.7 seconds
Started Aug 09 07:55:04 PM PDT 24
Finished Aug 09 07:55:18 PM PDT 24
Peak memory 224940 kb
Host smart-46353d2c-aeb5-443f-a3fe-bd344ad6f755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261438190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4261438190
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.502442773
Short name T733
Test name
Test status
Simulation time 8512976325 ps
CPU time 26.46 seconds
Started Aug 09 07:55:08 PM PDT 24
Finished Aug 09 07:55:34 PM PDT 24
Peak memory 241236 kb
Host smart-0cfbf4de-8699-49ba-876c-907b46ba7c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502442773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.502442773
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3517191860
Short name T60
Test name
Test status
Simulation time 1363707745 ps
CPU time 12.28 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:55:24 PM PDT 24
Peak memory 233112 kb
Host smart-14d41604-f5e8-42ca-9334-28f8e63adcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517191860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3517191860
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2529319634
Short name T509
Test name
Test status
Simulation time 1423075880 ps
CPU time 8.84 seconds
Started Aug 09 07:55:07 PM PDT 24
Finished Aug 09 07:55:16 PM PDT 24
Peak memory 233144 kb
Host smart-de01bb78-be90-44c5-80ea-04476c3b7611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529319634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2529319634
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.346614377
Short name T357
Test name
Test status
Simulation time 235817868 ps
CPU time 5.2 seconds
Started Aug 09 07:55:06 PM PDT 24
Finished Aug 09 07:55:11 PM PDT 24
Peak memory 233140 kb
Host smart-c150db4e-4b05-4dba-b191-edabb09910f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346614377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.346614377
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3802762875
Short name T905
Test name
Test status
Simulation time 6351651508 ps
CPU time 5.47 seconds
Started Aug 09 07:55:05 PM PDT 24
Finished Aug 09 07:55:10 PM PDT 24
Peak memory 224868 kb
Host smart-dd50e54d-266a-4877-8e23-74f37ff3e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802762875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3802762875
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.67242902
Short name T850
Test name
Test status
Simulation time 163449065 ps
CPU time 3.45 seconds
Started Aug 09 07:55:01 PM PDT 24
Finished Aug 09 07:55:05 PM PDT 24
Peak memory 223076 kb
Host smart-dd271bf8-e382-4530-bf0b-7bf2e40d9793
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=67242902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direc
t.67242902
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.809796591
Short name T978
Test name
Test status
Simulation time 6530341029 ps
CPU time 16.28 seconds
Started Aug 09 07:55:09 PM PDT 24
Finished Aug 09 07:55:25 PM PDT 24
Peak memory 216776 kb
Host smart-1721096b-0240-4dd6-a4ed-055410515662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809796591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.809796591
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3574360873
Short name T24
Test name
Test status
Simulation time 10661601174 ps
CPU time 17.26 seconds
Started Aug 09 07:55:00 PM PDT 24
Finished Aug 09 07:55:17 PM PDT 24
Peak memory 216672 kb
Host smart-f0ff385b-9f4c-4bc6-8f9d-63d0309210fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574360873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3574360873
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1600786949
Short name T347
Test name
Test status
Simulation time 26213812 ps
CPU time 1.18 seconds
Started Aug 09 07:54:55 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 216720 kb
Host smart-435cd2a4-1b5d-4967-bce1-7620825fe3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600786949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1600786949
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.297597145
Short name T993
Test name
Test status
Simulation time 60113290 ps
CPU time 0.76 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:55:11 PM PDT 24
Peak memory 206328 kb
Host smart-995a0456-d269-43a2-8874-a35aa327f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297597145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.297597145
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.782836008
Short name T273
Test name
Test status
Simulation time 14964207273 ps
CPU time 16.35 seconds
Started Aug 09 07:55:08 PM PDT 24
Finished Aug 09 07:55:25 PM PDT 24
Peak memory 233152 kb
Host smart-0031e129-c28d-4f27-9593-b17886465fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782836008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.782836008
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.83943459
Short name T547
Test name
Test status
Simulation time 30677349 ps
CPU time 0.73 seconds
Started Aug 09 07:55:15 PM PDT 24
Finished Aug 09 07:55:15 PM PDT 24
Peak memory 205812 kb
Host smart-7d407abb-a958-4af7-8023-2718b26cbc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83943459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.83943459
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1651046444
Short name T862
Test name
Test status
Simulation time 977344342 ps
CPU time 6.36 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:55:18 PM PDT 24
Peak memory 233024 kb
Host smart-a5f0326a-f84d-48d0-ac51-de76af81981d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651046444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1651046444
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3534194557
Short name T726
Test name
Test status
Simulation time 11764763 ps
CPU time 0.72 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:55:12 PM PDT 24
Peak memory 206220 kb
Host smart-fd71b5b9-3a26-42ca-96bb-a42edf2509d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534194557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3534194557
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1126937524
Short name T724
Test name
Test status
Simulation time 10581734847 ps
CPU time 65.77 seconds
Started Aug 09 07:55:09 PM PDT 24
Finished Aug 09 07:56:15 PM PDT 24
Peak memory 262700 kb
Host smart-3484ddac-0297-4067-920d-1af1a8067e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126937524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1126937524
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.437815514
Short name T135
Test name
Test status
Simulation time 122795471702 ps
CPU time 303.52 seconds
Started Aug 09 07:55:12 PM PDT 24
Finished Aug 09 08:00:15 PM PDT 24
Peak memory 250092 kb
Host smart-467bddaa-55d2-4e64-b987-f7c04ccbc196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437815514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.437815514
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3777781915
Short name T51
Test name
Test status
Simulation time 2364520172 ps
CPU time 14.46 seconds
Started Aug 09 07:55:08 PM PDT 24
Finished Aug 09 07:55:23 PM PDT 24
Peak memory 222680 kb
Host smart-9cda7f62-1c37-46bf-8c19-2846a1466a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777781915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3777781915
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3756149727
Short name T683
Test name
Test status
Simulation time 794431222 ps
CPU time 7.24 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:55:17 PM PDT 24
Peak memory 224856 kb
Host smart-f2c0b111-8fb9-4f64-b347-0d462c783c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756149727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3756149727
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3717562660
Short name T988
Test name
Test status
Simulation time 45700263093 ps
CPU time 98.75 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:56:50 PM PDT 24
Peak memory 241380 kb
Host smart-6f77ec02-9a65-4367-944b-c9d6331d2fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717562660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3717562660
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.187534296
Short name T919
Test name
Test status
Simulation time 2004784270 ps
CPU time 4.76 seconds
Started Aug 09 07:55:13 PM PDT 24
Finished Aug 09 07:55:18 PM PDT 24
Peak memory 224848 kb
Host smart-706b2ed5-a4b5-4a69-9829-8b749186926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187534296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.187534296
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1231168507
Short name T712
Test name
Test status
Simulation time 10862730576 ps
CPU time 60.99 seconds
Started Aug 09 07:55:12 PM PDT 24
Finished Aug 09 07:56:13 PM PDT 24
Peak memory 225004 kb
Host smart-ac7572f2-10e2-4a9f-8013-a22a9e000d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231168507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1231168507
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1218541568
Short name T968
Test name
Test status
Simulation time 6064548677 ps
CPU time 9.62 seconds
Started Aug 09 07:55:13 PM PDT 24
Finished Aug 09 07:55:22 PM PDT 24
Peak memory 241388 kb
Host smart-3f77c176-1e02-460f-aa46-f98d9e348aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218541568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1218541568
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4092827851
Short name T863
Test name
Test status
Simulation time 4034511326 ps
CPU time 4.46 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:55:15 PM PDT 24
Peak memory 233192 kb
Host smart-df17d8da-1a04-4daa-9ac6-1cba19af58e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092827851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4092827851
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2808224722
Short name T621
Test name
Test status
Simulation time 1959268153 ps
CPU time 19.81 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:55:31 PM PDT 24
Peak memory 220944 kb
Host smart-3d3fe5f0-2726-47ca-8990-74797978706d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2808224722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2808224722
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.750399179
Short name T144
Test name
Test status
Simulation time 111445828743 ps
CPU time 329.22 seconds
Started Aug 09 07:55:09 PM PDT 24
Finished Aug 09 08:00:38 PM PDT 24
Peak memory 272896 kb
Host smart-1bc6f991-6230-4481-b2eb-6ca7dba89909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750399179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.750399179
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3876499065
Short name T457
Test name
Test status
Simulation time 12960544507 ps
CPU time 19.66 seconds
Started Aug 09 07:55:10 PM PDT 24
Finished Aug 09 07:55:29 PM PDT 24
Peak memory 216700 kb
Host smart-572ab638-e49f-4ad4-9f24-35f973544415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876499065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3876499065
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1275569852
Short name T422
Test name
Test status
Simulation time 39944698 ps
CPU time 1.07 seconds
Started Aug 09 07:55:13 PM PDT 24
Finished Aug 09 07:55:14 PM PDT 24
Peak memory 206360 kb
Host smart-7f693567-f059-405b-a395-58a3a99b2df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275569852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1275569852
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2823974648
Short name T830
Test name
Test status
Simulation time 11357255 ps
CPU time 0.67 seconds
Started Aug 09 07:55:14 PM PDT 24
Finished Aug 09 07:55:15 PM PDT 24
Peak memory 205976 kb
Host smart-1f822f51-4d52-4b65-963f-d992a95330eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823974648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2823974648
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2430597362
Short name T994
Test name
Test status
Simulation time 29580029 ps
CPU time 0.66 seconds
Started Aug 09 07:55:12 PM PDT 24
Finished Aug 09 07:55:12 PM PDT 24
Peak memory 205948 kb
Host smart-08acf8cc-3c64-47a8-8236-a612930e0268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430597362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2430597362
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3781193360
Short name T271
Test name
Test status
Simulation time 3794153991 ps
CPU time 3.02 seconds
Started Aug 09 07:55:12 PM PDT 24
Finished Aug 09 07:55:15 PM PDT 24
Peak memory 224916 kb
Host smart-22d71439-e4ff-4622-8259-f4248620356f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781193360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3781193360
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1342320580
Short name T1005
Test name
Test status
Simulation time 13727325 ps
CPU time 0.71 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:31 PM PDT 24
Peak memory 205224 kb
Host smart-97c960cb-9d59-45b7-83e2-81325b0caf12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342320580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
342320580
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2048453648
Short name T878
Test name
Test status
Simulation time 294561074 ps
CPU time 4.26 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:34 PM PDT 24
Peak memory 233096 kb
Host smart-198ae8cf-b73f-49d4-a51f-67acc6509503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048453648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2048453648
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.767722614
Short name T903
Test name
Test status
Simulation time 47424905 ps
CPU time 0.78 seconds
Started Aug 09 07:54:17 PM PDT 24
Finished Aug 09 07:54:18 PM PDT 24
Peak memory 206304 kb
Host smart-40bd958d-0ecf-4a29-8058-467e00fb4de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767722614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.767722614
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1797469564
Short name T578
Test name
Test status
Simulation time 57881674794 ps
CPU time 389.8 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 08:01:00 PM PDT 24
Peak memory 252524 kb
Host smart-d478ec1a-e657-4a30-9bb4-9114cf51e126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797469564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1797469564
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.811357949
Short name T239
Test name
Test status
Simulation time 6432152108 ps
CPU time 89.39 seconds
Started Aug 09 07:54:28 PM PDT 24
Finished Aug 09 07:55:58 PM PDT 24
Peak memory 257808 kb
Host smart-235d4712-a8ca-49ac-a866-595ea0bab3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811357949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.811357949
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1972331061
Short name T964
Test name
Test status
Simulation time 12030348781 ps
CPU time 52.4 seconds
Started Aug 09 07:54:28 PM PDT 24
Finished Aug 09 07:55:20 PM PDT 24
Peak memory 250092 kb
Host smart-62e66c68-4fe5-462a-9767-c652bc58a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972331061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1972331061
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2280508
Short name T698
Test name
Test status
Simulation time 690066193 ps
CPU time 8.94 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:54:45 PM PDT 24
Peak memory 224844 kb
Host smart-2e7c4e9a-0fb2-4764-8bcf-c20963793e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2280508
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1676178654
Short name T449
Test name
Test status
Simulation time 3683559805 ps
CPU time 34.96 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 07:55:04 PM PDT 24
Peak memory 225008 kb
Host smart-2b378f0e-7d85-41aa-b4e8-9d08865b9758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676178654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1676178654
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4293430858
Short name T1000
Test name
Test status
Simulation time 209086514 ps
CPU time 3.68 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:35 PM PDT 24
Peak memory 233136 kb
Host smart-7182c23e-0056-4274-8349-a87aaf6eb013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293430858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4293430858
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3562211150
Short name T540
Test name
Test status
Simulation time 606241824 ps
CPU time 4.87 seconds
Started Aug 09 07:54:19 PM PDT 24
Finished Aug 09 07:54:23 PM PDT 24
Peak memory 241244 kb
Host smart-fbfeaaac-d3ec-4306-9f54-3e1d0b3c2eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562211150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3562211150
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2598928815
Short name T950
Test name
Test status
Simulation time 592685377 ps
CPU time 3.78 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:40 PM PDT 24
Peak memory 219240 kb
Host smart-c174ee99-b998-42c4-a244-ef521f5f020e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2598928815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2598928815
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1498122588
Short name T72
Test name
Test status
Simulation time 256190366 ps
CPU time 1.08 seconds
Started Aug 09 07:54:28 PM PDT 24
Finished Aug 09 07:54:29 PM PDT 24
Peak memory 236916 kb
Host smart-2867f6c0-4795-42f1-8dcf-39204ab1e76d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498122588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1498122588
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1557423054
Short name T731
Test name
Test status
Simulation time 14893756572 ps
CPU time 222.55 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 07:58:12 PM PDT 24
Peak memory 261884 kb
Host smart-c8694a3e-7c09-4654-a355-1405173c4033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557423054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1557423054
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2779626114
Short name T815
Test name
Test status
Simulation time 9049946692 ps
CPU time 39.52 seconds
Started Aug 09 07:54:24 PM PDT 24
Finished Aug 09 07:55:04 PM PDT 24
Peak memory 216672 kb
Host smart-519529e5-64e5-441f-9f6c-eafe1886ef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779626114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2779626114
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1269714558
Short name T613
Test name
Test status
Simulation time 516476875 ps
CPU time 4.33 seconds
Started Aug 09 07:54:15 PM PDT 24
Finished Aug 09 07:54:20 PM PDT 24
Peak memory 216672 kb
Host smart-f7725520-762d-418f-b621-0e2c195e4ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269714558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1269714558
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1261558534
Short name T703
Test name
Test status
Simulation time 170702871 ps
CPU time 1.49 seconds
Started Aug 09 07:54:21 PM PDT 24
Finished Aug 09 07:54:23 PM PDT 24
Peak memory 216692 kb
Host smart-0dc27487-ecf9-464b-8c7f-cfd59f69cc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261558534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1261558534
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3162190194
Short name T401
Test name
Test status
Simulation time 316385743 ps
CPU time 0.85 seconds
Started Aug 09 07:54:28 PM PDT 24
Finished Aug 09 07:54:29 PM PDT 24
Peak memory 206336 kb
Host smart-98b3c933-30c2-4de5-a8b6-adcd7636d1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162190194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3162190194
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1221667089
Short name T363
Test name
Test status
Simulation time 175136425 ps
CPU time 2.66 seconds
Started Aug 09 07:54:28 PM PDT 24
Finished Aug 09 07:54:31 PM PDT 24
Peak memory 233120 kb
Host smart-dd1577a8-315b-4fe6-9e95-f3a0ec0108f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221667089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1221667089
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.902865421
Short name T64
Test name
Test status
Simulation time 97341494 ps
CPU time 0.76 seconds
Started Aug 09 07:55:18 PM PDT 24
Finished Aug 09 07:55:19 PM PDT 24
Peak memory 205792 kb
Host smart-5e263a45-3142-4032-8980-4cacf9e8c04b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902865421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.902865421
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4213024389
Short name T267
Test name
Test status
Simulation time 170682543 ps
CPU time 3.62 seconds
Started Aug 09 07:55:14 PM PDT 24
Finished Aug 09 07:55:17 PM PDT 24
Peak memory 224844 kb
Host smart-6304f390-fa41-4cc3-866b-fc99f6c1783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213024389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4213024389
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3124307980
Short name T406
Test name
Test status
Simulation time 35860527 ps
CPU time 0.84 seconds
Started Aug 09 07:55:11 PM PDT 24
Finished Aug 09 07:55:12 PM PDT 24
Peak memory 206940 kb
Host smart-357c97e3-c5c9-4e37-b5ee-821f334bdd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124307980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3124307980
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3735078162
Short name T1003
Test name
Test status
Simulation time 72852828470 ps
CPU time 167.71 seconds
Started Aug 09 07:55:16 PM PDT 24
Finished Aug 09 07:58:03 PM PDT 24
Peak memory 257488 kb
Host smart-d9ea6f5c-96f9-402f-a138-66352a47bff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735078162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3735078162
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1322887403
Short name T430
Test name
Test status
Simulation time 152043869814 ps
CPU time 371.86 seconds
Started Aug 09 07:55:22 PM PDT 24
Finished Aug 09 08:01:34 PM PDT 24
Peak memory 265288 kb
Host smart-e35a7402-a068-46f7-8d1d-5ae94b19d8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322887403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1322887403
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3132246978
Short name T594
Test name
Test status
Simulation time 12836710299 ps
CPU time 60.58 seconds
Started Aug 09 07:55:14 PM PDT 24
Finished Aug 09 07:56:14 PM PDT 24
Peak memory 253308 kb
Host smart-7de1e0e1-b0e5-4ecd-94da-aefdc4482043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132246978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3132246978
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2925346474
Short name T388
Test name
Test status
Simulation time 8626238748 ps
CPU time 17.82 seconds
Started Aug 09 07:55:21 PM PDT 24
Finished Aug 09 07:55:39 PM PDT 24
Peak memory 224912 kb
Host smart-b03f7952-019c-4829-a9a2-3de06945783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925346474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2925346474
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1948195368
Short name T817
Test name
Test status
Simulation time 531395198 ps
CPU time 9.78 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:36 PM PDT 24
Peak memory 239508 kb
Host smart-f84c9bca-3949-42b2-98bf-eee221629f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948195368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1948195368
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3981405322
Short name T40
Test name
Test status
Simulation time 9754329604 ps
CPU time 11.09 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:55:49 PM PDT 24
Peak memory 233136 kb
Host smart-cbb912a1-9598-4b74-8832-b234a1798c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981405322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3981405322
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2006153336
Short name T591
Test name
Test status
Simulation time 5915336529 ps
CPU time 6.86 seconds
Started Aug 09 07:55:21 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 233164 kb
Host smart-b54356b2-5320-4808-839b-17bdbda24e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006153336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2006153336
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1636060567
Short name T494
Test name
Test status
Simulation time 653625857 ps
CPU time 4.05 seconds
Started Aug 09 07:55:22 PM PDT 24
Finished Aug 09 07:55:26 PM PDT 24
Peak memory 221292 kb
Host smart-e158a095-bd98-4746-890c-7aac83482bc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636060567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1636060567
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1418143082
Short name T436
Test name
Test status
Simulation time 30879692649 ps
CPU time 145.83 seconds
Started Aug 09 07:55:22 PM PDT 24
Finished Aug 09 07:57:48 PM PDT 24
Peak memory 237892 kb
Host smart-a64627da-03cc-40ce-bb0d-35fcca9928b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418143082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1418143082
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3891158648
Short name T136
Test name
Test status
Simulation time 370242939 ps
CPU time 2.46 seconds
Started Aug 09 07:55:24 PM PDT 24
Finished Aug 09 07:55:27 PM PDT 24
Peak memory 216700 kb
Host smart-185b6ea5-6b38-40f0-adf2-2ada5f0d1043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891158648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3891158648
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4215426906
Short name T485
Test name
Test status
Simulation time 16183588915 ps
CPU time 12.94 seconds
Started Aug 09 07:55:21 PM PDT 24
Finished Aug 09 07:55:34 PM PDT 24
Peak memory 216712 kb
Host smart-6f00471c-9765-44cb-8470-285f078162ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215426906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4215426906
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.972404211
Short name T504
Test name
Test status
Simulation time 145452274 ps
CPU time 0.86 seconds
Started Aug 09 07:55:16 PM PDT 24
Finished Aug 09 07:55:17 PM PDT 24
Peak memory 207072 kb
Host smart-96779b2e-c776-4b8e-a048-842ab27a1cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972404211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.972404211
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3291826894
Short name T375
Test name
Test status
Simulation time 203975194 ps
CPU time 0.84 seconds
Started Aug 09 07:55:25 PM PDT 24
Finished Aug 09 07:55:26 PM PDT 24
Peak memory 206364 kb
Host smart-8b82fcf7-214b-41c3-ae00-a58234cb5995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291826894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3291826894
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.871718642
Short name T809
Test name
Test status
Simulation time 1502327977 ps
CPU time 6.22 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 07:55:27 PM PDT 24
Peak memory 233044 kb
Host smart-0603a512-d1f2-45fb-9a6c-55977116a0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871718642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.871718642
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1379634375
Short name T828
Test name
Test status
Simulation time 25619136 ps
CPU time 0.7 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 07:55:21 PM PDT 24
Peak memory 205888 kb
Host smart-d2a60699-2df1-47c9-b527-ebedaa7d456b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379634375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1379634375
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3275534833
Short name T629
Test name
Test status
Simulation time 164936608 ps
CPU time 3.96 seconds
Started Aug 09 07:55:23 PM PDT 24
Finished Aug 09 07:55:27 PM PDT 24
Peak memory 233100 kb
Host smart-55cb3a9a-a3cd-4846-9483-f2fd7256efc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275534833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3275534833
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2999541414
Short name T553
Test name
Test status
Simulation time 43622331 ps
CPU time 0.77 seconds
Started Aug 09 07:55:16 PM PDT 24
Finished Aug 09 07:55:16 PM PDT 24
Peak memory 206288 kb
Host smart-ee7c0c9d-8db9-4592-a167-035dbcafebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999541414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2999541414
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3488208447
Short name T225
Test name
Test status
Simulation time 2436428272 ps
CPU time 60.41 seconds
Started Aug 09 07:55:21 PM PDT 24
Finished Aug 09 07:56:21 PM PDT 24
Peak memory 265960 kb
Host smart-e7f37a13-0cdc-49ed-8106-0af6988c24aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488208447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3488208447
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1260455838
Short name T253
Test name
Test status
Simulation time 4463187637 ps
CPU time 63 seconds
Started Aug 09 07:55:25 PM PDT 24
Finished Aug 09 07:56:28 PM PDT 24
Peak memory 251708 kb
Host smart-3d592904-e256-4f86-868d-600053000618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260455838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1260455838
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.983925420
Short name T304
Test name
Test status
Simulation time 561089754 ps
CPU time 6.58 seconds
Started Aug 09 07:55:15 PM PDT 24
Finished Aug 09 07:55:21 PM PDT 24
Peak memory 233096 kb
Host smart-fd2305d2-8f19-4b50-9991-365e6fac749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983925420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.983925420
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.965332973
Short name T976
Test name
Test status
Simulation time 133975926 ps
CPU time 2.41 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 232844 kb
Host smart-2369a12b-8faf-4a50-8ede-0fb6b6c82402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965332973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.965332973
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.816538830
Short name T857
Test name
Test status
Simulation time 632681352 ps
CPU time 10.75 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:37 PM PDT 24
Peak memory 233088 kb
Host smart-0faff170-9488-4aa3-a2e6-d13c8f5ec4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816538830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.816538830
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3102316046
Short name T933
Test name
Test status
Simulation time 2046650535 ps
CPU time 10.95 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 07:55:31 PM PDT 24
Peak memory 233024 kb
Host smart-7d72e8e2-407e-4f26-a98a-f417282e088a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102316046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3102316046
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.311244037
Short name T260
Test name
Test status
Simulation time 3001315891 ps
CPU time 5.87 seconds
Started Aug 09 07:55:22 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 224920 kb
Host smart-0cfdd31c-944f-4e83-8c33-7e27449e5cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311244037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.311244037
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2104402925
Short name T961
Test name
Test status
Simulation time 5369424943 ps
CPU time 5.79 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 07:55:26 PM PDT 24
Peak memory 221084 kb
Host smart-2a44f22e-5a50-4931-b7dd-dbf78170db8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2104402925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2104402925
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3292217957
Short name T840
Test name
Test status
Simulation time 27331719234 ps
CPU time 223.23 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 07:59:03 PM PDT 24
Peak memory 256544 kb
Host smart-f41aecff-55e6-480a-be9c-b689b2c6d2df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292217957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3292217957
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3510436314
Short name T177
Test name
Test status
Simulation time 1588923357 ps
CPU time 11.68 seconds
Started Aug 09 07:55:14 PM PDT 24
Finished Aug 09 07:55:26 PM PDT 24
Peak memory 216672 kb
Host smart-b190c418-9070-4144-8435-a6a1107f57d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510436314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3510436314
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3665379172
Short name T761
Test name
Test status
Simulation time 3073859940 ps
CPU time 4.64 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 07:55:25 PM PDT 24
Peak memory 216628 kb
Host smart-5be23475-1f44-49bb-912a-0ed7d7df86a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665379172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3665379172
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.434913967
Short name T554
Test name
Test status
Simulation time 31477612 ps
CPU time 0.68 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 07:55:21 PM PDT 24
Peak memory 206036 kb
Host smart-307df09c-0324-46e2-b007-dfe2ccb32c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434913967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.434913967
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.253636259
Short name T958
Test name
Test status
Simulation time 27763199 ps
CPU time 0.85 seconds
Started Aug 09 07:55:18 PM PDT 24
Finished Aug 09 07:55:19 PM PDT 24
Peak memory 206340 kb
Host smart-14352c6f-20b8-4794-9158-813b2eaacb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253636259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.253636259
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1343241088
Short name T960
Test name
Test status
Simulation time 4847364208 ps
CPU time 18.36 seconds
Started Aug 09 07:55:23 PM PDT 24
Finished Aug 09 07:55:41 PM PDT 24
Peak memory 234548 kb
Host smart-73644ee3-3971-4867-a211-083ed9803f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343241088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1343241088
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2751771524
Short name T844
Test name
Test status
Simulation time 34791870 ps
CPU time 0.71 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:27 PM PDT 24
Peak memory 205836 kb
Host smart-5063bd8f-fccc-45e8-b2e3-ef054dbb2e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751771524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2751771524
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1524540170
Short name T765
Test name
Test status
Simulation time 2923089727 ps
CPU time 7.89 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 225044 kb
Host smart-97fa41eb-4452-4f18-aa07-c41220e27e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524540170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1524540170
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4075130556
Short name T330
Test name
Test status
Simulation time 23456154 ps
CPU time 0.75 seconds
Started Aug 09 07:55:17 PM PDT 24
Finished Aug 09 07:55:18 PM PDT 24
Peak memory 205948 kb
Host smart-afb2cec7-465c-4e35-8557-b09c29e02112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075130556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4075130556
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1522422323
Short name T276
Test name
Test status
Simulation time 2591893418 ps
CPU time 34.45 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:56:04 PM PDT 24
Peak memory 240720 kb
Host smart-e24a08c3-6def-49c2-95a4-81fa9d4deb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522422323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1522422323
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3642548287
Short name T839
Test name
Test status
Simulation time 12454613083 ps
CPU time 39.47 seconds
Started Aug 09 07:55:25 PM PDT 24
Finished Aug 09 07:56:05 PM PDT 24
Peak memory 249584 kb
Host smart-3121bd7c-d08b-47a2-acf1-bc5fb2abdeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642548287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3642548287
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.65377302
Short name T289
Test name
Test status
Simulation time 9822447816 ps
CPU time 107.7 seconds
Started Aug 09 07:55:16 PM PDT 24
Finished Aug 09 07:57:03 PM PDT 24
Peak memory 269000 kb
Host smart-aae3ce33-a378-44b9-bb3e-b7003fa1a551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65377302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.65377302
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2040403166
Short name T1011
Test name
Test status
Simulation time 121702107 ps
CPU time 3.45 seconds
Started Aug 09 07:55:19 PM PDT 24
Finished Aug 09 07:55:22 PM PDT 24
Peak memory 224972 kb
Host smart-1d6b6df7-a745-4e99-9ab3-47485de96497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040403166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2040403166
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3259971694
Short name T752
Test name
Test status
Simulation time 1520949705 ps
CPU time 5.86 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:32 PM PDT 24
Peak memory 224852 kb
Host smart-10deee4f-7bd0-409d-81fc-3a3a1e91467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259971694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3259971694
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2928055966
Short name T916
Test name
Test status
Simulation time 3884130476 ps
CPU time 6.39 seconds
Started Aug 09 07:55:19 PM PDT 24
Finished Aug 09 07:55:26 PM PDT 24
Peak memory 233172 kb
Host smart-2d481a33-65ad-41d8-a452-c8dc8c8433d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928055966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2928055966
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3175820046
Short name T120
Test name
Test status
Simulation time 3070318504 ps
CPU time 6.56 seconds
Started Aug 09 07:55:23 PM PDT 24
Finished Aug 09 07:55:30 PM PDT 24
Peak memory 240960 kb
Host smart-441bb6b6-916e-4098-884b-1c1cc2562ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175820046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3175820046
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1587481049
Short name T426
Test name
Test status
Simulation time 8382519076 ps
CPU time 11.4 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:37 PM PDT 24
Peak memory 219504 kb
Host smart-76a1a67d-66cc-4a99-9f5e-c1e3d9a4682d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1587481049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1587481049
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.622329854
Short name T887
Test name
Test status
Simulation time 39666451882 ps
CPU time 85.31 seconds
Started Aug 09 07:55:25 PM PDT 24
Finished Aug 09 07:56:50 PM PDT 24
Peak memory 249608 kb
Host smart-0ca53539-5a6f-4919-8b1b-56afe1e026d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622329854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.622329854
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.880284082
Short name T555
Test name
Test status
Simulation time 16082700 ps
CPU time 0.73 seconds
Started Aug 09 07:55:19 PM PDT 24
Finished Aug 09 07:55:19 PM PDT 24
Peak memory 206460 kb
Host smart-fc556bcd-1f01-4fb5-acfa-5e12f4ece030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880284082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.880284082
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1533376697
Short name T143
Test name
Test status
Simulation time 138517469 ps
CPU time 1.43 seconds
Started Aug 09 07:55:21 PM PDT 24
Finished Aug 09 07:55:23 PM PDT 24
Peak memory 208264 kb
Host smart-3ee583f9-e14e-4fb1-a353-b67ed17eb3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533376697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1533376697
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3505365781
Short name T142
Test name
Test status
Simulation time 74057248 ps
CPU time 1.6 seconds
Started Aug 09 07:55:20 PM PDT 24
Finished Aug 09 07:55:22 PM PDT 24
Peak memory 216624 kb
Host smart-2b4eb932-5e03-4938-92dd-bf1fd4d8127b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505365781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3505365781
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.561932362
Short name T416
Test name
Test status
Simulation time 131231500 ps
CPU time 0.78 seconds
Started Aug 09 07:55:25 PM PDT 24
Finished Aug 09 07:55:25 PM PDT 24
Peak memory 206276 kb
Host smart-e73b8ceb-57b8-41fc-aca5-44497ddea302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561932362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.561932362
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2187781675
Short name T709
Test name
Test status
Simulation time 2121250807 ps
CPU time 6.23 seconds
Started Aug 09 07:55:17 PM PDT 24
Finished Aug 09 07:55:23 PM PDT 24
Peak memory 239288 kb
Host smart-028fd764-1cc9-4418-98fa-122314e86772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187781675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2187781675
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1158744362
Short name T476
Test name
Test status
Simulation time 42555331 ps
CPU time 0.75 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:26 PM PDT 24
Peak memory 205868 kb
Host smart-78389b64-e629-4f18-a1eb-381e151f0c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158744362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1158744362
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2056748734
Short name T91
Test name
Test status
Simulation time 103836404 ps
CPU time 2.5 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:29 PM PDT 24
Peak memory 224944 kb
Host smart-506b76fe-f1f0-43e3-a654-b9638f0a0777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056748734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2056748734
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2101445802
Short name T801
Test name
Test status
Simulation time 18299309 ps
CPU time 0.81 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:27 PM PDT 24
Peak memory 206972 kb
Host smart-db23b19a-ec54-4569-85d5-356a778709c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101445802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2101445802
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.954954692
Short name T414
Test name
Test status
Simulation time 3694818148 ps
CPU time 18.65 seconds
Started Aug 09 07:55:24 PM PDT 24
Finished Aug 09 07:55:42 PM PDT 24
Peak memory 233124 kb
Host smart-03309b12-be03-4749-823c-232b9c2dfa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954954692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.954954692
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1148363569
Short name T11
Test name
Test status
Simulation time 10425762318 ps
CPU time 41.22 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:56:08 PM PDT 24
Peak memory 253376 kb
Host smart-b8ad5eb2-f611-4e6d-9d7e-3d93d0a17e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148363569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1148363569
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.866407261
Short name T297
Test name
Test status
Simulation time 11223938932 ps
CPU time 87.9 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:56:55 PM PDT 24
Peak memory 255588 kb
Host smart-4cc1b5e1-7b37-4c04-8486-0b12884016e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866407261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.866407261
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3153895204
Short name T370
Test name
Test status
Simulation time 117138896 ps
CPU time 3.44 seconds
Started Aug 09 07:55:25 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 224944 kb
Host smart-1f0a5b8f-c21f-4414-9bb5-ec72b2d153e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153895204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3153895204
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2187706463
Short name T234
Test name
Test status
Simulation time 1898243976 ps
CPU time 39.97 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:56:07 PM PDT 24
Peak memory 252304 kb
Host smart-0e33cc42-75e1-4671-b2bb-0fd68384df15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187706463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2187706463
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1604776981
Short name T722
Test name
Test status
Simulation time 300015779 ps
CPU time 2.99 seconds
Started Aug 09 07:55:30 PM PDT 24
Finished Aug 09 07:55:33 PM PDT 24
Peak memory 224892 kb
Host smart-2ef774fa-3fec-4dff-a454-d1cd51fe3458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604776981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1604776981
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1597646934
Short name T620
Test name
Test status
Simulation time 4887446750 ps
CPU time 61.84 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:56:28 PM PDT 24
Peak memory 233172 kb
Host smart-b489ce9b-1b12-4f4a-8de4-3b098a07ef28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597646934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1597646934
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.862655885
Short name T162
Test name
Test status
Simulation time 8700940825 ps
CPU time 25.75 seconds
Started Aug 09 07:55:25 PM PDT 24
Finished Aug 09 07:55:51 PM PDT 24
Peak memory 250568 kb
Host smart-0cec65ed-5e70-4de6-8812-fe915295e719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862655885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.862655885
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3573242120
Short name T665
Test name
Test status
Simulation time 33018823060 ps
CPU time 26 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:55 PM PDT 24
Peak memory 240812 kb
Host smart-3ac24b85-1400-4036-bbc1-69a87142ac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573242120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3573242120
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2082255884
Short name T877
Test name
Test status
Simulation time 550799370 ps
CPU time 8.58 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:36 PM PDT 24
Peak memory 223084 kb
Host smart-bae7c6de-a316-4056-931a-d6f588354c58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2082255884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2082255884
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.934973543
Short name T282
Test name
Test status
Simulation time 503818414497 ps
CPU time 529.25 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 08:04:15 PM PDT 24
Peak memory 267680 kb
Host smart-f549c195-a415-40f3-a802-ab4d464849ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934973543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.934973543
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3685209141
Short name T429
Test name
Test status
Simulation time 10852017151 ps
CPU time 13.74 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:41 PM PDT 24
Peak memory 216648 kb
Host smart-f48b6213-88a6-42e2-a646-557a53a45a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685209141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3685209141
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1421187697
Short name T604
Test name
Test status
Simulation time 6355913366 ps
CPU time 4.89 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:32 PM PDT 24
Peak memory 216724 kb
Host smart-dd433952-8849-4fa4-9ec9-70335cbae781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421187697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1421187697
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1155796227
Short name T831
Test name
Test status
Simulation time 808138352 ps
CPU time 2.72 seconds
Started Aug 09 07:55:23 PM PDT 24
Finished Aug 09 07:55:26 PM PDT 24
Peak memory 216664 kb
Host smart-04a9cee0-d3c4-4c55-ab00-d647b7cbd9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155796227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1155796227
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1042424616
Short name T778
Test name
Test status
Simulation time 32603527 ps
CPU time 0.81 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:27 PM PDT 24
Peak memory 206328 kb
Host smart-00c48355-f925-49c2-9e7c-f650e3cab1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042424616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1042424616
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3808013316
Short name T984
Test name
Test status
Simulation time 167080686 ps
CPU time 2.25 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 233052 kb
Host smart-9295eb2a-5015-46af-bb31-fe4479ac8865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808013316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3808013316
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3395574947
Short name T696
Test name
Test status
Simulation time 37837327 ps
CPU time 0.74 seconds
Started Aug 09 07:55:30 PM PDT 24
Finished Aug 09 07:55:31 PM PDT 24
Peak memory 206172 kb
Host smart-8660294f-84c9-4472-898e-1498d4151921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395574947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3395574947
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2801263825
Short name T742
Test name
Test status
Simulation time 570802332 ps
CPU time 3.7 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:31 PM PDT 24
Peak memory 224900 kb
Host smart-beb36515-a250-4c9d-87ed-8495deb97998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801263825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2801263825
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1238629886
Short name T671
Test name
Test status
Simulation time 13841779 ps
CPU time 0.79 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 207004 kb
Host smart-88c0297c-c7ed-4f98-bf0d-1299c21d7035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238629886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1238629886
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2582629577
Short name T962
Test name
Test status
Simulation time 91071469048 ps
CPU time 604.46 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 08:05:33 PM PDT 24
Peak memory 266452 kb
Host smart-993f6b82-f732-41c9-ac74-87fb61c3a4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582629577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2582629577
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2338615870
Short name T588
Test name
Test status
Simulation time 83887154985 ps
CPU time 220.17 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:59:07 PM PDT 24
Peak memory 257836 kb
Host smart-c2528c66-aa0f-433e-a8c3-49cbd94e392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338615870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2338615870
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3639434419
Short name T1014
Test name
Test status
Simulation time 17321301441 ps
CPU time 38.08 seconds
Started Aug 09 07:55:31 PM PDT 24
Finished Aug 09 07:56:09 PM PDT 24
Peak memory 233164 kb
Host smart-e8acfcfa-179e-4815-a0b0-6412d46c5f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639434419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3639434419
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.810780201
Short name T217
Test name
Test status
Simulation time 96455523210 ps
CPU time 375.64 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 08:01:42 PM PDT 24
Peak memory 263616 kb
Host smart-fa4f1b20-6557-4fa1-8fe2-1231bf8ad6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810780201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.810780201
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1502298030
Short name T515
Test name
Test status
Simulation time 429331164 ps
CPU time 7.41 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 07:55:36 PM PDT 24
Peak memory 233076 kb
Host smart-a674ce01-08c0-4fa4-adf6-ee0af259800d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502298030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1502298030
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.501462104
Short name T925
Test name
Test status
Simulation time 12834616864 ps
CPU time 26.7 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 07:55:55 PM PDT 24
Peak memory 233140 kb
Host smart-da3b2efc-d619-4f38-a927-bd7a556f46a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501462104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.501462104
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2435915976
Short name T281
Test name
Test status
Simulation time 5417978634 ps
CPU time 6.05 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:32 PM PDT 24
Peak memory 233212 kb
Host smart-180a73de-d83f-40c4-b02d-8cbcbefdee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435915976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2435915976
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4048069448
Short name T659
Test name
Test status
Simulation time 722274732 ps
CPU time 5.98 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:32 PM PDT 24
Peak memory 232708 kb
Host smart-2e9f1d8e-9a18-415b-b543-b5beed8eb9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048069448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4048069448
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3874589014
Short name T563
Test name
Test status
Simulation time 335895622 ps
CPU time 4.1 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 07:55:32 PM PDT 24
Peak memory 220484 kb
Host smart-e0fc4e28-3060-4a0d-8a52-3beef6a09e41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3874589014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3874589014
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3578365611
Short name T54
Test name
Test status
Simulation time 16743153473 ps
CPU time 100.04 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:57:06 PM PDT 24
Peak memory 252208 kb
Host smart-76b89c5a-5b2d-42d4-9d57-2cf77578bc23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578365611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3578365611
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2431728043
Short name T315
Test name
Test status
Simulation time 3235266987 ps
CPU time 31.84 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:59 PM PDT 24
Peak memory 218852 kb
Host smart-cd9074e9-e7ab-448e-8d68-aab9bf627303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431728043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2431728043
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2072695587
Short name T490
Test name
Test status
Simulation time 32844407088 ps
CPU time 20.99 seconds
Started Aug 09 07:55:30 PM PDT 24
Finished Aug 09 07:55:51 PM PDT 24
Peak memory 217560 kb
Host smart-9329bb77-d6b7-4965-a3aa-8b138c926d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072695587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2072695587
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3428579663
Short name T326
Test name
Test status
Simulation time 29700579 ps
CPU time 0.67 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 07:55:29 PM PDT 24
Peak memory 205920 kb
Host smart-edf2b528-24df-4485-8a30-e2f3212d5de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428579663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3428579663
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.456861135
Short name T986
Test name
Test status
Simulation time 42978679 ps
CPU time 0.78 seconds
Started Aug 09 07:55:26 PM PDT 24
Finished Aug 09 07:55:27 PM PDT 24
Peak memory 205932 kb
Host smart-0fd3377a-6c07-4c12-b4e8-4c6f6d99ca4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456861135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.456861135
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3937870690
Short name T374
Test name
Test status
Simulation time 154430157 ps
CPU time 3.61 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:31 PM PDT 24
Peak memory 241292 kb
Host smart-9f00bd62-e874-490a-8aed-87632397b835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937870690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3937870690
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3525750473
Short name T952
Test name
Test status
Simulation time 30882767 ps
CPU time 0.73 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 07:55:29 PM PDT 24
Peak memory 205256 kb
Host smart-a558df9a-b70c-4e7d-97e8-3213f08a8832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525750473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3525750473
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3939914275
Short name T656
Test name
Test status
Simulation time 4773678614 ps
CPU time 9.24 seconds
Started Aug 09 07:55:30 PM PDT 24
Finished Aug 09 07:55:39 PM PDT 24
Peak memory 233060 kb
Host smart-c166831f-5d9d-4300-9b4e-82b1480bca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939914275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3939914275
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2347238076
Short name T735
Test name
Test status
Simulation time 24723697 ps
CPU time 0.79 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 206980 kb
Host smart-623717bf-c67f-4ca9-827e-6f28cf305bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347238076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2347238076
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4027027678
Short name T288
Test name
Test status
Simulation time 8714970573 ps
CPU time 46.08 seconds
Started Aug 09 07:55:33 PM PDT 24
Finished Aug 09 07:56:19 PM PDT 24
Peak memory 251456 kb
Host smart-d53d2a69-dceb-4832-803d-7a3c63bad30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027027678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4027027678
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1210512447
Short name T473
Test name
Test status
Simulation time 1050148489 ps
CPU time 11.93 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:41 PM PDT 24
Peak memory 233120 kb
Host smart-8950e0a4-b83f-41c0-9462-63d86c2a6b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210512447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1210512447
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1024123491
Short name T212
Test name
Test status
Simulation time 7098293784 ps
CPU time 17.71 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:55:45 PM PDT 24
Peak memory 233148 kb
Host smart-fd0472fe-226d-42a0-b384-004bc700614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024123491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1024123491
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2793374545
Short name T277
Test name
Test status
Simulation time 780698778 ps
CPU time 16.7 seconds
Started Aug 09 07:55:32 PM PDT 24
Finished Aug 09 07:55:49 PM PDT 24
Peak memory 235456 kb
Host smart-51055476-5e07-4801-82d4-4d88e38469d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793374545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2793374545
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.835293955
Short name T264
Test name
Test status
Simulation time 446542705 ps
CPU time 4.44 seconds
Started Aug 09 07:55:30 PM PDT 24
Finished Aug 09 07:55:35 PM PDT 24
Peak memory 233072 kb
Host smart-480ec839-6a0e-427e-a87f-5ba65e0cb6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835293955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.835293955
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.600779899
Short name T894
Test name
Test status
Simulation time 33843510 ps
CPU time 2.49 seconds
Started Aug 09 07:55:33 PM PDT 24
Finished Aug 09 07:55:35 PM PDT 24
Peak memory 232776 kb
Host smart-7b9c7c65-016b-4b2c-9858-3ffed7fb79df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600779899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.600779899
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3634888835
Short name T622
Test name
Test status
Simulation time 14131768085 ps
CPU time 14.06 seconds
Started Aug 09 07:55:32 PM PDT 24
Finished Aug 09 07:55:46 PM PDT 24
Peak memory 222600 kb
Host smart-bb80678d-2cca-4380-ba95-752451d2efdc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3634888835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3634888835
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1442932166
Short name T146
Test name
Test status
Simulation time 24507792076 ps
CPU time 248.36 seconds
Started Aug 09 07:55:30 PM PDT 24
Finished Aug 09 07:59:38 PM PDT 24
Peak memory 266532 kb
Host smart-ef61dcfa-7b1c-4860-ac1f-6b99d40c7aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442932166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1442932166
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2895084514
Short name T551
Test name
Test status
Simulation time 2106203879 ps
CPU time 11.33 seconds
Started Aug 09 07:55:34 PM PDT 24
Finished Aug 09 07:55:46 PM PDT 24
Peak memory 216552 kb
Host smart-08a4d15e-6670-4212-a491-0b1d32f6d124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895084514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2895084514
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4236991774
Short name T333
Test name
Test status
Simulation time 387211188 ps
CPU time 1.15 seconds
Started Aug 09 07:55:30 PM PDT 24
Finished Aug 09 07:55:31 PM PDT 24
Peak memory 208100 kb
Host smart-1cae8a46-b1ef-4cc2-81b5-8923fce7e97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236991774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4236991774
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.590283923
Short name T573
Test name
Test status
Simulation time 154629625 ps
CPU time 1.89 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:31 PM PDT 24
Peak memory 216624 kb
Host smart-46b59cc5-0e45-434b-9fa3-b13cd194843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590283923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.590283923
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2122906834
Short name T991
Test name
Test status
Simulation time 33421671 ps
CPU time 0.83 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:30 PM PDT 24
Peak memory 206324 kb
Host smart-4a800a5d-b544-4bcf-8e57-249718e91e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122906834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2122906834
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1236220501
Short name T838
Test name
Test status
Simulation time 798225040 ps
CPU time 4.76 seconds
Started Aug 09 07:55:30 PM PDT 24
Finished Aug 09 07:55:35 PM PDT 24
Peak memory 233064 kb
Host smart-cfca6273-3e58-47a6-b703-bacca5efdc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236220501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1236220501
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2303965511
Short name T65
Test name
Test status
Simulation time 43650574 ps
CPU time 0.76 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:55:39 PM PDT 24
Peak memory 205248 kb
Host smart-1a6de28a-a78c-4dab-af9b-8df10d6a9bcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303965511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2303965511
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1769415250
Short name T922
Test name
Test status
Simulation time 927500722 ps
CPU time 8.85 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:38 PM PDT 24
Peak memory 233008 kb
Host smart-6f6b6dee-ed7a-4cd5-b1c0-457d284c5c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769415250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1769415250
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.416717809
Short name T749
Test name
Test status
Simulation time 31244967 ps
CPU time 0.79 seconds
Started Aug 09 07:55:33 PM PDT 24
Finished Aug 09 07:55:34 PM PDT 24
Peak memory 206972 kb
Host smart-be9fa690-b5e0-4199-b839-c73210fc3791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416717809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.416717809
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3797475694
Short name T680
Test name
Test status
Simulation time 3429498452 ps
CPU time 63.89 seconds
Started Aug 09 07:55:27 PM PDT 24
Finished Aug 09 07:56:31 PM PDT 24
Peak memory 257800 kb
Host smart-253cc218-cc9c-4ce5-9852-609ea8ecc11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797475694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3797475694
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4181304894
Short name T754
Test name
Test status
Simulation time 13851364821 ps
CPU time 93.46 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 07:57:02 PM PDT 24
Peak memory 253096 kb
Host smart-98f02aa1-e378-43a6-ae0d-786660b04eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181304894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4181304894
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3122612762
Short name T279
Test name
Test status
Simulation time 9526772830 ps
CPU time 148.13 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:57:58 PM PDT 24
Peak memory 270568 kb
Host smart-64e19d9a-f6c3-4d37-bf38-fc8f17276644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122612762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3122612762
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.881718774
Short name T725
Test name
Test status
Simulation time 13918214480 ps
CPU time 13.8 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 07:55:42 PM PDT 24
Peak memory 224964 kb
Host smart-7bd2460a-9356-4920-aecc-175b16ae7664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881718774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.881718774
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3409395292
Short name T773
Test name
Test status
Simulation time 2110674058 ps
CPU time 23.53 seconds
Started Aug 09 07:55:28 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 249528 kb
Host smart-f66af417-e2fc-4f51-b5f5-12bf9366c94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409395292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3409395292
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4165786528
Short name T548
Test name
Test status
Simulation time 739961946 ps
CPU time 4.32 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:33 PM PDT 24
Peak memory 224876 kb
Host smart-ba22dbe0-1af0-40b2-bf55-dd536374838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165786528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4165786528
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.478579744
Short name T980
Test name
Test status
Simulation time 3926988147 ps
CPU time 17.97 seconds
Started Aug 09 07:55:33 PM PDT 24
Finished Aug 09 07:55:51 PM PDT 24
Peak memory 241216 kb
Host smart-571c30fa-7f08-4cf1-877f-54053048e231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478579744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.478579744
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3872098962
Short name T663
Test name
Test status
Simulation time 1200458052 ps
CPU time 4.81 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:34 PM PDT 24
Peak memory 241196 kb
Host smart-ce567a95-a96a-4d30-9a12-d84eaae38b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872098962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3872098962
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1622559551
Short name T229
Test name
Test status
Simulation time 8725354979 ps
CPU time 15.45 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:44 PM PDT 24
Peak memory 233048 kb
Host smart-a79537ae-83a1-400e-b0c0-54f9ab722b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622559551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1622559551
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1394679827
Short name T425
Test name
Test status
Simulation time 167587123 ps
CPU time 3.73 seconds
Started Aug 09 07:55:25 PM PDT 24
Finished Aug 09 07:55:29 PM PDT 24
Peak memory 221892 kb
Host smart-11af7dcc-2931-4ef7-b1d0-53524a90ce34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1394679827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1394679827
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1974803189
Short name T173
Test name
Test status
Simulation time 268139096 ps
CPU time 1.13 seconds
Started Aug 09 07:55:35 PM PDT 24
Finished Aug 09 07:55:36 PM PDT 24
Peak memory 208176 kb
Host smart-9943fc38-b2ad-4647-8e03-b9ab38c382a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974803189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1974803189
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3884565235
Short name T660
Test name
Test status
Simulation time 5522778202 ps
CPU time 29.52 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:58 PM PDT 24
Peak memory 216792 kb
Host smart-39bad248-e472-49fc-963d-7efec032eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884565235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3884565235
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2124019817
Short name T580
Test name
Test status
Simulation time 29872051508 ps
CPU time 17.36 seconds
Started Aug 09 07:55:31 PM PDT 24
Finished Aug 09 07:55:49 PM PDT 24
Peak memory 216796 kb
Host smart-cb2db653-a96a-4e9e-9980-e229dea64814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124019817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2124019817
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.262994191
Short name T408
Test name
Test status
Simulation time 80176349 ps
CPU time 1.19 seconds
Started Aug 09 07:55:33 PM PDT 24
Finished Aug 09 07:55:34 PM PDT 24
Peak memory 208272 kb
Host smart-6a2ced8a-4dbf-47f3-9a86-283fa80ae91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262994191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.262994191
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2145953445
Short name T848
Test name
Test status
Simulation time 62748346 ps
CPU time 0.76 seconds
Started Aug 09 07:55:33 PM PDT 24
Finished Aug 09 07:55:33 PM PDT 24
Peak memory 206368 kb
Host smart-05f48d5c-e71b-4367-843d-19a88ed29ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145953445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2145953445
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3458790610
Short name T410
Test name
Test status
Simulation time 326290239 ps
CPU time 2.43 seconds
Started Aug 09 07:55:29 PM PDT 24
Finished Aug 09 07:55:31 PM PDT 24
Peak memory 224900 kb
Host smart-fb2a8f01-c97d-454b-97b9-59c8993f0e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458790610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3458790610
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.877627523
Short name T864
Test name
Test status
Simulation time 38549905 ps
CPU time 0.72 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:55:39 PM PDT 24
Peak memory 205248 kb
Host smart-75dcae1c-cbd1-4574-911a-c165ca2aa582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877627523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.877627523
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.124039951
Short name T662
Test name
Test status
Simulation time 622942371 ps
CPU time 5.94 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:55:44 PM PDT 24
Peak memory 233148 kb
Host smart-a7f3bf2a-57a7-432e-8f1b-35cd1728ccb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124039951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.124039951
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.593801663
Short name T466
Test name
Test status
Simulation time 69121405 ps
CPU time 0.78 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:40 PM PDT 24
Peak memory 206996 kb
Host smart-9df49589-5cc5-41d0-8f74-21b06594334a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593801663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.593801663
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.598612201
Short name T259
Test name
Test status
Simulation time 229208779887 ps
CPU time 457.94 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 08:03:16 PM PDT 24
Peak memory 266432 kb
Host smart-d813bcbf-ad47-401e-aa1a-a7834cbd5bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598612201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.598612201
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2952132147
Short name T675
Test name
Test status
Simulation time 9178756787 ps
CPU time 137.46 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:57:57 PM PDT 24
Peak memory 265264 kb
Host smart-9128c10e-2ad4-4b27-8b90-a7ecaffc55cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952132147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2952132147
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.783678189
Short name T220
Test name
Test status
Simulation time 2239671571 ps
CPU time 52.13 seconds
Started Aug 09 07:55:37 PM PDT 24
Finished Aug 09 07:56:29 PM PDT 24
Peak memory 256852 kb
Host smart-a87d696f-c4b1-48f5-be7c-d9df751ce8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783678189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.783678189
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.794681185
Short name T309
Test name
Test status
Simulation time 9558643656 ps
CPU time 17.78 seconds
Started Aug 09 07:55:36 PM PDT 24
Finished Aug 09 07:55:53 PM PDT 24
Peak memory 233112 kb
Host smart-749665a1-ada9-49db-b33f-d865bc3cbec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794681185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.794681185
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2287522148
Short name T861
Test name
Test status
Simulation time 29033484980 ps
CPU time 103.36 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:57:21 PM PDT 24
Peak memory 250624 kb
Host smart-7daf101d-bec3-4a19-ac24-2e3f6707afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287522148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2287522148
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2829241426
Short name T714
Test name
Test status
Simulation time 1235722072 ps
CPU time 14.25 seconds
Started Aug 09 07:55:37 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 233148 kb
Host smart-46387d7e-376d-4aff-989d-5e56788fda7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829241426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2829241426
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1903131037
Short name T417
Test name
Test status
Simulation time 2695529435 ps
CPU time 30.89 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:56:09 PM PDT 24
Peak memory 225000 kb
Host smart-3b007f45-7a39-4b12-bac1-61ab2966c6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903131037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1903131037
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1799383821
Short name T552
Test name
Test status
Simulation time 15400321245 ps
CPU time 15.97 seconds
Started Aug 09 07:55:37 PM PDT 24
Finished Aug 09 07:55:53 PM PDT 24
Peak memory 240632 kb
Host smart-e3b2b5cb-4f5f-4212-b862-c8198f6879f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799383821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1799383821
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2604277021
Short name T631
Test name
Test status
Simulation time 311231898 ps
CPU time 4.06 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:55:42 PM PDT 24
Peak memory 233108 kb
Host smart-9c74cee5-b70d-42e1-8522-47fb37567613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604277021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2604277021
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2074324243
Short name T37
Test name
Test status
Simulation time 942443285 ps
CPU time 5.14 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:44 PM PDT 24
Peak memory 223664 kb
Host smart-3868e081-e427-49cf-9aee-2e90e7ac43ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2074324243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2074324243
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.540177387
Short name T893
Test name
Test status
Simulation time 662764192 ps
CPU time 3.91 seconds
Started Aug 09 07:55:37 PM PDT 24
Finished Aug 09 07:55:41 PM PDT 24
Peak memory 216684 kb
Host smart-27cdc7d6-aa9b-4687-bf4a-a5cc370470b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540177387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.540177387
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1079928250
Short name T658
Test name
Test status
Simulation time 23313421 ps
CPU time 0.73 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:39 PM PDT 24
Peak memory 206088 kb
Host smart-6f16ac8d-b102-477d-8403-b9b96c548ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079928250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1079928250
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3884770690
Short name T444
Test name
Test status
Simulation time 18478892 ps
CPU time 0.8 seconds
Started Aug 09 07:55:35 PM PDT 24
Finished Aug 09 07:55:36 PM PDT 24
Peak memory 206316 kb
Host smart-e7f2e936-2489-4d73-a132-53a5caeffd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884770690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3884770690
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.800796207
Short name T879
Test name
Test status
Simulation time 67439506 ps
CPU time 0.88 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:55:39 PM PDT 24
Peak memory 206312 kb
Host smart-7b36ca30-96c4-4e82-88b0-2d2b584ad5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800796207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.800796207
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2373852587
Short name T823
Test name
Test status
Simulation time 1471279485 ps
CPU time 4.16 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:55:42 PM PDT 24
Peak memory 224848 kb
Host smart-aab21f2a-38ec-4b36-942e-b489f6a876a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373852587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2373852587
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1000664416
Short name T1007
Test name
Test status
Simulation time 35213733 ps
CPU time 0.72 seconds
Started Aug 09 07:55:40 PM PDT 24
Finished Aug 09 07:55:41 PM PDT 24
Peak memory 205796 kb
Host smart-da2fc28e-e99d-4f88-94c2-8a2df68a7731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000664416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1000664416
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3601441382
Short name T866
Test name
Test status
Simulation time 2271615244 ps
CPU time 27.67 seconds
Started Aug 09 07:55:43 PM PDT 24
Finished Aug 09 07:56:11 PM PDT 24
Peak memory 224980 kb
Host smart-820c019d-564f-45b0-b7ca-a80fec630d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601441382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3601441382
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2445729241
Short name T938
Test name
Test status
Simulation time 17397378 ps
CPU time 0.83 seconds
Started Aug 09 07:55:36 PM PDT 24
Finished Aug 09 07:55:37 PM PDT 24
Peak memory 205928 kb
Host smart-77e3acad-65a6-4428-93e8-6db53d465312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445729241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2445729241
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2508390331
Short name T199
Test name
Test status
Simulation time 3984003164 ps
CPU time 25.13 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:56:04 PM PDT 24
Peak memory 250108 kb
Host smart-f1b00540-9fd3-4ddf-b74c-d9c1ffdd4830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508390331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2508390331
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1607664558
Short name T263
Test name
Test status
Simulation time 28615091463 ps
CPU time 118.34 seconds
Started Aug 09 07:55:40 PM PDT 24
Finished Aug 09 07:57:38 PM PDT 24
Peak memory 267088 kb
Host smart-2c9a53fb-6d92-4f6a-b1cd-2a780d41bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607664558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1607664558
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4268732121
Short name T218
Test name
Test status
Simulation time 186803552426 ps
CPU time 323.34 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 08:01:07 PM PDT 24
Peak memory 254820 kb
Host smart-48bad673-bafb-4efd-bdd4-2998eb21ad7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268732121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4268732121
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1961383084
Short name T308
Test name
Test status
Simulation time 1679710883 ps
CPU time 16.41 seconds
Started Aug 09 07:55:40 PM PDT 24
Finished Aug 09 07:55:56 PM PDT 24
Peak memory 233080 kb
Host smart-5a1f0001-7185-4063-a34d-d7df23c20c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961383084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1961383084
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3415699970
Short name T623
Test name
Test status
Simulation time 717249135 ps
CPU time 8.34 seconds
Started Aug 09 07:55:37 PM PDT 24
Finished Aug 09 07:55:45 PM PDT 24
Peak memory 233040 kb
Host smart-9b1907d5-73a4-40d0-ba38-105fc6d85be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415699970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3415699970
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3459818236
Short name T514
Test name
Test status
Simulation time 1525530921 ps
CPU time 18.69 seconds
Started Aug 09 07:55:36 PM PDT 24
Finished Aug 09 07:55:54 PM PDT 24
Peak memory 234244 kb
Host smart-0050a5b6-271e-4ead-b837-abf42e199afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459818236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3459818236
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3255825783
Short name T931
Test name
Test status
Simulation time 6024421231 ps
CPU time 4.72 seconds
Started Aug 09 07:55:40 PM PDT 24
Finished Aug 09 07:55:44 PM PDT 24
Peak memory 233112 kb
Host smart-deea9fbe-579b-4498-83e6-57c0a1cc44f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255825783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3255825783
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1825131304
Short name T690
Test name
Test status
Simulation time 67104958 ps
CPU time 1.96 seconds
Started Aug 09 07:55:37 PM PDT 24
Finished Aug 09 07:55:39 PM PDT 24
Peak memory 224488 kb
Host smart-8ed8ba0f-756c-4aa5-ad49-356043723e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825131304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1825131304
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.572066884
Short name T719
Test name
Test status
Simulation time 305170115 ps
CPU time 5.69 seconds
Started Aug 09 07:55:37 PM PDT 24
Finished Aug 09 07:55:42 PM PDT 24
Peak memory 222988 kb
Host smart-913f7abd-5b1c-4500-9efb-15637f3cc0fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=572066884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.572066884
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3996918222
Short name T299
Test name
Test status
Simulation time 191375789384 ps
CPU time 960.96 seconds
Started Aug 09 07:55:42 PM PDT 24
Finished Aug 09 08:11:44 PM PDT 24
Peak memory 290608 kb
Host smart-dfb91d4c-6be4-4b00-91d9-2ab8afd47cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996918222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3996918222
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1026895108
Short name T440
Test name
Test status
Simulation time 1198402035 ps
CPU time 6.23 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:45 PM PDT 24
Peak memory 216676 kb
Host smart-ccb5887f-0d3b-459a-9699-a00e4ac4b754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026895108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1026895108
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3347203023
Short name T484
Test name
Test status
Simulation time 13692309192 ps
CPU time 8.11 seconds
Started Aug 09 07:55:38 PM PDT 24
Finished Aug 09 07:55:46 PM PDT 24
Peak memory 216792 kb
Host smart-d507ae13-3e74-4189-8ed1-c552bb70a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347203023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3347203023
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3066729589
Short name T741
Test name
Test status
Simulation time 294252068 ps
CPU time 1.12 seconds
Started Aug 09 07:55:35 PM PDT 24
Finished Aug 09 07:55:36 PM PDT 24
Peak memory 216720 kb
Host smart-10545248-93e1-44c1-bb78-cabc575ac648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066729589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3066729589
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.330587078
Short name T390
Test name
Test status
Simulation time 81701936 ps
CPU time 0.74 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:40 PM PDT 24
Peak memory 206384 kb
Host smart-f34ed154-21bf-4a12-943d-c14ca4e6f99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330587078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.330587078
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4200768306
Short name T966
Test name
Test status
Simulation time 27123210931 ps
CPU time 19.36 seconds
Started Aug 09 07:55:42 PM PDT 24
Finished Aug 09 07:56:02 PM PDT 24
Peak memory 241376 kb
Host smart-2ac4e2e4-8252-4fb5-91a4-b19f4ec3fdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200768306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4200768306
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2894445667
Short name T947
Test name
Test status
Simulation time 21397262 ps
CPU time 0.81 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:45 PM PDT 24
Peak memory 205276 kb
Host smart-5771d0dd-888e-426d-9faa-60d9dd7b1dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894445667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2894445667
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1872135441
Short name T630
Test name
Test status
Simulation time 59666026 ps
CPU time 2.97 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:47 PM PDT 24
Peak memory 233096 kb
Host smart-32a225c6-5994-44a8-9fb7-4951e6e1b455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872135441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1872135441
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1813953295
Short name T617
Test name
Test status
Simulation time 65527105 ps
CPU time 0.75 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:45 PM PDT 24
Peak memory 205956 kb
Host smart-3a8849ed-606a-401b-b544-7b0f0dbf56e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813953295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1813953295
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2993719559
Short name T782
Test name
Test status
Simulation time 16933507906 ps
CPU time 134.89 seconds
Started Aug 09 07:55:43 PM PDT 24
Finished Aug 09 07:57:58 PM PDT 24
Peak memory 252912 kb
Host smart-1f7c5295-3081-43e4-9f98-2d4ec5b50a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993719559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2993719559
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1799560857
Short name T211
Test name
Test status
Simulation time 39059096042 ps
CPU time 128.62 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:57:53 PM PDT 24
Peak memory 251472 kb
Host smart-760b5ca4-5d78-475f-8f57-31fd15b3e938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799560857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1799560857
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.775130802
Short name T654
Test name
Test status
Simulation time 3132061973 ps
CPU time 50.27 seconds
Started Aug 09 07:55:42 PM PDT 24
Finished Aug 09 07:56:33 PM PDT 24
Peak memory 254524 kb
Host smart-405f3251-74fb-47d6-a14c-bed6769e5164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775130802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.775130802
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1191767490
Short name T431
Test name
Test status
Simulation time 543549654 ps
CPU time 4.38 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:49 PM PDT 24
Peak memory 224928 kb
Host smart-ae7b7c46-c198-481a-9194-70e23df6dd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191767490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1191767490
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2868934425
Short name T627
Test name
Test status
Simulation time 478449358 ps
CPU time 4.7 seconds
Started Aug 09 07:55:41 PM PDT 24
Finished Aug 09 07:55:46 PM PDT 24
Peak memory 224876 kb
Host smart-76da9eae-8ef1-494a-8710-18ba7b0d310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868934425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2868934425
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2662639312
Short name T366
Test name
Test status
Simulation time 3780615295 ps
CPU time 22.24 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:56:06 PM PDT 24
Peak memory 239848 kb
Host smart-7d1d7235-66c2-4770-8d22-d2e81b333eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662639312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2662639312
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1758973035
Short name T539
Test name
Test status
Simulation time 969350515 ps
CPU time 7.81 seconds
Started Aug 09 07:55:43 PM PDT 24
Finished Aug 09 07:55:51 PM PDT 24
Peak memory 240280 kb
Host smart-0abe0196-6163-4e77-b57b-56f353009425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758973035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1758973035
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2911461114
Short name T468
Test name
Test status
Simulation time 975219909 ps
CPU time 5.99 seconds
Started Aug 09 07:55:42 PM PDT 24
Finished Aug 09 07:55:48 PM PDT 24
Peak memory 224916 kb
Host smart-095db169-bb95-4770-bbcf-c1a02bc6d6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911461114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2911461114
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2931045456
Short name T155
Test name
Test status
Simulation time 660030139 ps
CPU time 5.43 seconds
Started Aug 09 07:55:45 PM PDT 24
Finished Aug 09 07:55:51 PM PDT 24
Peak memory 219564 kb
Host smart-26998e19-073a-4dd0-81dc-46fe4a60e05b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2931045456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2931045456
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2594170962
Short name T943
Test name
Test status
Simulation time 814629359 ps
CPU time 1.04 seconds
Started Aug 09 07:55:41 PM PDT 24
Finished Aug 09 07:55:42 PM PDT 24
Peak memory 207124 kb
Host smart-ca8847b2-8ae1-460c-a49f-4d84fb0823b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594170962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2594170962
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3887439609
Short name T483
Test name
Test status
Simulation time 10718373919 ps
CPU time 9.03 seconds
Started Aug 09 07:55:43 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 216776 kb
Host smart-9233e838-a869-48ba-82f9-816d163f020d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887439609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3887439609
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2371592601
Short name T583
Test name
Test status
Simulation time 8744426051 ps
CPU time 8.55 seconds
Started Aug 09 07:55:43 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 217012 kb
Host smart-faad42e9-f80d-45f3-bde7-ba992c9fe919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371592601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2371592601
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1453212618
Short name T80
Test name
Test status
Simulation time 34018281 ps
CPU time 1.18 seconds
Started Aug 09 07:55:37 PM PDT 24
Finished Aug 09 07:55:39 PM PDT 24
Peak memory 208456 kb
Host smart-eb48c2db-2928-4dc9-8dff-a2d12545ab4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453212618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1453212618
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2885104452
Short name T833
Test name
Test status
Simulation time 31099314 ps
CPU time 0.76 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:44 PM PDT 24
Peak memory 206328 kb
Host smart-5a1f1c30-5d89-4554-95ab-dff3c309ba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885104452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2885104452
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.931720504
Short name T247
Test name
Test status
Simulation time 1025214008 ps
CPU time 5 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:49 PM PDT 24
Peak memory 224864 kb
Host smart-e232e807-f6d2-4ed3-9762-be84ff2d2096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931720504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.931720504
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2365793996
Short name T835
Test name
Test status
Simulation time 12180243 ps
CPU time 0.72 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:54:37 PM PDT 24
Peak memory 205272 kb
Host smart-fb892f14-c584-4098-a428-d7ed556ab4e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365793996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
365793996
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1827570422
Short name T77
Test name
Test status
Simulation time 33624650 ps
CPU time 2.48 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:34 PM PDT 24
Peak memory 233072 kb
Host smart-de359323-7eab-4903-9421-817031ba11d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827570422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1827570422
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1734774542
Short name T502
Test name
Test status
Simulation time 38806376 ps
CPU time 0.75 seconds
Started Aug 09 07:54:28 PM PDT 24
Finished Aug 09 07:54:28 PM PDT 24
Peak memory 206948 kb
Host smart-2e068689-0861-4163-b9f2-1744e3eba682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734774542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1734774542
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2840061460
Short name T3
Test name
Test status
Simulation time 21898021828 ps
CPU time 116.43 seconds
Started Aug 09 07:54:28 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 264712 kb
Host smart-8b8ae96f-e424-4297-939e-445992997f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840061460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2840061460
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3218331598
Short name T285
Test name
Test status
Simulation time 6222472399 ps
CPU time 57.69 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:55:34 PM PDT 24
Peak memory 257564 kb
Host smart-feb5a445-bc99-4bc0-b5d3-2a401fbe8fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218331598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3218331598
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.77209119
Short name T25
Test name
Test status
Simulation time 24198592642 ps
CPU time 222.78 seconds
Started Aug 09 07:54:27 PM PDT 24
Finished Aug 09 07:58:10 PM PDT 24
Peak memory 249552 kb
Host smart-97f806a7-476a-4d1b-81d2-35ad2d0d0a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77209119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.77209119
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2329198093
Short name T867
Test name
Test status
Simulation time 500390995 ps
CPU time 7.07 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:38 PM PDT 24
Peak memory 235400 kb
Host smart-ef3d40d6-26bf-4166-9b0e-0002b6021235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329198093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2329198093
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2254525277
Short name T349
Test name
Test status
Simulation time 7122827176 ps
CPU time 25.07 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 241340 kb
Host smart-a4f9b2a7-c06c-45fc-9de7-868457d0e5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254525277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2254525277
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3871208568
Short name T702
Test name
Test status
Simulation time 1039433193 ps
CPU time 3.77 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:39 PM PDT 24
Peak memory 224888 kb
Host smart-2cccecbd-0c4d-4b86-9379-0517fb729a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871208568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3871208568
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1273054867
Short name T847
Test name
Test status
Simulation time 4333602315 ps
CPU time 11.69 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:43 PM PDT 24
Peak memory 233136 kb
Host smart-9fb08906-765d-44c5-98b0-eaf2faf2f9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273054867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1273054867
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.66686676
Short name T574
Test name
Test status
Simulation time 7371955695 ps
CPU time 6.83 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:38 PM PDT 24
Peak memory 241176 kb
Host smart-9a634c48-c27b-4d09-a10e-536ef145ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66686676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.66686676
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2621116602
Short name T508
Test name
Test status
Simulation time 265283900 ps
CPU time 3.68 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:34 PM PDT 24
Peak memory 224756 kb
Host smart-2a625581-f042-49eb-a1e9-6188af15bece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621116602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2621116602
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1678656394
Short name T153
Test name
Test status
Simulation time 6208346971 ps
CPU time 12.18 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 07:54:42 PM PDT 24
Peak memory 220952 kb
Host smart-957d9994-6dd3-460f-a728-2e4006f680a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1678656394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1678656394
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.87184890
Short name T73
Test name
Test status
Simulation time 319220370 ps
CPU time 1.15 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:32 PM PDT 24
Peak memory 236820 kb
Host smart-ff4c1814-7ad5-4f34-b0db-c8a84d28eef1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87184890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.87184890
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.339358763
Short name T559
Test name
Test status
Simulation time 198470344 ps
CPU time 1.1 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 07:54:30 PM PDT 24
Peak memory 208012 kb
Host smart-0e57d66b-54e8-4bc7-b5cf-643d2b885c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339358763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.339358763
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.426983527
Short name T645
Test name
Test status
Simulation time 2121295586 ps
CPU time 21.76 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:52 PM PDT 24
Peak memory 216740 kb
Host smart-0f327963-1731-4756-8306-3af56b332630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426983527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.426983527
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.323073539
Short name T954
Test name
Test status
Simulation time 2722858929 ps
CPU time 4.94 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:36 PM PDT 24
Peak memory 216644 kb
Host smart-98b21818-de35-4791-85a4-8ecb69b0eb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323073539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.323073539
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.216621377
Short name T758
Test name
Test status
Simulation time 134069293 ps
CPU time 1.44 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:32 PM PDT 24
Peak memory 216604 kb
Host smart-b3d19ecf-fde7-4ae9-9988-523e5d94aec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216621377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.216621377
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2548862101
Short name T766
Test name
Test status
Simulation time 65904033 ps
CPU time 0.91 seconds
Started Aug 09 07:54:32 PM PDT 24
Finished Aug 09 07:54:33 PM PDT 24
Peak memory 206604 kb
Host smart-4858a067-8d77-48c3-ae3a-5ec768baf10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548862101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2548862101
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2408623086
Short name T1006
Test name
Test status
Simulation time 922518791 ps
CPU time 12.17 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:44 PM PDT 24
Peak memory 235372 kb
Host smart-e21143b3-c0d1-47f9-8d53-46b2fb2fad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408623086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2408623086
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2293628767
Short name T462
Test name
Test status
Simulation time 53433600 ps
CPU time 0.74 seconds
Started Aug 09 07:55:42 PM PDT 24
Finished Aug 09 07:55:43 PM PDT 24
Peak memory 205892 kb
Host smart-31b11753-c4a1-4666-9858-3905b2cc5204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293628767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2293628767
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2710144380
Short name T963
Test name
Test status
Simulation time 1523923106 ps
CPU time 4.74 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:49 PM PDT 24
Peak memory 233092 kb
Host smart-18b7a039-2f5b-40a8-a00a-6de0ff3dadfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710144380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2710144380
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3267298887
Short name T405
Test name
Test status
Simulation time 15612819 ps
CPU time 0.76 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:45 PM PDT 24
Peak memory 207296 kb
Host smart-340538d7-ef69-424c-8c80-41f703014176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267298887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3267298887
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2607650283
Short name T869
Test name
Test status
Simulation time 54283430475 ps
CPU time 115.11 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:57:39 PM PDT 24
Peak memory 241360 kb
Host smart-68e7ad08-9887-44df-a407-9ffa7eec4331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607650283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2607650283
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2703543374
Short name T238
Test name
Test status
Simulation time 24733979545 ps
CPU time 116.59 seconds
Started Aug 09 07:55:46 PM PDT 24
Finished Aug 09 07:57:43 PM PDT 24
Peak memory 239452 kb
Host smart-3f037e57-7432-4759-8479-496fac328259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703543374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2703543374
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3561908183
Short name T897
Test name
Test status
Simulation time 15058115310 ps
CPU time 54.06 seconds
Started Aug 09 07:55:46 PM PDT 24
Finished Aug 09 07:56:40 PM PDT 24
Peak memory 249792 kb
Host smart-712f2a35-576a-4a1b-bf4b-3e64feeebc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561908183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3561908183
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.910039376
Short name T616
Test name
Test status
Simulation time 2080507952 ps
CPU time 8.86 seconds
Started Aug 09 07:55:43 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 224936 kb
Host smart-dcbbb40a-03be-4297-8343-34f8d1ac413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910039376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.910039376
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3883320677
Short name T34
Test name
Test status
Simulation time 2067801844 ps
CPU time 30.58 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:56:10 PM PDT 24
Peak memory 249244 kb
Host smart-980b441b-eb40-4111-b03c-98a34ec3c232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883320677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3883320677
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.952162755
Short name T89
Test name
Test status
Simulation time 6377085072 ps
CPU time 8.26 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:48 PM PDT 24
Peak memory 233168 kb
Host smart-11fd5b1d-5736-4c54-8f1d-4696d3c5632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952162755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.952162755
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1131052810
Short name T689
Test name
Test status
Simulation time 10113163114 ps
CPU time 49.1 seconds
Started Aug 09 07:55:50 PM PDT 24
Finished Aug 09 07:56:40 PM PDT 24
Peak memory 241472 kb
Host smart-c9790026-53bd-47ef-a863-9652ff5c75f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131052810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1131052810
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1194905157
Short name T715
Test name
Test status
Simulation time 1243461859 ps
CPU time 5.66 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:50 PM PDT 24
Peak memory 224928 kb
Host smart-37eb8043-d9f8-45c5-83de-f797291b5908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194905157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1194905157
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2734899023
Short name T798
Test name
Test status
Simulation time 10975222679 ps
CPU time 6.05 seconds
Started Aug 09 07:55:46 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 225152 kb
Host smart-6a36a039-971b-4a79-a9f5-835bad1d0fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734899023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2734899023
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1197810224
Short name T1004
Test name
Test status
Simulation time 17949378243 ps
CPU time 11.13 seconds
Started Aug 09 07:55:46 PM PDT 24
Finished Aug 09 07:55:57 PM PDT 24
Peak memory 223452 kb
Host smart-950e7443-6918-44a1-a85c-3075f5fa697e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1197810224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1197810224
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2046718164
Short name T448
Test name
Test status
Simulation time 309525732 ps
CPU time 0.98 seconds
Started Aug 09 07:55:40 PM PDT 24
Finished Aug 09 07:55:41 PM PDT 24
Peak memory 207208 kb
Host smart-55b769cd-7854-4b65-a03b-dada8e8ca174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046718164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2046718164
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3967490703
Short name T451
Test name
Test status
Simulation time 14089850417 ps
CPU time 19.46 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:59 PM PDT 24
Peak memory 216760 kb
Host smart-a4c2068e-9086-4609-aa77-aaf30f1346ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967490703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3967490703
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.783707528
Short name T62
Test name
Test status
Simulation time 19588072777 ps
CPU time 5.97 seconds
Started Aug 09 07:55:45 PM PDT 24
Finished Aug 09 07:55:51 PM PDT 24
Peak memory 218048 kb
Host smart-3f72baff-be0a-4672-b4a4-a496d23bb23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783707528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.783707528
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2626592996
Short name T179
Test name
Test status
Simulation time 790291592 ps
CPU time 3.71 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:48 PM PDT 24
Peak memory 216640 kb
Host smart-ca2757fd-f265-4b5f-9dbd-44f079009707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626592996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2626592996
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1612234201
Short name T442
Test name
Test status
Simulation time 82177742 ps
CPU time 0.79 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:45 PM PDT 24
Peak memory 206348 kb
Host smart-7b72290e-1d4f-4b80-a7e3-cb4a94bcc846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612234201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1612234201
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1472658299
Short name T382
Test name
Test status
Simulation time 1804526668 ps
CPU time 8.69 seconds
Started Aug 09 07:55:45 PM PDT 24
Finished Aug 09 07:55:54 PM PDT 24
Peak memory 233384 kb
Host smart-ea72a7d3-6f11-42bd-bb36-8374a8335232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472658299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1472658299
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4014943682
Short name T822
Test name
Test status
Simulation time 2665096373 ps
CPU time 13.98 seconds
Started Aug 09 07:55:36 PM PDT 24
Finished Aug 09 07:55:50 PM PDT 24
Peak memory 224968 kb
Host smart-425447e1-aec6-4f4d-ab39-0a3bc378297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014943682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4014943682
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4188521229
Short name T537
Test name
Test status
Simulation time 64278961 ps
CPU time 0.78 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:40 PM PDT 24
Peak memory 207268 kb
Host smart-00f0498d-2f5d-4776-a2e7-4e57710bedd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188521229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4188521229
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2820283497
Short name T182
Test name
Test status
Simulation time 26354142732 ps
CPU time 105.74 seconds
Started Aug 09 07:55:49 PM PDT 24
Finished Aug 09 07:57:35 PM PDT 24
Peak memory 249556 kb
Host smart-92452a72-47b8-466e-9a16-04d2a058dbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820283497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2820283497
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.158922322
Short name T233
Test name
Test status
Simulation time 122810372943 ps
CPU time 237.85 seconds
Started Aug 09 07:55:51 PM PDT 24
Finished Aug 09 07:59:49 PM PDT 24
Peak memory 250596 kb
Host smart-980e447c-279b-4f18-ab7c-a532f17b0d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158922322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.158922322
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3110063964
Short name T311
Test name
Test status
Simulation time 5287082428 ps
CPU time 37.23 seconds
Started Aug 09 07:55:50 PM PDT 24
Finished Aug 09 07:56:27 PM PDT 24
Peak memory 249896 kb
Host smart-167a9d63-1542-4ab9-9462-ac35682806f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110063964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3110063964
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1646594578
Short name T707
Test name
Test status
Simulation time 2340199513 ps
CPU time 9.06 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:53 PM PDT 24
Peak memory 235616 kb
Host smart-3471ba07-c970-4010-9525-42a726579b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646594578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1646594578
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.206031481
Short name T195
Test name
Test status
Simulation time 105482183083 ps
CPU time 183.12 seconds
Started Aug 09 07:55:50 PM PDT 24
Finished Aug 09 07:58:53 PM PDT 24
Peak memory 241396 kb
Host smart-d2389114-5c42-4949-8396-f16744e209b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206031481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.206031481
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1468504174
Short name T730
Test name
Test status
Simulation time 454051314 ps
CPU time 4.28 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:43 PM PDT 24
Peak memory 233084 kb
Host smart-28c76b41-b251-4eb9-a124-696b0be3bddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468504174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1468504174
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3830905419
Short name T699
Test name
Test status
Simulation time 3346312678 ps
CPU time 42.38 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:56:26 PM PDT 24
Peak memory 233184 kb
Host smart-02cbf71e-88d2-443c-a9dc-c5f7a0aec955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830905419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3830905419
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.465432853
Short name T987
Test name
Test status
Simulation time 4715207728 ps
CPU time 13.73 seconds
Started Aug 09 07:55:42 PM PDT 24
Finished Aug 09 07:55:56 PM PDT 24
Peak memory 225016 kb
Host smart-8c589087-4ba7-4594-8c66-196908f2e106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465432853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.465432853
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1726576850
Short name T268
Test name
Test status
Simulation time 637893150 ps
CPU time 3.28 seconds
Started Aug 09 07:55:40 PM PDT 24
Finished Aug 09 07:55:43 PM PDT 24
Peak memory 233088 kb
Host smart-1067cc77-145d-4b8f-9bae-e263083547e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726576850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1726576850
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2452595415
Short name T501
Test name
Test status
Simulation time 1659508493 ps
CPU time 4.72 seconds
Started Aug 09 07:55:49 PM PDT 24
Finished Aug 09 07:55:54 PM PDT 24
Peak memory 223492 kb
Host smart-c922b8fc-1089-4dd5-82ab-401924442236
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2452595415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2452595415
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4058320678
Short name T788
Test name
Test status
Simulation time 10749624595 ps
CPU time 73.37 seconds
Started Aug 09 07:55:48 PM PDT 24
Finished Aug 09 07:57:02 PM PDT 24
Peak memory 254328 kb
Host smart-095c7ea8-c416-4a7c-b330-b710994eafaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058320678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4058320678
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.424817251
Short name T706
Test name
Test status
Simulation time 3016984387 ps
CPU time 10.74 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:50 PM PDT 24
Peak memory 216840 kb
Host smart-580602ae-a0ce-41f5-babb-09db3c2d3745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424817251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.424817251
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3485107392
Short name T328
Test name
Test status
Simulation time 1378229606 ps
CPU time 2.08 seconds
Started Aug 09 07:55:41 PM PDT 24
Finished Aug 09 07:55:43 PM PDT 24
Peak memory 208212 kb
Host smart-fd19138d-e6e6-4b5e-b55b-451b579fb425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485107392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3485107392
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2649252723
Short name T176
Test name
Test status
Simulation time 77050695 ps
CPU time 1.47 seconds
Started Aug 09 07:55:40 PM PDT 24
Finished Aug 09 07:55:41 PM PDT 24
Peak memory 208336 kb
Host smart-72adc6b3-f425-425f-83d1-08b82dc4d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649252723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2649252723
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1102937193
Short name T9
Test name
Test status
Simulation time 74445644 ps
CPU time 0.86 seconds
Started Aug 09 07:55:39 PM PDT 24
Finished Aug 09 07:55:40 PM PDT 24
Peak memory 206328 kb
Host smart-80c3e7ea-6638-47d9-b15f-013115eefe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102937193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1102937193
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2417232252
Short name T252
Test name
Test status
Simulation time 3015597938 ps
CPU time 7.3 seconds
Started Aug 09 07:55:44 PM PDT 24
Finished Aug 09 07:55:51 PM PDT 24
Peak memory 241364 kb
Host smart-d9f012be-1b31-4bdf-9431-26c493f87bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417232252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2417232252
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2793278437
Short name T806
Test name
Test status
Simulation time 15140696 ps
CPU time 0.8 seconds
Started Aug 09 07:55:54 PM PDT 24
Finished Aug 09 07:55:55 PM PDT 24
Peak memory 205784 kb
Host smart-b0c94ea9-a47b-46ff-81e1-5efa80e52f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793278437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2793278437
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2549301998
Short name T906
Test name
Test status
Simulation time 331730986 ps
CPU time 4.07 seconds
Started Aug 09 07:55:49 PM PDT 24
Finished Aug 09 07:55:53 PM PDT 24
Peak memory 224852 kb
Host smart-6e0e5542-e00d-4bca-80f2-6ff0da4e0e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549301998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2549301998
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.998033919
Short name T907
Test name
Test status
Simulation time 45317609 ps
CPU time 0.75 seconds
Started Aug 09 07:55:48 PM PDT 24
Finished Aug 09 07:55:49 PM PDT 24
Peak memory 205896 kb
Host smart-210c29c3-2b5f-4d83-b2ba-c4b326d49cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998033919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.998033919
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2055367291
Short name T860
Test name
Test status
Simulation time 1591347543 ps
CPU time 31.66 seconds
Started Aug 09 07:55:53 PM PDT 24
Finished Aug 09 07:56:25 PM PDT 24
Peak memory 251068 kb
Host smart-79754743-1efe-4433-998a-57d07f716388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055367291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2055367291
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.381311249
Short name T210
Test name
Test status
Simulation time 1218339756 ps
CPU time 29.34 seconds
Started Aug 09 07:55:50 PM PDT 24
Finished Aug 09 07:56:19 PM PDT 24
Peak memory 249476 kb
Host smart-b8a47eb4-473b-4f54-8c74-e3150f202596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381311249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.381311249
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.599822436
Short name T805
Test name
Test status
Simulation time 2187298872 ps
CPU time 8.85 seconds
Started Aug 09 07:55:52 PM PDT 24
Finished Aug 09 07:56:01 PM PDT 24
Peak memory 224984 kb
Host smart-16e3c767-2bd6-43dc-8440-8a259c36dbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599822436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.599822436
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2076767793
Short name T967
Test name
Test status
Simulation time 10644182787 ps
CPU time 58.38 seconds
Started Aug 09 07:55:53 PM PDT 24
Finished Aug 09 07:56:51 PM PDT 24
Peak memory 249584 kb
Host smart-764edfd9-66bc-4a56-bc36-d66a26bc8663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076767793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2076767793
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1902111274
Short name T946
Test name
Test status
Simulation time 474730057 ps
CPU time 7.2 seconds
Started Aug 09 07:55:47 PM PDT 24
Finished Aug 09 07:55:54 PM PDT 24
Peak memory 233072 kb
Host smart-17d063dd-3480-4f11-807d-a6550320215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902111274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1902111274
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4047272783
Short name T880
Test name
Test status
Simulation time 462153701 ps
CPU time 11.41 seconds
Started Aug 09 07:55:55 PM PDT 24
Finished Aug 09 07:56:06 PM PDT 24
Peak memory 233148 kb
Host smart-88d4a193-806d-42b5-8800-bb74fda8eb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047272783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4047272783
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3195248620
Short name T795
Test name
Test status
Simulation time 4118027469 ps
CPU time 8.67 seconds
Started Aug 09 07:55:50 PM PDT 24
Finished Aug 09 07:55:59 PM PDT 24
Peak memory 233156 kb
Host smart-6570a2b1-48cd-40f7-a011-3470afc4d906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195248620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3195248620
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3367393436
Short name T324
Test name
Test status
Simulation time 66244391 ps
CPU time 2.52 seconds
Started Aug 09 07:55:51 PM PDT 24
Finished Aug 09 07:55:53 PM PDT 24
Peak memory 232744 kb
Host smart-eb1bf751-41e9-4f14-a6a2-749446d828c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367393436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3367393436
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3427576253
Short name T158
Test name
Test status
Simulation time 503891469 ps
CPU time 4.04 seconds
Started Aug 09 07:55:53 PM PDT 24
Finished Aug 09 07:55:57 PM PDT 24
Peak memory 223704 kb
Host smart-69c6445d-4965-47b4-9681-dd518e00d4b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3427576253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3427576253
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2401810065
Short name T771
Test name
Test status
Simulation time 158779879 ps
CPU time 0.93 seconds
Started Aug 09 07:55:51 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 207096 kb
Host smart-328049a4-12b1-4f46-9630-261cde0cee0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401810065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2401810065
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3488518215
Short name T811
Test name
Test status
Simulation time 7171661039 ps
CPU time 21.96 seconds
Started Aug 09 07:55:54 PM PDT 24
Finished Aug 09 07:56:17 PM PDT 24
Peak memory 216652 kb
Host smart-1633961c-079d-44fa-9421-3392c463717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488518215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3488518215
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3333537456
Short name T780
Test name
Test status
Simulation time 15925898 ps
CPU time 0.72 seconds
Started Aug 09 07:55:50 PM PDT 24
Finished Aug 09 07:55:51 PM PDT 24
Peak memory 206048 kb
Host smart-2096d745-1546-45bf-858b-d7d6ba64b57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333537456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3333537456
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1278746195
Short name T653
Test name
Test status
Simulation time 274508570 ps
CPU time 4.23 seconds
Started Aug 09 07:55:51 PM PDT 24
Finished Aug 09 07:55:56 PM PDT 24
Peak memory 216612 kb
Host smart-861b4746-1619-48a6-aad1-a87529c8e77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278746195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1278746195
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1202121968
Short name T479
Test name
Test status
Simulation time 472507922 ps
CPU time 0.85 seconds
Started Aug 09 07:55:49 PM PDT 24
Finished Aug 09 07:55:50 PM PDT 24
Peak memory 206340 kb
Host smart-b9468334-d305-4ea6-a5f3-bf4af61fb423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202121968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1202121968
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3241586432
Short name T137
Test name
Test status
Simulation time 33485069 ps
CPU time 2.33 seconds
Started Aug 09 07:55:53 PM PDT 24
Finished Aug 09 07:55:55 PM PDT 24
Peak memory 234768 kb
Host smart-1e81cf82-9d9a-4103-9321-67d2b27ab25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241586432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3241586432
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2275105283
Short name T769
Test name
Test status
Simulation time 12355064 ps
CPU time 0.73 seconds
Started Aug 09 07:55:56 PM PDT 24
Finished Aug 09 07:55:56 PM PDT 24
Peak memory 205296 kb
Host smart-ddba758e-9f8e-4feb-b2e5-1aaa57cd0184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275105283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2275105283
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.231938285
Short name T441
Test name
Test status
Simulation time 3074090248 ps
CPU time 19.07 seconds
Started Aug 09 07:55:55 PM PDT 24
Finished Aug 09 07:56:14 PM PDT 24
Peak memory 224992 kb
Host smart-bcec24e6-2724-48a0-81dc-24c2025ff3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231938285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.231938285
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1101493110
Short name T589
Test name
Test status
Simulation time 26504845 ps
CPU time 0.73 seconds
Started Aug 09 07:55:50 PM PDT 24
Finished Aug 09 07:55:51 PM PDT 24
Peak memory 205936 kb
Host smart-c2453cf2-5d3e-4371-a1cf-b714049fb7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101493110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1101493110
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.431636482
Short name T181
Test name
Test status
Simulation time 7591727157 ps
CPU time 80.81 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:57:18 PM PDT 24
Peak memory 256412 kb
Host smart-7b43aa18-492a-46b7-8a4b-f6bb51f3ba28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431636482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.431636482
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1406305837
Short name T474
Test name
Test status
Simulation time 4141725055 ps
CPU time 52.33 seconds
Started Aug 09 07:55:59 PM PDT 24
Finished Aug 09 07:56:51 PM PDT 24
Peak memory 234140 kb
Host smart-f921b967-d651-4da9-8072-6556f182dc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406305837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1406305837
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1380070666
Short name T710
Test name
Test status
Simulation time 4770469725 ps
CPU time 77.18 seconds
Started Aug 09 07:55:59 PM PDT 24
Finished Aug 09 07:57:16 PM PDT 24
Peak memory 249612 kb
Host smart-2e3e643f-df39-4305-a710-1c3217337da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380070666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1380070666
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.627629691
Short name T300
Test name
Test status
Simulation time 744460701 ps
CPU time 13.96 seconds
Started Aug 09 07:55:56 PM PDT 24
Finished Aug 09 07:56:10 PM PDT 24
Peak memory 234180 kb
Host smart-0188521e-8b92-4f2e-919d-ee41c750e4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627629691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.627629691
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3822303848
Short name T96
Test name
Test status
Simulation time 22651122800 ps
CPU time 132.15 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:58:09 PM PDT 24
Peak memory 249572 kb
Host smart-7167e32e-0bad-43da-9a0a-7340b383e556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822303848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3822303848
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3109802720
Short name T872
Test name
Test status
Simulation time 4969405980 ps
CPU time 17.32 seconds
Started Aug 09 07:55:55 PM PDT 24
Finished Aug 09 07:56:12 PM PDT 24
Peak memory 233208 kb
Host smart-73956f83-2577-41fd-b6c2-e5c0ef56c3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109802720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3109802720
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3615607912
Short name T767
Test name
Test status
Simulation time 210666041 ps
CPU time 2.57 seconds
Started Aug 09 07:55:54 PM PDT 24
Finished Aug 09 07:55:57 PM PDT 24
Peak memory 232780 kb
Host smart-24218fa4-114b-486c-a552-0071bbf902bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615607912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3615607912
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3890592394
Short name T458
Test name
Test status
Simulation time 598835139 ps
CPU time 4.24 seconds
Started Aug 09 07:55:54 PM PDT 24
Finished Aug 09 07:55:59 PM PDT 24
Peak memory 233140 kb
Host smart-d71fce05-4e71-4a18-ba30-37381f174a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890592394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3890592394
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2558891706
Short name T874
Test name
Test status
Simulation time 2450268843 ps
CPU time 13.29 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:56:11 PM PDT 24
Peak memory 241316 kb
Host smart-8bc7664b-7cba-4838-a0b6-c82df6feb2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558891706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2558891706
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3383895740
Short name T596
Test name
Test status
Simulation time 1846598311 ps
CPU time 17.14 seconds
Started Aug 09 07:55:56 PM PDT 24
Finished Aug 09 07:56:13 PM PDT 24
Peak memory 220784 kb
Host smart-cfee4d68-9666-40ca-a9fb-ed0bbbbeed08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3383895740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3383895740
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2421022590
Short name T17
Test name
Test status
Simulation time 72342493 ps
CPU time 0.99 seconds
Started Aug 09 07:55:55 PM PDT 24
Finished Aug 09 07:55:57 PM PDT 24
Peak memory 208148 kb
Host smart-1cdfd03e-448c-4647-939f-514c2b84c743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421022590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2421022590
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2772000744
Short name T518
Test name
Test status
Simulation time 477526168 ps
CPU time 3.16 seconds
Started Aug 09 07:55:51 PM PDT 24
Finished Aug 09 07:55:54 PM PDT 24
Peak memory 217656 kb
Host smart-d5bc44bd-6489-4504-9e39-74c360e1c68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772000744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2772000744
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1030721264
Short name T348
Test name
Test status
Simulation time 883722320 ps
CPU time 4.7 seconds
Started Aug 09 07:55:53 PM PDT 24
Finished Aug 09 07:55:58 PM PDT 24
Peak memory 216556 kb
Host smart-84ce4bf3-823f-4bcf-ae08-05332ceeaa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030721264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1030721264
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3730431866
Short name T747
Test name
Test status
Simulation time 45382047 ps
CPU time 1.33 seconds
Started Aug 09 07:55:53 PM PDT 24
Finished Aug 09 07:55:54 PM PDT 24
Peak memory 208456 kb
Host smart-bf853bdf-90e9-41b5-97e4-ad65d8ee1ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730431866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3730431866
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2587420238
Short name T343
Test name
Test status
Simulation time 31991676 ps
CPU time 0.86 seconds
Started Aug 09 07:55:55 PM PDT 24
Finished Aug 09 07:55:56 PM PDT 24
Peak memory 207380 kb
Host smart-306af28a-5719-4430-abb4-922657e6e017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587420238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2587420238
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1740022592
Short name T774
Test name
Test status
Simulation time 2288762502 ps
CPU time 5.81 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:56:03 PM PDT 24
Peak memory 224984 kb
Host smart-34536609-de19-4d8b-b662-676df21a6e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740022592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1740022592
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1594179606
Short name T402
Test name
Test status
Simulation time 22384464 ps
CPU time 0.81 seconds
Started Aug 09 07:55:59 PM PDT 24
Finished Aug 09 07:56:00 PM PDT 24
Peak memory 205236 kb
Host smart-21dace37-9d67-4b05-9835-10dcbf73389c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594179606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1594179606
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2291752918
Short name T269
Test name
Test status
Simulation time 548336060 ps
CPU time 6.59 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:56:04 PM PDT 24
Peak memory 224792 kb
Host smart-6531b471-f76a-4f23-a12a-3718e94dc2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291752918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2291752918
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4269579081
Short name T419
Test name
Test status
Simulation time 20460227 ps
CPU time 0.79 seconds
Started Aug 09 07:55:56 PM PDT 24
Finished Aug 09 07:55:57 PM PDT 24
Peak memory 206936 kb
Host smart-96f558fd-8ec6-4d28-9c9e-ae2a32de2874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269579081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4269579081
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1745275497
Short name T496
Test name
Test status
Simulation time 58458837237 ps
CPU time 196.36 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:59:14 PM PDT 24
Peak memory 250784 kb
Host smart-e21068ac-b9c6-4c9c-a522-5be5d4482ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745275497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1745275497
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2861131659
Short name T206
Test name
Test status
Simulation time 5254866301 ps
CPU time 20.45 seconds
Started Aug 09 07:56:04 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 222352 kb
Host smart-745af98b-3a74-4ed6-a81a-6174f376dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861131659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2861131659
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2640796835
Short name T29
Test name
Test status
Simulation time 23126281191 ps
CPU time 33.36 seconds
Started Aug 09 07:56:04 PM PDT 24
Finished Aug 09 07:56:37 PM PDT 24
Peak memory 217780 kb
Host smart-6cced87f-a984-412d-b0e9-c34280d5ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640796835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2640796835
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3326169337
Short name T876
Test name
Test status
Simulation time 1116856086 ps
CPU time 10.22 seconds
Started Aug 09 07:55:59 PM PDT 24
Finished Aug 09 07:56:10 PM PDT 24
Peak memory 233104 kb
Host smart-6e29ec30-c0a1-4e26-b25b-3e8a61d38553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326169337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3326169337
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.240656138
Short name T618
Test name
Test status
Simulation time 64845335922 ps
CPU time 115.22 seconds
Started Aug 09 07:56:00 PM PDT 24
Finished Aug 09 07:57:55 PM PDT 24
Peak memory 249616 kb
Host smart-f5a4d3a9-e9c8-4c55-a0ef-05e0f04069ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240656138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.240656138
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1441391367
Short name T608
Test name
Test status
Simulation time 6905279713 ps
CPU time 17.83 seconds
Started Aug 09 07:56:04 PM PDT 24
Finished Aug 09 07:56:22 PM PDT 24
Peak memory 224932 kb
Host smart-f86e0e18-e156-444c-b360-35abdde790a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441391367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1441391367
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2818727650
Short name T394
Test name
Test status
Simulation time 7604600844 ps
CPU time 19.83 seconds
Started Aug 09 07:55:59 PM PDT 24
Finished Aug 09 07:56:19 PM PDT 24
Peak memory 224980 kb
Host smart-afbafdb4-b79c-4b02-8316-8b0b5ff04026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818727650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2818727650
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1586502604
Short name T214
Test name
Test status
Simulation time 7312221836 ps
CPU time 22.06 seconds
Started Aug 09 07:56:00 PM PDT 24
Finished Aug 09 07:56:22 PM PDT 24
Peak memory 233248 kb
Host smart-593b48c7-54a6-411f-a01d-b1eae833e4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586502604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1586502604
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.147780581
Short name T480
Test name
Test status
Simulation time 122791943430 ps
CPU time 28.31 seconds
Started Aug 09 07:56:04 PM PDT 24
Finished Aug 09 07:56:32 PM PDT 24
Peak memory 224912 kb
Host smart-9dc72592-76f5-46a4-a3b2-7dd00f7b24b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147780581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.147780581
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4123693624
Short name T385
Test name
Test status
Simulation time 407481340 ps
CPU time 8.16 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:56:06 PM PDT 24
Peak memory 221216 kb
Host smart-21337ce7-ea7d-4ef9-8b4b-5a4dab26468c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4123693624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4123693624
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3768814749
Short name T836
Test name
Test status
Simulation time 6330232430 ps
CPU time 52.44 seconds
Started Aug 09 07:56:00 PM PDT 24
Finished Aug 09 07:56:53 PM PDT 24
Peak memory 248796 kb
Host smart-f077c14c-db58-4ea3-a99b-c6f79e9510b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768814749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3768814749
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.359999501
Short name T433
Test name
Test status
Simulation time 1825015595 ps
CPU time 18.97 seconds
Started Aug 09 07:55:56 PM PDT 24
Finished Aug 09 07:56:15 PM PDT 24
Peak memory 216888 kb
Host smart-904a8353-dfa7-4eb0-904a-b10f42419d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359999501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.359999501
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2051288148
Short name T443
Test name
Test status
Simulation time 5274646364 ps
CPU time 4.54 seconds
Started Aug 09 07:55:54 PM PDT 24
Finished Aug 09 07:55:59 PM PDT 24
Peak memory 216720 kb
Host smart-3f709365-2734-45d1-8817-b6b6a8012a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051288148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2051288148
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3425419105
Short name T392
Test name
Test status
Simulation time 32945175 ps
CPU time 1.82 seconds
Started Aug 09 07:56:04 PM PDT 24
Finished Aug 09 07:56:06 PM PDT 24
Peak memory 216544 kb
Host smart-339e693a-54bb-4444-8315-7e6eae1c2e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425419105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3425419105
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4258926692
Short name T557
Test name
Test status
Simulation time 47457967 ps
CPU time 0.77 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:55:58 PM PDT 24
Peak memory 206272 kb
Host smart-7316f23d-287f-45e1-a6b3-fec042ab90d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258926692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4258926692
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2845008605
Short name T531
Test name
Test status
Simulation time 23393311599 ps
CPU time 9.79 seconds
Started Aug 09 07:55:56 PM PDT 24
Finished Aug 09 07:56:06 PM PDT 24
Peak memory 233200 kb
Host smart-23594b68-4398-4b1f-8335-9d18935ae191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845008605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2845008605
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3672314804
Short name T384
Test name
Test status
Simulation time 19574919 ps
CPU time 0.71 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:08 PM PDT 24
Peak memory 205296 kb
Host smart-e5868c5d-891d-438d-a47a-4bef18c6941f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672314804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3672314804
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1280364371
Short name T400
Test name
Test status
Simulation time 899552753 ps
CPU time 4.84 seconds
Started Aug 09 07:56:06 PM PDT 24
Finished Aug 09 07:56:11 PM PDT 24
Peak memory 233076 kb
Host smart-4f4c82f1-ba93-4723-85ab-4433f53c4963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280364371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1280364371
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2960908906
Short name T561
Test name
Test status
Simulation time 22113282 ps
CPU time 0.76 seconds
Started Aug 09 07:56:01 PM PDT 24
Finished Aug 09 07:56:02 PM PDT 24
Peak memory 205928 kb
Host smart-9fea7774-a82e-446e-9c6f-04b2b257a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960908906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2960908906
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1486567297
Short name T970
Test name
Test status
Simulation time 164521588696 ps
CPU time 324.14 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 08:01:32 PM PDT 24
Peak memory 265572 kb
Host smart-421c9ad8-f872-4482-a559-ec63dc70f3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486567297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1486567297
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.285007776
Short name T942
Test name
Test status
Simulation time 4121791251 ps
CPU time 52.24 seconds
Started Aug 09 07:56:05 PM PDT 24
Finished Aug 09 07:56:58 PM PDT 24
Peak memory 251092 kb
Host smart-127bedc1-8648-4513-9c55-e145198c044c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285007776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.285007776
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2935540578
Short name T280
Test name
Test status
Simulation time 64836685315 ps
CPU time 641.3 seconds
Started Aug 09 07:56:11 PM PDT 24
Finished Aug 09 08:06:52 PM PDT 24
Peak memory 268036 kb
Host smart-cf215886-d1ff-4e26-b4d7-3f811287e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935540578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2935540578
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.228595375
Short name T310
Test name
Test status
Simulation time 753307963 ps
CPU time 13.15 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:20 PM PDT 24
Peak memory 232180 kb
Host smart-1ceb23ce-675d-4afe-8d35-1fd1bac7250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228595375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.228595375
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1680323294
Short name T652
Test name
Test status
Simulation time 2420363303 ps
CPU time 24.76 seconds
Started Aug 09 07:56:05 PM PDT 24
Finished Aug 09 07:56:30 PM PDT 24
Peak memory 249608 kb
Host smart-66d08ed6-60cf-4474-ab5c-3d3d502e8ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680323294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1680323294
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.177900501
Short name T649
Test name
Test status
Simulation time 1474737040 ps
CPU time 4.34 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:56:01 PM PDT 24
Peak memory 224952 kb
Host smart-9a766153-1648-4f01-84c5-6aeba120faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177900501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.177900501
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1086711470
Short name T413
Test name
Test status
Simulation time 369147664 ps
CPU time 3.32 seconds
Started Aug 09 07:56:01 PM PDT 24
Finished Aug 09 07:56:04 PM PDT 24
Peak memory 224904 kb
Host smart-1f5a4e59-2346-4c3b-9b5e-c9f22bddc8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086711470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1086711470
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4098450566
Short name T999
Test name
Test status
Simulation time 1384021614 ps
CPU time 6.29 seconds
Started Aug 09 07:55:57 PM PDT 24
Finished Aug 09 07:56:03 PM PDT 24
Peak memory 233164 kb
Host smart-bb23db4a-e04f-49d2-b514-8bb9d98a54a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098450566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4098450566
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1223226228
Short name T700
Test name
Test status
Simulation time 8195358481 ps
CPU time 25.78 seconds
Started Aug 09 07:56:01 PM PDT 24
Finished Aug 09 07:56:27 PM PDT 24
Peak memory 233180 kb
Host smart-0d421ce8-4a0c-4875-8f63-ff0a57c1c7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223226228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1223226228
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3674607036
Short name T902
Test name
Test status
Simulation time 16471929373 ps
CPU time 13.33 seconds
Started Aug 09 07:56:06 PM PDT 24
Finished Aug 09 07:56:20 PM PDT 24
Peak memory 222032 kb
Host smart-9f457c7f-2ea2-4f56-ba1e-e5e1391de5fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3674607036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3674607036
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3878181984
Short name T19
Test name
Test status
Simulation time 21084391490 ps
CPU time 184.42 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:59:11 PM PDT 24
Peak memory 249628 kb
Host smart-e9bd538c-9f52-4823-83cd-523a96d4460c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878181984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3878181984
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3621674094
Short name T544
Test name
Test status
Simulation time 2259889420 ps
CPU time 22.98 seconds
Started Aug 09 07:56:01 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 216708 kb
Host smart-0b9aabb9-a30d-4f29-9fe3-f606f2add7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621674094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3621674094
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4205157941
Short name T639
Test name
Test status
Simulation time 26342495 ps
CPU time 0.71 seconds
Started Aug 09 07:55:59 PM PDT 24
Finished Aug 09 07:56:00 PM PDT 24
Peak memory 206068 kb
Host smart-0fac4633-247f-4372-af23-0158dba1d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205157941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4205157941
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2352457467
Short name T337
Test name
Test status
Simulation time 106402974 ps
CPU time 1.9 seconds
Started Aug 09 07:56:00 PM PDT 24
Finished Aug 09 07:56:03 PM PDT 24
Peak memory 216596 kb
Host smart-a4be41c3-b0f6-4083-9e18-ac3007d4e3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352457467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2352457467
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2653521014
Short name T386
Test name
Test status
Simulation time 46843765 ps
CPU time 0.88 seconds
Started Aug 09 07:55:59 PM PDT 24
Finished Aug 09 07:56:00 PM PDT 24
Peak memory 206312 kb
Host smart-c0182232-8147-445b-b88e-9787907165b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653521014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2653521014
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2053481425
Short name T717
Test name
Test status
Simulation time 30173742499 ps
CPU time 24.26 seconds
Started Aug 09 07:56:01 PM PDT 24
Finished Aug 09 07:56:25 PM PDT 24
Peak memory 239568 kb
Host smart-d028adde-f4a6-4f97-9711-51587951948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053481425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2053481425
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.96598782
Short name T770
Test name
Test status
Simulation time 56024654 ps
CPU time 0.76 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:07 PM PDT 24
Peak memory 206148 kb
Host smart-86888544-7ccc-4b76-b16f-d7f4000d8522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96598782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.96598782
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.317047207
Short name T258
Test name
Test status
Simulation time 103897914 ps
CPU time 3.58 seconds
Started Aug 09 07:56:06 PM PDT 24
Finished Aug 09 07:56:10 PM PDT 24
Peak memory 233064 kb
Host smart-988a96c2-b440-4622-8a64-6f249eb89b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317047207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.317047207
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1730630435
Short name T797
Test name
Test status
Simulation time 67169334 ps
CPU time 0.78 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:08 PM PDT 24
Peak memory 206964 kb
Host smart-ae623271-2912-44fb-853e-1d94f2484f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730630435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1730630435
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.780749787
Short name T995
Test name
Test status
Simulation time 4713980444 ps
CPU time 72.79 seconds
Started Aug 09 07:56:09 PM PDT 24
Finished Aug 09 07:57:22 PM PDT 24
Peak memory 255468 kb
Host smart-b03a04d1-4843-4fa2-b0cd-6d62d9969473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780749787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.780749787
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3495057239
Short name T365
Test name
Test status
Simulation time 58277849879 ps
CPU time 193.74 seconds
Started Aug 09 07:56:10 PM PDT 24
Finished Aug 09 07:59:24 PM PDT 24
Peak memory 249696 kb
Host smart-926989d8-2af4-43d0-9563-ad2469f9cce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495057239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3495057239
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2944425052
Short name T149
Test name
Test status
Simulation time 2465792673 ps
CPU time 61.03 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 07:57:09 PM PDT 24
Peak memory 253508 kb
Host smart-b08ff927-7dc0-4b3f-b5ce-33ff89521e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944425052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2944425052
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1944998881
Short name T790
Test name
Test status
Simulation time 18989015193 ps
CPU time 28.47 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:36 PM PDT 24
Peak memory 249588 kb
Host smart-eb5d1c54-eca7-4b75-939e-87b2f012ee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944998881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1944998881
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1456268069
Short name T395
Test name
Test status
Simulation time 8948221830 ps
CPU time 73.39 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:57:20 PM PDT 24
Peak memory 252524 kb
Host smart-56675bb4-e2c7-437e-bd73-1203f4b9c239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456268069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1456268069
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3972748584
Short name T909
Test name
Test status
Simulation time 876146393 ps
CPU time 11.38 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 07:56:19 PM PDT 24
Peak memory 224940 kb
Host smart-a84a8b05-4986-459c-921a-94c704b78a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972748584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3972748584
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3263977709
Short name T821
Test name
Test status
Simulation time 9402966240 ps
CPU time 26.77 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 07:56:35 PM PDT 24
Peak memory 224880 kb
Host smart-d0b76f71-b8ca-4a34-9800-deff91d4c48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263977709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3263977709
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2789496306
Short name T750
Test name
Test status
Simulation time 1781894966 ps
CPU time 6.38 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 07:56:14 PM PDT 24
Peak memory 224852 kb
Host smart-ea69c199-1c9a-4ee7-a2cd-4ae9fc861658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789496306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2789496306
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2693613957
Short name T650
Test name
Test status
Simulation time 8967801704 ps
CPU time 14.55 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:22 PM PDT 24
Peak memory 224900 kb
Host smart-1f0abc0f-fb6c-429d-b70e-88d2c33e9174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693613957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2693613957
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1161305318
Short name T927
Test name
Test status
Simulation time 327698438 ps
CPU time 3.36 seconds
Started Aug 09 07:56:06 PM PDT 24
Finished Aug 09 07:56:09 PM PDT 24
Peak memory 223268 kb
Host smart-b1ec5ce0-0af5-4c1c-aa35-61bb878d6298
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1161305318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1161305318
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3870514330
Short name T7
Test name
Test status
Simulation time 1526499256 ps
CPU time 18.76 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:26 PM PDT 24
Peak memory 216884 kb
Host smart-218fdf33-25b5-40f2-9c08-85d1733af8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870514330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3870514330
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2931229003
Short name T885
Test name
Test status
Simulation time 6005075551 ps
CPU time 16.76 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:23 PM PDT 24
Peak memory 216664 kb
Host smart-2d95318d-2b60-499b-a1b2-5a64fd6a0db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931229003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2931229003
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1824951322
Short name T693
Test name
Test status
Simulation time 58918681 ps
CPU time 1.03 seconds
Started Aug 09 07:56:05 PM PDT 24
Finished Aug 09 07:56:06 PM PDT 24
Peak memory 208240 kb
Host smart-6dab7ea1-bf33-4713-b1f3-b34a12bb37cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824951322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1824951322
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.132190179
Short name T334
Test name
Test status
Simulation time 17775911 ps
CPU time 0.72 seconds
Started Aug 09 07:56:10 PM PDT 24
Finished Aug 09 07:56:11 PM PDT 24
Peak memory 206324 kb
Host smart-bbc24ff6-4f3b-4046-9a47-faa82f3d6f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132190179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.132190179
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4024684499
Short name T720
Test name
Test status
Simulation time 4746792238 ps
CPU time 7.46 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 07:56:16 PM PDT 24
Peak memory 239712 kb
Host smart-df177204-18ff-4221-ba3b-00e8e711c3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024684499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4024684499
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3345592613
Short name T435
Test name
Test status
Simulation time 14501939 ps
CPU time 0.72 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:07 PM PDT 24
Peak memory 204084 kb
Host smart-0a8671e4-149f-4ac0-81c0-aa003ad96eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345592613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3345592613
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3452006033
Short name T198
Test name
Test status
Simulation time 271277612 ps
CPU time 3.73 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 07:56:11 PM PDT 24
Peak memory 233012 kb
Host smart-89bf137b-8155-4723-b37f-74932ea40877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452006033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3452006033
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3219732906
Short name T505
Test name
Test status
Simulation time 74727696 ps
CPU time 0.8 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 07:56:09 PM PDT 24
Peak memory 206976 kb
Host smart-5ff4b814-03e6-4c38-806c-da1e2fd25948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219732906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3219732906
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3246994015
Short name T293
Test name
Test status
Simulation time 64324321504 ps
CPU time 152.21 seconds
Started Aug 09 07:56:14 PM PDT 24
Finished Aug 09 07:58:46 PM PDT 24
Peak memory 257760 kb
Host smart-d17306bb-33c6-41c5-bb14-281fd59adc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246994015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3246994015
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3258782558
Short name T200
Test name
Test status
Simulation time 27931285560 ps
CPU time 252.18 seconds
Started Aug 09 07:56:15 PM PDT 24
Finished Aug 09 08:00:27 PM PDT 24
Peak memory 249592 kb
Host smart-74dbf107-d059-4da9-879c-20560f973f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258782558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3258782558
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.554528223
Short name T521
Test name
Test status
Simulation time 4355413286 ps
CPU time 110.6 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:57:58 PM PDT 24
Peak memory 258048 kb
Host smart-b0949eae-2ba2-48c7-8801-fd60dc9c19ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554528223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.554528223
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.608385429
Short name T800
Test name
Test status
Simulation time 31335646 ps
CPU time 2.6 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:10 PM PDT 24
Peak memory 233192 kb
Host smart-cd39ff0d-785b-422d-94c5-6aca155c6857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608385429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.608385429
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3220678200
Short name T196
Test name
Test status
Simulation time 58627456465 ps
CPU time 225.22 seconds
Started Aug 09 07:56:09 PM PDT 24
Finished Aug 09 07:59:54 PM PDT 24
Peak memory 263580 kb
Host smart-d1908d8d-e288-48de-85e9-26c07dc82111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220678200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3220678200
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.756304844
Short name T56
Test name
Test status
Simulation time 683833322 ps
CPU time 3.49 seconds
Started Aug 09 07:56:06 PM PDT 24
Finished Aug 09 07:56:09 PM PDT 24
Peak memory 233140 kb
Host smart-dad28a2f-4616-4758-a960-241979bc67bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756304844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.756304844
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1411203569
Short name T228
Test name
Test status
Simulation time 7596502269 ps
CPU time 31.25 seconds
Started Aug 09 07:56:14 PM PDT 24
Finished Aug 09 07:56:46 PM PDT 24
Peak memory 249532 kb
Host smart-e6f942ed-2642-4143-b962-76e7c1856f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411203569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1411203569
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3813028023
Short name T275
Test name
Test status
Simulation time 1651995293 ps
CPU time 9.94 seconds
Started Aug 09 07:56:06 PM PDT 24
Finished Aug 09 07:56:16 PM PDT 24
Peak memory 224852 kb
Host smart-3e0ede47-bed0-40f8-8b5d-76ae71668396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813028023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3813028023
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4153220771
Short name T536
Test name
Test status
Simulation time 1271323765 ps
CPU time 6.13 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:13 PM PDT 24
Peak memory 224836 kb
Host smart-1f47d51a-1a9a-475c-97e5-75d3de8367a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153220771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4153220771
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1496954450
Short name T900
Test name
Test status
Simulation time 103457381 ps
CPU time 4.45 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 07:56:13 PM PDT 24
Peak memory 223556 kb
Host smart-6fc9e887-3512-4688-b3ef-6c321221d785
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1496954450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1496954450
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3554066708
Short name T316
Test name
Test status
Simulation time 52049144804 ps
CPU time 137.12 seconds
Started Aug 09 07:56:14 PM PDT 24
Finished Aug 09 07:58:32 PM PDT 24
Peak memory 249616 kb
Host smart-2b5838f6-6336-43b9-b5f4-2bc276354732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554066708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3554066708
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2365259253
Short name T635
Test name
Test status
Simulation time 2181362479 ps
CPU time 14.71 seconds
Started Aug 09 07:56:06 PM PDT 24
Finished Aug 09 07:56:21 PM PDT 24
Peak memory 219604 kb
Host smart-6c7458b5-d1ce-4d4d-bf3f-838fe1922966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365259253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2365259253
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3482767195
Short name T373
Test name
Test status
Simulation time 437988627 ps
CPU time 3.1 seconds
Started Aug 09 07:56:06 PM PDT 24
Finished Aug 09 07:56:09 PM PDT 24
Peak memory 216600 kb
Host smart-e73993df-2a60-43c3-8d7c-c6843fac21f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482767195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3482767195
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3454249602
Short name T614
Test name
Test status
Simulation time 2878729166 ps
CPU time 2.07 seconds
Started Aug 09 07:56:06 PM PDT 24
Finished Aug 09 07:56:08 PM PDT 24
Peak memory 216752 kb
Host smart-751df1b8-6fba-46c1-8e88-38d29126ef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454249602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3454249602
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3816778602
Short name T437
Test name
Test status
Simulation time 136036338 ps
CPU time 0.78 seconds
Started Aug 09 07:56:07 PM PDT 24
Finished Aug 09 07:56:08 PM PDT 24
Peak memory 206332 kb
Host smart-4ddb6dca-2af8-4087-b91e-cd1c4c64028a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816778602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3816778602
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3897178899
Short name T737
Test name
Test status
Simulation time 1364283149 ps
CPU time 8.54 seconds
Started Aug 09 07:56:10 PM PDT 24
Finished Aug 09 07:56:19 PM PDT 24
Peak memory 233164 kb
Host smart-8cccf03c-7bc2-4e8f-9a16-3f8c1d830e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897178899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3897178899
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2762439417
Short name T701
Test name
Test status
Simulation time 11566486 ps
CPU time 0.73 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:56:19 PM PDT 24
Peak memory 205260 kb
Host smart-871fa4e8-5e8f-4281-9e0e-88204bbba8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762439417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2762439417
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2422054123
Short name T250
Test name
Test status
Simulation time 11075953880 ps
CPU time 24.64 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:44 PM PDT 24
Peak memory 233116 kb
Host smart-cbdf30cf-6417-4efc-8f85-a8c2265a8725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422054123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2422054123
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.939802801
Short name T636
Test name
Test status
Simulation time 110755063 ps
CPU time 0.75 seconds
Started Aug 09 07:56:10 PM PDT 24
Finished Aug 09 07:56:10 PM PDT 24
Peak memory 206972 kb
Host smart-793d4239-00b8-4e9f-995e-8594d0d6e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939802801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.939802801
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4263590926
Short name T764
Test name
Test status
Simulation time 50200997799 ps
CPU time 51.32 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:57:09 PM PDT 24
Peak memory 237124 kb
Host smart-92220ac4-673e-4ba1-9630-7890ed05fca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263590926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4263590926
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.112703409
Short name T651
Test name
Test status
Simulation time 251431928499 ps
CPU time 303.56 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 08:01:23 PM PDT 24
Peak memory 265924 kb
Host smart-4d5d21b2-f9d4-4498-b929-f7e9116aa2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112703409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.112703409
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2270701230
Short name T48
Test name
Test status
Simulation time 11216919152 ps
CPU time 164 seconds
Started Aug 09 07:56:20 PM PDT 24
Finished Aug 09 07:59:04 PM PDT 24
Peak memory 270872 kb
Host smart-a11545d7-81d5-48fd-861b-fdaa4c615469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270701230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2270701230
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4123865287
Short name T951
Test name
Test status
Simulation time 2481031343 ps
CPU time 11.68 seconds
Started Aug 09 07:56:17 PM PDT 24
Finished Aug 09 07:56:29 PM PDT 24
Peak memory 224996 kb
Host smart-5d8c44b6-2ac6-4102-9650-6e4deffb44c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123865287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4123865287
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.397953287
Short name T753
Test name
Test status
Simulation time 3236804048 ps
CPU time 9.19 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:56:27 PM PDT 24
Peak memory 224940 kb
Host smart-860ee956-907f-4fc5-adb3-5474ea42af3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397953287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.397953287
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1514109728
Short name T568
Test name
Test status
Simulation time 7030744620 ps
CPU time 67.77 seconds
Started Aug 09 07:56:15 PM PDT 24
Finished Aug 09 07:57:23 PM PDT 24
Peak memory 241108 kb
Host smart-efb3a2cc-cd67-43b6-97a9-dc5788685ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514109728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1514109728
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1078101103
Short name T859
Test name
Test status
Simulation time 2847101044 ps
CPU time 10.13 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:56:28 PM PDT 24
Peak memory 224996 kb
Host smart-4710ed16-e266-4156-b3d7-2e699793b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078101103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1078101103
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.724755490
Short name T420
Test name
Test status
Simulation time 2700424473 ps
CPU time 4.61 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 233136 kb
Host smart-c22d4a7f-d1ed-4fc3-acd8-5232544d6676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724755490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.724755490
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1458556737
Short name T716
Test name
Test status
Simulation time 128481354 ps
CPU time 3.97 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:56:22 PM PDT 24
Peak memory 221180 kb
Host smart-b640f1be-3713-4b61-81b4-c25b51c33236
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1458556737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1458556737
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2188822604
Short name T644
Test name
Test status
Simulation time 36976231143 ps
CPU time 110.17 seconds
Started Aug 09 07:56:16 PM PDT 24
Finished Aug 09 07:58:06 PM PDT 24
Peak memory 250616 kb
Host smart-d2578d0f-7428-45a3-b822-16b5fb24c315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188822604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2188822604
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4169810589
Short name T411
Test name
Test status
Simulation time 1537420872 ps
CPU time 23.79 seconds
Started Aug 09 07:56:13 PM PDT 24
Finished Aug 09 07:56:37 PM PDT 24
Peak memory 216948 kb
Host smart-7a953358-a110-44c7-bbc0-0716f75adbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169810589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4169810589
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2365168479
Short name T685
Test name
Test status
Simulation time 263063535 ps
CPU time 2.05 seconds
Started Aug 09 07:56:08 PM PDT 24
Finished Aug 09 07:56:10 PM PDT 24
Peak memory 216368 kb
Host smart-247dcc06-eb52-4e37-ab7e-8672580e2476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365168479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2365168479
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3317128399
Short name T576
Test name
Test status
Simulation time 56897677 ps
CPU time 1.19 seconds
Started Aug 09 07:56:10 PM PDT 24
Finished Aug 09 07:56:12 PM PDT 24
Peak memory 208224 kb
Host smart-5a3b000a-1e22-4a4d-96c4-0aec56e33fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317128399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3317128399
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.929597599
Short name T676
Test name
Test status
Simulation time 84864981 ps
CPU time 0.95 seconds
Started Aug 09 07:56:10 PM PDT 24
Finished Aug 09 07:56:11 PM PDT 24
Peak memory 206312 kb
Host smart-14eb98b7-0a97-4f1c-93cc-278bb1d28fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929597599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.929597599
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3969858670
Short name T849
Test name
Test status
Simulation time 4750231477 ps
CPU time 8.47 seconds
Started Aug 09 07:56:16 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 231504 kb
Host smart-49086268-2ca1-4333-a907-bdff96d2e90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969858670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3969858670
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.264865243
Short name T492
Test name
Test status
Simulation time 32548722 ps
CPU time 0.73 seconds
Started Aug 09 07:56:21 PM PDT 24
Finished Aug 09 07:56:22 PM PDT 24
Peak memory 205816 kb
Host smart-f0039fb1-c3c4-4954-9e37-b43c6a6d5619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264865243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.264865243
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2992129195
Short name T503
Test name
Test status
Simulation time 962097320 ps
CPU time 3.66 seconds
Started Aug 09 07:56:20 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 233160 kb
Host smart-f2e6f7ee-b9dc-43d2-bd2c-4d2e3c3c3e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992129195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2992129195
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3102061781
Short name T26
Test name
Test status
Simulation time 17255909 ps
CPU time 0.77 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:56:19 PM PDT 24
Peak memory 205884 kb
Host smart-7468324f-fc78-4754-af64-da377413e1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102061781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3102061781
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3611381652
Short name T667
Test name
Test status
Simulation time 4987891792 ps
CPU time 46.66 seconds
Started Aug 09 07:56:17 PM PDT 24
Finished Aug 09 07:57:04 PM PDT 24
Peak memory 252172 kb
Host smart-6244bf86-7bda-47d0-b3c5-b9c844e5e9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611381652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3611381652
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.734697632
Short name T391
Test name
Test status
Simulation time 12033487975 ps
CPU time 141.12 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:58:39 PM PDT 24
Peak memory 256632 kb
Host smart-c3380182-8cda-4089-8a26-57095bb3169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734697632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.734697632
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2639906976
Short name T53
Test name
Test status
Simulation time 168449086354 ps
CPU time 189.77 seconds
Started Aug 09 07:56:20 PM PDT 24
Finished Aug 09 07:59:30 PM PDT 24
Peak memory 253932 kb
Host smart-af376327-78bb-4103-8798-449776f3393e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639906976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2639906976
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.801631180
Short name T827
Test name
Test status
Simulation time 589368503 ps
CPU time 10.35 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:29 PM PDT 24
Peak memory 224872 kb
Host smart-bf9b4a51-4e10-4602-be7b-b075d9a9d4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801631180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.801631180
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3807066034
Short name T58
Test name
Test status
Simulation time 35947218042 ps
CPU time 144.48 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:58:43 PM PDT 24
Peak memory 256808 kb
Host smart-b2d5f31d-3ca3-4b4f-9296-9fc3ff70044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807066034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3807066034
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2670196430
Short name T455
Test name
Test status
Simulation time 491011369 ps
CPU time 6.14 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:25 PM PDT 24
Peak memory 233124 kb
Host smart-ce6eb0d7-4b1c-48cd-84e6-fea184b93325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670196430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2670196430
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.693484722
Short name T470
Test name
Test status
Simulation time 2989756344 ps
CPU time 12.54 seconds
Started Aug 09 07:56:21 PM PDT 24
Finished Aug 09 07:56:33 PM PDT 24
Peak memory 224948 kb
Host smart-05053f74-361e-4e56-830d-8935a2cff57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693484722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.693484722
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.589091131
Short name T90
Test name
Test status
Simulation time 414874820 ps
CPU time 3.42 seconds
Started Aug 09 07:56:21 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 224932 kb
Host smart-5d04b5e2-9318-411a-a79e-42300a4420df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589091131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.589091131
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.379518628
Short name T945
Test name
Test status
Simulation time 802301471 ps
CPU time 2.95 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:22 PM PDT 24
Peak memory 233140 kb
Host smart-f6808e26-cf02-40df-8269-757bae342221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379518628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.379518628
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.539044772
Short name T734
Test name
Test status
Simulation time 3867766491 ps
CPU time 13.24 seconds
Started Aug 09 07:56:16 PM PDT 24
Finished Aug 09 07:56:29 PM PDT 24
Peak memory 223624 kb
Host smart-ff4a0d4d-c397-4342-a07d-fefa27a4edb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=539044772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.539044772
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3448507464
Short name T313
Test name
Test status
Simulation time 6398276670 ps
CPU time 98.27 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:57:58 PM PDT 24
Peak memory 254592 kb
Host smart-f0144fcb-d3c4-4677-b383-77e853291ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448507464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3448507464
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.880236862
Short name T369
Test name
Test status
Simulation time 1055031963 ps
CPU time 2.64 seconds
Started Aug 09 07:56:16 PM PDT 24
Finished Aug 09 07:56:19 PM PDT 24
Peak memory 216588 kb
Host smart-92830df2-3708-49ec-b6d6-6670fd360d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880236862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.880236862
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4052397348
Short name T599
Test name
Test status
Simulation time 1480161036 ps
CPU time 3.27 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:56:22 PM PDT 24
Peak memory 216612 kb
Host smart-e551fae2-d5b5-4274-b337-2d3d01040b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052397348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4052397348
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2315000895
Short name T577
Test name
Test status
Simulation time 97293516 ps
CPU time 0.91 seconds
Started Aug 09 07:56:17 PM PDT 24
Finished Aug 09 07:56:18 PM PDT 24
Peak memory 208244 kb
Host smart-19c50b75-bb3d-413c-bdc1-617ac7ba4a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315000895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2315000895
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.105326621
Short name T81
Test name
Test status
Simulation time 19457438 ps
CPU time 0.72 seconds
Started Aug 09 07:56:17 PM PDT 24
Finished Aug 09 07:56:18 PM PDT 24
Peak memory 206344 kb
Host smart-3706fb44-6306-44c5-a2b1-156855da540b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105326621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.105326621
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.435728705
Short name T519
Test name
Test status
Simulation time 13202775204 ps
CPU time 24.97 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:44 PM PDT 24
Peak memory 233148 kb
Host smart-5ed7f5a8-6de4-4fb5-8c24-944c644d2c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435728705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.435728705
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2316420673
Short name T322
Test name
Test status
Simulation time 12383665 ps
CPU time 0.69 seconds
Started Aug 09 07:54:27 PM PDT 24
Finished Aug 09 07:54:28 PM PDT 24
Peak memory 205260 kb
Host smart-c03a2aa0-e3d4-4be0-9290-aa8f03a9d21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316420673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
316420673
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.357567963
Short name T824
Test name
Test status
Simulation time 265959881 ps
CPU time 2.65 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 07:54:32 PM PDT 24
Peak memory 224864 kb
Host smart-27ccf372-6362-4416-a1fa-4203d9d32a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357567963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.357567963
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3662188284
Short name T915
Test name
Test status
Simulation time 26272197 ps
CPU time 0.74 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:35 PM PDT 24
Peak memory 206240 kb
Host smart-256a5076-b5aa-4f73-a9f5-79814de14001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662188284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3662188284
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2036661766
Short name T1009
Test name
Test status
Simulation time 45050834450 ps
CPU time 308.43 seconds
Started Aug 09 07:54:27 PM PDT 24
Finished Aug 09 07:59:36 PM PDT 24
Peak memory 271152 kb
Host smart-972500e5-3700-4079-b1e5-eed37a147fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036661766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2036661766
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3814349174
Short name T205
Test name
Test status
Simulation time 53528415189 ps
CPU time 210.91 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:58:02 PM PDT 24
Peak memory 265384 kb
Host smart-8d6191e5-476e-48b0-b75b-b1264845f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814349174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3814349174
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3387048132
Short name T446
Test name
Test status
Simulation time 4730274247 ps
CPU time 86.03 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:55:57 PM PDT 24
Peak memory 250820 kb
Host smart-91e2d081-4cad-4488-a245-3409e207760e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387048132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3387048132
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.344323637
Short name T341
Test name
Test status
Simulation time 94022265 ps
CPU time 2.77 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:39 PM PDT 24
Peak memory 233084 kb
Host smart-d4257230-fced-494d-a940-82e98e84cd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344323637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.344323637
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2258560698
Short name T736
Test name
Test status
Simulation time 128794146984 ps
CPU time 213.03 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 07:58:02 PM PDT 24
Peak memory 252264 kb
Host smart-f8eefa11-29f6-4e05-bb7c-add96f74d96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258560698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2258560698
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1263773830
Short name T674
Test name
Test status
Simulation time 9077400409 ps
CPU time 25.48 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:55 PM PDT 24
Peak memory 224904 kb
Host smart-c3b6e96d-963f-4378-abfe-2969200acd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263773830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1263773830
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.783641579
Short name T786
Test name
Test status
Simulation time 3666477006 ps
CPU time 22.35 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:54:56 PM PDT 24
Peak memory 240824 kb
Host smart-0123b253-defb-4c8c-8b6d-bcf24fe73b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783641579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.783641579
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3631771439
Short name T985
Test name
Test status
Simulation time 4426824289 ps
CPU time 16.63 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 233120 kb
Host smart-df1cd045-18d7-48b0-b6c3-155355d8d04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631771439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3631771439
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.991004677
Short name T256
Test name
Test status
Simulation time 8738753657 ps
CPU time 11.14 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:54:45 PM PDT 24
Peak memory 240016 kb
Host smart-d1ee34bc-89b9-41fc-9946-64778108fa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991004677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.991004677
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1013539187
Short name T351
Test name
Test status
Simulation time 224720665 ps
CPU time 6.06 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:54:39 PM PDT 24
Peak memory 220772 kb
Host smart-720c99b5-ec8d-4e95-b799-ad0f1fbd1fa1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1013539187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1013539187
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.782903612
Short name T74
Test name
Test status
Simulation time 131847991 ps
CPU time 1.08 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:32 PM PDT 24
Peak memory 236256 kb
Host smart-0a28603d-d244-4b7b-a13b-c389965fb6fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782903612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.782903612
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2548328390
Short name T581
Test name
Test status
Simulation time 34183807 ps
CPU time 0.98 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 07:54:30 PM PDT 24
Peak memory 207940 kb
Host smart-a86773dd-249a-4073-81a3-be262262b42b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548328390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2548328390
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1051832916
Short name T317
Test name
Test status
Simulation time 2027830963 ps
CPU time 12.79 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:49 PM PDT 24
Peak memory 216904 kb
Host smart-dd66044b-33ea-4814-b268-b6710d8e6202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051832916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1051832916
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1850212968
Short name T27
Test name
Test status
Simulation time 23935625669 ps
CPU time 15.61 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 216616 kb
Host smart-17ffb93d-48f2-4d93-8bdc-b59ab4d2cef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850212968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1850212968
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4083305516
Short name T439
Test name
Test status
Simulation time 41141599 ps
CPU time 0.7 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:54:34 PM PDT 24
Peak memory 205984 kb
Host smart-8c8bd33e-fa0b-4652-a3c0-abce27471a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083305516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4083305516
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.106101955
Short name T904
Test name
Test status
Simulation time 125989263 ps
CPU time 0.9 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:31 PM PDT 24
Peak memory 206292 kb
Host smart-b6461389-bfff-4dde-ae73-cace41abd5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106101955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.106101955
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.454228838
Short name T941
Test name
Test status
Simulation time 36664907122 ps
CPU time 16.05 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 251888 kb
Host smart-9394a422-834b-4222-9a52-6e78213d388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454228838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.454228838
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1588020759
Short name T791
Test name
Test status
Simulation time 34477749 ps
CPU time 0.72 seconds
Started Aug 09 07:56:20 PM PDT 24
Finished Aug 09 07:56:21 PM PDT 24
Peak memory 205268 kb
Host smart-2c2717c8-3610-421e-8d74-b8a4e0930540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588020759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1588020759
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3161539076
Short name T500
Test name
Test status
Simulation time 1032147755 ps
CPU time 11.47 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:31 PM PDT 24
Peak memory 224960 kb
Host smart-a5aa48a9-f686-4883-9108-b29e0804cf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161539076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3161539076
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4046909219
Short name T397
Test name
Test status
Simulation time 27010892 ps
CPU time 0.73 seconds
Started Aug 09 07:56:16 PM PDT 24
Finished Aug 09 07:56:17 PM PDT 24
Peak memory 205768 kb
Host smart-0a45f2ae-2909-4206-bd22-093a6e4b4bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046909219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4046909219
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1951886029
Short name T692
Test name
Test status
Simulation time 7483341190 ps
CPU time 43.65 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:57:03 PM PDT 24
Peak memory 237376 kb
Host smart-aff2136a-bf34-4bc8-a769-9977250f00f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951886029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1951886029
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3827927470
Short name T242
Test name
Test status
Simulation time 9270703579 ps
CPU time 65.02 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:57:24 PM PDT 24
Peak memory 253104 kb
Host smart-0f439860-5dc8-4aec-bd29-0e975dbc2414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827927470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3827927470
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3560991688
Short name T845
Test name
Test status
Simulation time 13538609194 ps
CPU time 158.8 seconds
Started Aug 09 07:56:20 PM PDT 24
Finished Aug 09 07:58:58 PM PDT 24
Peak memory 257844 kb
Host smart-2eced57a-2974-4721-ae8b-a079d9f62748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560991688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3560991688
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1248986133
Short name T695
Test name
Test status
Simulation time 926847315 ps
CPU time 7.93 seconds
Started Aug 09 07:56:16 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 223748 kb
Host smart-9cf587b1-3596-4ab9-8f81-fc37e77ed142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248986133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1248986133
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3334167414
Short name T290
Test name
Test status
Simulation time 132584129800 ps
CPU time 315.75 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 08:01:35 PM PDT 24
Peak memory 273816 kb
Host smart-a46c7498-e5b5-4e4b-9532-155dce6edbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334167414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3334167414
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3057710307
Short name T95
Test name
Test status
Simulation time 194648867 ps
CPU time 3.89 seconds
Started Aug 09 07:56:20 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 233120 kb
Host smart-e146ffe1-85d0-4d97-86bf-79314943945c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057710307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3057710307
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1520880738
Short name T522
Test name
Test status
Simulation time 4989137105 ps
CPU time 10.65 seconds
Started Aug 09 07:56:17 PM PDT 24
Finished Aug 09 07:56:28 PM PDT 24
Peak memory 224888 kb
Host smart-108c1283-e366-44c8-a847-70f259f90c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520880738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1520880738
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.672871135
Short name T291
Test name
Test status
Simulation time 7390562535 ps
CPU time 5.75 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:25 PM PDT 24
Peak memory 224980 kb
Host smart-562dda55-ca5d-404a-a80a-5859fdc71460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672871135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.672871135
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1072491118
Short name T463
Test name
Test status
Simulation time 16529271071 ps
CPU time 18.79 seconds
Started Aug 09 07:56:20 PM PDT 24
Finished Aug 09 07:56:39 PM PDT 24
Peak memory 224960 kb
Host smart-e1f4462f-ff64-42f2-a9da-690f2cf0a51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072491118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1072491118
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2782145542
Short name T971
Test name
Test status
Simulation time 2033494364 ps
CPU time 6.86 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:56:25 PM PDT 24
Peak memory 221584 kb
Host smart-3b828fe0-b9de-4e24-bd4b-742db2bdd1eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2782145542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2782145542
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1744294950
Short name T516
Test name
Test status
Simulation time 6918008669 ps
CPU time 20.21 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:40 PM PDT 24
Peak memory 216716 kb
Host smart-f6c706e7-dc5a-4d4d-98ea-b47269bc91fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744294950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1744294950
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.996698873
Short name T932
Test name
Test status
Simulation time 6446236810 ps
CPU time 17.94 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:37 PM PDT 24
Peak memory 216724 kb
Host smart-705a0533-db5c-4179-8d8b-ed3e57097873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996698873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.996698873
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3777843253
Short name T881
Test name
Test status
Simulation time 172081482 ps
CPU time 10.51 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:30 PM PDT 24
Peak memory 216656 kb
Host smart-0543cd2d-b5fa-48b6-b88d-6b94720026ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777843253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3777843253
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.504478845
Short name T638
Test name
Test status
Simulation time 59236337 ps
CPU time 0.98 seconds
Started Aug 09 07:56:18 PM PDT 24
Finished Aug 09 07:56:19 PM PDT 24
Peak memory 207336 kb
Host smart-d9b3c87a-14e0-450a-b953-da96799979ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504478845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.504478845
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3534244712
Short name T497
Test name
Test status
Simulation time 120930235 ps
CPU time 2.17 seconds
Started Aug 09 07:56:19 PM PDT 24
Finished Aug 09 07:56:22 PM PDT 24
Peak memory 224260 kb
Host smart-67c9e124-4991-4bfb-b29c-eb31de089afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534244712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3534244712
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.156882507
Short name T883
Test name
Test status
Simulation time 21714217 ps
CPU time 0.76 seconds
Started Aug 09 07:56:26 PM PDT 24
Finished Aug 09 07:56:27 PM PDT 24
Peak memory 205748 kb
Host smart-40f7b8b9-aba8-4248-9448-770a9ef530c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156882507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.156882507
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.197045771
Short name T321
Test name
Test status
Simulation time 68131417 ps
CPU time 2.49 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:56:32 PM PDT 24
Peak memory 232820 kb
Host smart-b24ab5ca-d65a-49a3-aedb-6460afeb1f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197045771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.197045771
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.273429497
Short name T816
Test name
Test status
Simulation time 29371923 ps
CPU time 0.76 seconds
Started Aug 09 07:56:25 PM PDT 24
Finished Aug 09 07:56:26 PM PDT 24
Peak memory 206920 kb
Host smart-870d6119-6935-4efb-b088-88cf8f5c3545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273429497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.273429497
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.69926900
Short name T232
Test name
Test status
Simulation time 70643375654 ps
CPU time 89.7 seconds
Started Aug 09 07:56:31 PM PDT 24
Finished Aug 09 07:58:01 PM PDT 24
Peak memory 233072 kb
Host smart-955a499f-f02d-41d0-b9bb-d7530cccbf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69926900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.69926900
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2114949356
Short name T36
Test name
Test status
Simulation time 59606252481 ps
CPU time 112.15 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:58:21 PM PDT 24
Peak memory 255572 kb
Host smart-3b363d06-b199-45bc-9c1e-9b04e663708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114949356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2114949356
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.543075413
Short name T854
Test name
Test status
Simulation time 24759212601 ps
CPU time 68.06 seconds
Started Aug 09 07:56:27 PM PDT 24
Finished Aug 09 07:57:35 PM PDT 24
Peak memory 262576 kb
Host smart-ef0eae4d-d096-4ef3-93aa-1dcd2ad7944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543075413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.543075413
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4027932364
Short name T119
Test name
Test status
Simulation time 471291231 ps
CPU time 14.07 seconds
Started Aug 09 07:56:30 PM PDT 24
Finished Aug 09 07:56:45 PM PDT 24
Peak memory 241128 kb
Host smart-8d706d47-d024-44ef-ae4d-81bb577be38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027932364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4027932364
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2591098022
Short name T611
Test name
Test status
Simulation time 3696735874 ps
CPU time 27.05 seconds
Started Aug 09 07:56:34 PM PDT 24
Finished Aug 09 07:57:01 PM PDT 24
Peak memory 235024 kb
Host smart-a1d4170c-098a-4268-87ec-11faa9b02a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591098022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2591098022
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3946265292
Short name T748
Test name
Test status
Simulation time 91057309 ps
CPU time 2.12 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:31 PM PDT 24
Peak memory 224260 kb
Host smart-eadc9b35-3636-491b-9a5d-4197b143af86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946265292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3946265292
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3015190861
Short name T207
Test name
Test status
Simulation time 1168564904 ps
CPU time 14.71 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:43 PM PDT 24
Peak memory 241112 kb
Host smart-7e249bc0-5455-4203-8dc6-3b6c92560405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015190861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3015190861
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3721002552
Short name T495
Test name
Test status
Simulation time 161734770 ps
CPU time 4.48 seconds
Started Aug 09 07:56:34 PM PDT 24
Finished Aug 09 07:56:38 PM PDT 24
Peak memory 237196 kb
Host smart-be9fc6d3-9663-4ca6-8356-c3e3bc11139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721002552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3721002552
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3155300518
Short name T682
Test name
Test status
Simulation time 31545674 ps
CPU time 2.17 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:56:32 PM PDT 24
Peak memory 232764 kb
Host smart-2c516a18-3595-40fb-b366-f60a60c36c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155300518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3155300518
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3906575855
Short name T664
Test name
Test status
Simulation time 8613064489 ps
CPU time 12.46 seconds
Started Aug 09 07:56:27 PM PDT 24
Finished Aug 09 07:56:39 PM PDT 24
Peak memory 222256 kb
Host smart-a7eb927a-f85c-466f-9f13-fe847fcf723a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3906575855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3906575855
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1797267292
Short name T983
Test name
Test status
Simulation time 60417039 ps
CPU time 1 seconds
Started Aug 09 07:56:33 PM PDT 24
Finished Aug 09 07:56:34 PM PDT 24
Peak memory 207152 kb
Host smart-55ba41dc-faee-48b9-9eec-6dc8dd999e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797267292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1797267292
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.4035406066
Short name T917
Test name
Test status
Simulation time 4405216716 ps
CPU time 29.49 seconds
Started Aug 09 07:56:30 PM PDT 24
Finished Aug 09 07:57:00 PM PDT 24
Peak memory 216688 kb
Host smart-245666f0-f81a-4aed-b052-6a4cba6fe5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035406066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4035406066
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2796994647
Short name T368
Test name
Test status
Simulation time 10233411781 ps
CPU time 5.39 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:33 PM PDT 24
Peak memory 216692 kb
Host smart-2832606f-3a87-4d92-ae34-0cb1dcc8f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796994647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2796994647
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3729499264
Short name T477
Test name
Test status
Simulation time 1349327781 ps
CPU time 2.56 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:31 PM PDT 24
Peak memory 216588 kb
Host smart-ff4ffb60-3523-4d2a-a5d3-a34788f35eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729499264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3729499264
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1691916445
Short name T740
Test name
Test status
Simulation time 63030652 ps
CPU time 0.75 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:29 PM PDT 24
Peak memory 206324 kb
Host smart-d1642056-2cc6-4bca-ba9b-9a0dc1628ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691916445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1691916445
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1360637376
Short name T224
Test name
Test status
Simulation time 1893470905 ps
CPU time 7.94 seconds
Started Aug 09 07:56:30 PM PDT 24
Finished Aug 09 07:56:38 PM PDT 24
Peak memory 237704 kb
Host smart-634d072f-608d-47a4-8002-fe4f0f6503ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360637376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1360637376
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2503351876
Short name T1016
Test name
Test status
Simulation time 17713686 ps
CPU time 0.76 seconds
Started Aug 09 07:56:30 PM PDT 24
Finished Aug 09 07:56:31 PM PDT 24
Peak memory 205760 kb
Host smart-dddf1826-3a9c-4d5d-a450-1179eabaf875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503351876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2503351876
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.930437838
Short name T981
Test name
Test status
Simulation time 76656033 ps
CPU time 2.16 seconds
Started Aug 09 07:56:31 PM PDT 24
Finished Aug 09 07:56:33 PM PDT 24
Peak memory 224524 kb
Host smart-176b7e77-7e88-476d-9f64-aa966864686d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930437838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.930437838
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.967575541
Short name T934
Test name
Test status
Simulation time 42297113 ps
CPU time 0.74 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:56:30 PM PDT 24
Peak memory 206968 kb
Host smart-72346fd0-d132-4267-9644-673543529259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967575541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.967575541
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1251996020
Short name T842
Test name
Test status
Simulation time 23494624755 ps
CPU time 63.19 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:57:33 PM PDT 24
Peak memory 249596 kb
Host smart-79b91528-d561-40e6-bbfc-800447ba18fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251996020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1251996020
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3202498756
Short name T776
Test name
Test status
Simulation time 26199102147 ps
CPU time 217.49 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 08:00:06 PM PDT 24
Peak memory 237820 kb
Host smart-3c32da51-670f-4586-a58b-e6cc9c90b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202498756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3202498756
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1546013685
Short name T43
Test name
Test status
Simulation time 3406505560 ps
CPU time 40.55 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:57:09 PM PDT 24
Peak memory 224960 kb
Host smart-fb64b1bc-43f3-413a-baff-1f5912d5fc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546013685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1546013685
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.371737207
Short name T1010
Test name
Test status
Simulation time 1466425503 ps
CPU time 12.75 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:40 PM PDT 24
Peak memory 237048 kb
Host smart-39cc5fd0-40e9-4709-add9-f9fde43159ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371737207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.371737207
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.774769772
Short name T371
Test name
Test status
Simulation time 1388659493 ps
CPU time 9.96 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:38 PM PDT 24
Peak memory 238996 kb
Host smart-e08c3fa7-42dd-42ab-9420-a46e9c94f1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774769772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.774769772
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2893918695
Short name T694
Test name
Test status
Simulation time 2070132697 ps
CPU time 20.06 seconds
Started Aug 09 07:56:33 PM PDT 24
Finished Aug 09 07:56:53 PM PDT 24
Peak memory 224868 kb
Host smart-43722c69-9fc7-4153-9a1a-b5891136d485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893918695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2893918695
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1352350838
Short name T705
Test name
Test status
Simulation time 2752754438 ps
CPU time 9.96 seconds
Started Aug 09 07:56:32 PM PDT 24
Finished Aug 09 07:56:42 PM PDT 24
Peak memory 238520 kb
Host smart-635be9f1-7ef0-4573-8970-e71d61dbca58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352350838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1352350838
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.628845953
Short name T14
Test name
Test status
Simulation time 1367540722 ps
CPU time 11.3 seconds
Started Aug 09 07:56:25 PM PDT 24
Finished Aug 09 07:56:36 PM PDT 24
Peak memory 249084 kb
Host smart-53b179bf-2d17-40d2-8b35-363f7f6a2b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628845953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.628845953
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1154878184
Short name T875
Test name
Test status
Simulation time 1629594373 ps
CPU time 4.56 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:56:33 PM PDT 24
Peak memory 233068 kb
Host smart-6c5d55be-1147-4f7c-9879-05b68b96b667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154878184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1154878184
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2820793716
Short name T818
Test name
Test status
Simulation time 1115114755 ps
CPU time 6.52 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:56:36 PM PDT 24
Peak memory 223664 kb
Host smart-4235a6a5-2eb4-4efa-bf23-b77500985869
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2820793716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2820793716
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.556868950
Short name T472
Test name
Test status
Simulation time 29169594831 ps
CPU time 117.74 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:58:26 PM PDT 24
Peak memory 249588 kb
Host smart-50a5815a-ad4e-4e09-b5fd-6e239370b2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556868950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.556868950
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.978722754
Short name T633
Test name
Test status
Simulation time 24572705948 ps
CPU time 40.17 seconds
Started Aug 09 07:56:31 PM PDT 24
Finished Aug 09 07:57:11 PM PDT 24
Peak memory 216724 kb
Host smart-81d584f6-2e09-41bd-a5b0-d75b6f9adcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978722754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.978722754
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3262321159
Short name T340
Test name
Test status
Simulation time 1418987456 ps
CPU time 5.27 seconds
Started Aug 09 07:56:26 PM PDT 24
Finished Aug 09 07:56:32 PM PDT 24
Peak memory 216688 kb
Host smart-5448f90e-4891-4fbf-9e38-a4b23ce359da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262321159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3262321159
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2483962192
Short name T511
Test name
Test status
Simulation time 162780791 ps
CPU time 1.22 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:29 PM PDT 24
Peak memory 216392 kb
Host smart-8853ee18-2a29-4734-b942-c7ecf525d57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483962192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2483962192
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2720018493
Short name T434
Test name
Test status
Simulation time 54438529 ps
CPU time 0.81 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:56:30 PM PDT 24
Peak memory 206304 kb
Host smart-c5d7ac73-9880-4304-b13f-7f4487e01798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720018493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2720018493
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2841483845
Short name T35
Test name
Test status
Simulation time 15823102368 ps
CPU time 15.06 seconds
Started Aug 09 07:56:27 PM PDT 24
Finished Aug 09 07:56:42 PM PDT 24
Peak memory 233104 kb
Host smart-38a6b93b-dcba-47d7-b4f1-82603569e006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841483845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2841483845
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4108857703
Short name T338
Test name
Test status
Simulation time 38501143 ps
CPU time 0.7 seconds
Started Aug 09 07:56:37 PM PDT 24
Finished Aug 09 07:56:38 PM PDT 24
Peak memory 206188 kb
Host smart-d0eacd59-9cc7-4d73-bd5e-f60c403aad2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108857703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4108857703
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4234262355
Short name T727
Test name
Test status
Simulation time 856240138 ps
CPU time 6.44 seconds
Started Aug 09 07:56:34 PM PDT 24
Finished Aug 09 07:56:40 PM PDT 24
Peak memory 224864 kb
Host smart-590c6acc-1c78-407f-88a1-81bfd21d39f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234262355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4234262355
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2654221799
Short name T612
Test name
Test status
Simulation time 13796411 ps
CPU time 0.8 seconds
Started Aug 09 07:56:27 PM PDT 24
Finished Aug 09 07:56:28 PM PDT 24
Peak memory 206960 kb
Host smart-b829db58-ad6c-4163-b440-ef1c40b2ee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654221799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2654221799
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3473571699
Short name T977
Test name
Test status
Simulation time 32166189647 ps
CPU time 167.89 seconds
Started Aug 09 07:56:36 PM PDT 24
Finished Aug 09 07:59:24 PM PDT 24
Peak memory 257276 kb
Host smart-b852b95b-7d6b-425f-b87a-2bb7c4cba237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473571699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3473571699
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1540303194
Short name T262
Test name
Test status
Simulation time 10381587642 ps
CPU time 89.49 seconds
Started Aug 09 07:56:38 PM PDT 24
Finished Aug 09 07:58:07 PM PDT 24
Peak memory 253620 kb
Host smart-ebc400d0-2582-413d-be09-2bdf16e17e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540303194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1540303194
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3086214600
Short name T541
Test name
Test status
Simulation time 1309101269 ps
CPU time 4.06 seconds
Started Aug 09 07:56:31 PM PDT 24
Finished Aug 09 07:56:35 PM PDT 24
Peak memory 224876 kb
Host smart-7c07fe1b-0886-4524-8850-0bd05a3deaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086214600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3086214600
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2165583127
Short name T183
Test name
Test status
Simulation time 8254908434 ps
CPU time 67.82 seconds
Started Aug 09 07:56:26 PM PDT 24
Finished Aug 09 07:57:34 PM PDT 24
Peak memory 237968 kb
Host smart-a020c38f-7ca2-40f5-a34c-6e5336989d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165583127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2165583127
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.565313929
Short name T244
Test name
Test status
Simulation time 1186512722 ps
CPU time 7.02 seconds
Started Aug 09 07:56:30 PM PDT 24
Finished Aug 09 07:56:38 PM PDT 24
Peak memory 233068 kb
Host smart-c156294c-c853-4ab8-94be-8eed1965eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565313929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.565313929
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1659796200
Short name T605
Test name
Test status
Simulation time 33050526 ps
CPU time 2.46 seconds
Started Aug 09 07:56:34 PM PDT 24
Finished Aug 09 07:56:36 PM PDT 24
Peak memory 232724 kb
Host smart-730d1579-ab01-4e38-a23b-2876c3b6dcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659796200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1659796200
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.324045071
Short name T4
Test name
Test status
Simulation time 7714904711 ps
CPU time 6.95 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:56:36 PM PDT 24
Peak memory 233148 kb
Host smart-21925f94-0ec9-4c3e-8fe5-433c71a41464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324045071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.324045071
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1479734071
Short name T379
Test name
Test status
Simulation time 13293106378 ps
CPU time 9.99 seconds
Started Aug 09 07:56:30 PM PDT 24
Finished Aug 09 07:56:40 PM PDT 24
Peak memory 233392 kb
Host smart-4c9af7d2-da8c-4b11-af04-43b5bd2c0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479734071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1479734071
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3959014973
Short name T908
Test name
Test status
Simulation time 1053627782 ps
CPU time 9.24 seconds
Started Aug 09 07:56:36 PM PDT 24
Finished Aug 09 07:56:46 PM PDT 24
Peak memory 220848 kb
Host smart-c6258f39-c2f6-45c3-846d-c1bd5efff8f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3959014973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3959014973
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3963646321
Short name T891
Test name
Test status
Simulation time 37828480 ps
CPU time 1 seconds
Started Aug 09 07:56:37 PM PDT 24
Finished Aug 09 07:56:38 PM PDT 24
Peak memory 207908 kb
Host smart-4a2fdf8c-4d26-43f1-8569-7c9c11b84fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963646321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3963646321
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1023063857
Short name T140
Test name
Test status
Simulation time 10570519405 ps
CPU time 15.39 seconds
Started Aug 09 07:56:27 PM PDT 24
Finished Aug 09 07:56:42 PM PDT 24
Peak memory 216932 kb
Host smart-45a9e44c-b0e0-4fc3-b0b2-75499f65768e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023063857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1023063857
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2355496412
Short name T603
Test name
Test status
Simulation time 4253643756 ps
CPU time 14.99 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:44 PM PDT 24
Peak memory 216664 kb
Host smart-9de1ae2f-0a96-490d-88cd-2e808702e525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355496412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2355496412
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3456504892
Short name T469
Test name
Test status
Simulation time 100606308 ps
CPU time 1.22 seconds
Started Aug 09 07:56:29 PM PDT 24
Finished Aug 09 07:56:30 PM PDT 24
Peak memory 208216 kb
Host smart-ba08f2d1-2c6e-49e7-8ddd-8500b14d404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456504892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3456504892
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1260351062
Short name T403
Test name
Test status
Simulation time 32391928 ps
CPU time 0.77 seconds
Started Aug 09 07:56:30 PM PDT 24
Finished Aug 09 07:56:31 PM PDT 24
Peak memory 206356 kb
Host smart-cfd80174-ceb9-4910-966a-a424530051ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260351062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1260351062
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3387912785
Short name T670
Test name
Test status
Simulation time 3921620705 ps
CPU time 14.19 seconds
Started Aug 09 07:56:28 PM PDT 24
Finished Aug 09 07:56:42 PM PDT 24
Peak memory 233088 kb
Host smart-9a3bc937-8ca9-410a-abba-09988aa76fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387912785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3387912785
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3739964820
Short name T524
Test name
Test status
Simulation time 34523587 ps
CPU time 0.72 seconds
Started Aug 09 07:56:43 PM PDT 24
Finished Aug 09 07:56:44 PM PDT 24
Peak memory 205856 kb
Host smart-d7e9f700-3f9f-4ae3-87eb-ac4a240dcd22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739964820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3739964820
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.792655273
Short name T138
Test name
Test status
Simulation time 6504005721 ps
CPU time 6.55 seconds
Started Aug 09 07:56:38 PM PDT 24
Finished Aug 09 07:56:45 PM PDT 24
Peak memory 224964 kb
Host smart-96023908-3bdd-4f1b-b5d5-1b789cb67d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792655273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.792655273
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.415634851
Short name T342
Test name
Test status
Simulation time 143751736 ps
CPU time 0.75 seconds
Started Aug 09 07:56:37 PM PDT 24
Finished Aug 09 07:56:38 PM PDT 24
Peak memory 205932 kb
Host smart-7a815fe6-b814-4d6b-a3cd-c988e4e3de76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415634851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.415634851
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.707047986
Short name T972
Test name
Test status
Simulation time 11921703972 ps
CPU time 157.02 seconds
Started Aug 09 07:56:40 PM PDT 24
Finished Aug 09 07:59:17 PM PDT 24
Peak memory 264624 kb
Host smart-5156045b-c23a-43da-bbae-a3083fc8ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707047986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.707047986
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3629693180
Short name T587
Test name
Test status
Simulation time 38713947810 ps
CPU time 219.53 seconds
Started Aug 09 07:56:37 PM PDT 24
Finished Aug 09 08:00:17 PM PDT 24
Peak memory 256336 kb
Host smart-d0efddba-e50c-403b-9d2e-6b0ba7ea808e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629693180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3629693180
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3217544896
Short name T46
Test name
Test status
Simulation time 1803148499 ps
CPU time 48.15 seconds
Started Aug 09 07:56:35 PM PDT 24
Finished Aug 09 07:57:23 PM PDT 24
Peak memory 250020 kb
Host smart-b768d2df-851b-4af3-9890-9fa65c96ff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217544896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3217544896
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4254704985
Short name T152
Test name
Test status
Simulation time 1029162921 ps
CPU time 17.56 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 07:56:59 PM PDT 24
Peak memory 233120 kb
Host smart-3f38d361-93cd-49c0-9fcf-3786e4903cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254704985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4254704985
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2844855389
Short name T646
Test name
Test status
Simulation time 5311526579 ps
CPU time 11.39 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 07:56:52 PM PDT 24
Peak memory 233216 kb
Host smart-6a910dbf-5c07-4531-8c78-58cf5c16b7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844855389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2844855389
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.630073591
Short name T248
Test name
Test status
Simulation time 11522278934 ps
CPU time 21.54 seconds
Started Aug 09 07:56:40 PM PDT 24
Finished Aug 09 07:57:01 PM PDT 24
Peak memory 224928 kb
Host smart-4f4179fa-4dc8-4271-a530-877d6f5be044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630073591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.630073591
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2490798321
Short name T718
Test name
Test status
Simulation time 2626262624 ps
CPU time 2.75 seconds
Started Aug 09 07:56:36 PM PDT 24
Finished Aug 09 07:56:39 PM PDT 24
Peak memory 219308 kb
Host smart-ec6911a3-514f-47f6-abc3-24b13071d289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490798321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2490798321
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.816070878
Short name T757
Test name
Test status
Simulation time 72788600 ps
CPU time 2.25 seconds
Started Aug 09 07:56:38 PM PDT 24
Finished Aug 09 07:56:40 PM PDT 24
Peak memory 223364 kb
Host smart-65e48f53-1e23-490e-9b41-64d9399d8761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816070878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.816070878
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2432020079
Short name T481
Test name
Test status
Simulation time 116401988 ps
CPU time 4.18 seconds
Started Aug 09 07:56:39 PM PDT 24
Finished Aug 09 07:56:44 PM PDT 24
Peak memory 223412 kb
Host smart-ab5f0962-9f39-4bc4-beec-08707c1cffbb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2432020079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2432020079
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1948046485
Short name T52
Test name
Test status
Simulation time 6805643253 ps
CPU time 28.14 seconds
Started Aug 09 07:56:42 PM PDT 24
Finished Aug 09 07:57:11 PM PDT 24
Peak memory 224552 kb
Host smart-466b0c7a-f3db-43d3-8ae4-d44ced35e1d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948046485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1948046485
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2489912363
Short name T896
Test name
Test status
Simulation time 12125196723 ps
CPU time 16.07 seconds
Started Aug 09 07:56:35 PM PDT 24
Finished Aug 09 07:56:52 PM PDT 24
Peak memory 216704 kb
Host smart-01c19a75-7822-44e0-bc5c-1b3b60c4ef2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489912363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2489912363
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.500531091
Short name T364
Test name
Test status
Simulation time 5158814558 ps
CPU time 17.38 seconds
Started Aug 09 07:56:39 PM PDT 24
Finished Aug 09 07:56:56 PM PDT 24
Peak memory 216736 kb
Host smart-b705fcb4-75f5-407f-a84c-5d6bb7fcb756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500531091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.500531091
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.177125879
Short name T760
Test name
Test status
Simulation time 17913339 ps
CPU time 0.82 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 07:56:42 PM PDT 24
Peak memory 206356 kb
Host smart-b8c3535c-1dd7-417f-8aef-d58afcbb3357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177125879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.177125879
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2749999002
Short name T376
Test name
Test status
Simulation time 106006447 ps
CPU time 0.82 seconds
Started Aug 09 07:56:42 PM PDT 24
Finished Aug 09 07:56:43 PM PDT 24
Peak memory 206364 kb
Host smart-6447f12c-8762-41e2-9239-6ceb3ea1ab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749999002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2749999002
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.10740062
Short name T567
Test name
Test status
Simulation time 676726908 ps
CPU time 6.42 seconds
Started Aug 09 07:56:42 PM PDT 24
Finished Aug 09 07:56:48 PM PDT 24
Peak memory 239892 kb
Host smart-a17b8a94-bdec-423a-bd5f-b39b3f791392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10740062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.10740062
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1455079984
Short name T759
Test name
Test status
Simulation time 13091718 ps
CPU time 0.74 seconds
Started Aug 09 07:56:46 PM PDT 24
Finished Aug 09 07:56:47 PM PDT 24
Peak memory 205260 kb
Host smart-0642975a-afd9-45f8-b420-467763d1b15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455079984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1455079984
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3720373231
Short name T564
Test name
Test status
Simulation time 151485994 ps
CPU time 2.59 seconds
Started Aug 09 07:56:44 PM PDT 24
Finished Aug 09 07:56:46 PM PDT 24
Peak memory 233100 kb
Host smart-2084c5ee-5071-463b-b132-a50f7a1ba588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720373231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3720373231
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3690325974
Short name T6
Test name
Test status
Simulation time 27262436 ps
CPU time 0.84 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 07:56:42 PM PDT 24
Peak memory 205924 kb
Host smart-75b3163b-37e8-4c50-a20f-f2d38731915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690325974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3690325974
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2800405051
Short name T236
Test name
Test status
Simulation time 3290184960 ps
CPU time 18.68 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 07:57:00 PM PDT 24
Peak memory 239904 kb
Host smart-e4b9ff97-c388-42c2-ab8a-eba37680a7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800405051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2800405051
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3881073712
Short name T998
Test name
Test status
Simulation time 6975081153 ps
CPU time 144.11 seconds
Started Aug 09 07:56:36 PM PDT 24
Finished Aug 09 07:59:00 PM PDT 24
Peak memory 256596 kb
Host smart-fbbfb6e7-1d4f-426f-91cb-053117b64c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881073712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3881073712
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.131786888
Short name T784
Test name
Test status
Simulation time 42639852584 ps
CPU time 385.34 seconds
Started Aug 09 07:56:39 PM PDT 24
Finished Aug 09 08:03:04 PM PDT 24
Peak memory 256792 kb
Host smart-e671a9c7-4172-462b-805d-5d6130e95e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131786888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.131786888
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.237990903
Short name T615
Test name
Test status
Simulation time 4272137875 ps
CPU time 19.4 seconds
Started Aug 09 07:56:36 PM PDT 24
Finished Aug 09 07:56:56 PM PDT 24
Peak memory 233108 kb
Host smart-aba6d03c-d4ea-4e67-b123-d3553c01dac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237990903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.237990903
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2134796639
Short name T202
Test name
Test status
Simulation time 45369586081 ps
CPU time 314.95 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 08:01:56 PM PDT 24
Peak memory 251416 kb
Host smart-83ad69c1-26e5-454c-a47a-906329971a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134796639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2134796639
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1566635446
Short name T704
Test name
Test status
Simulation time 7961518306 ps
CPU time 21.22 seconds
Started Aug 09 07:56:42 PM PDT 24
Finished Aug 09 07:57:04 PM PDT 24
Peak memory 224448 kb
Host smart-2ef6e45e-cb69-481d-bc63-758ca60d7e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566635446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1566635446
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2423186627
Short name T1012
Test name
Test status
Simulation time 202600013 ps
CPU time 2.19 seconds
Started Aug 09 07:56:35 PM PDT 24
Finished Aug 09 07:56:38 PM PDT 24
Peak memory 224836 kb
Host smart-fdae6810-cfd8-4538-a17b-dfc28a0ba1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423186627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2423186627
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.529780643
Short name T75
Test name
Test status
Simulation time 2113207330 ps
CPU time 8.73 seconds
Started Aug 09 07:56:36 PM PDT 24
Finished Aug 09 07:56:45 PM PDT 24
Peak memory 240912 kb
Host smart-31d83eff-f3aa-4320-abf5-02bfa49b5e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529780643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.529780643
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2789523214
Short name T928
Test name
Test status
Simulation time 4133523889 ps
CPU time 10.89 seconds
Started Aug 09 07:56:34 PM PDT 24
Finished Aug 09 07:56:45 PM PDT 24
Peak memory 224900 kb
Host smart-7aea4d93-1be2-4eef-8ad5-256fb56d2d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789523214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2789523214
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2620429848
Short name T535
Test name
Test status
Simulation time 604087030 ps
CPU time 5.49 seconds
Started Aug 09 07:56:36 PM PDT 24
Finished Aug 09 07:56:42 PM PDT 24
Peak memory 219388 kb
Host smart-901e6d80-45ff-4e1b-9d63-7f78751f4408
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2620429848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2620429848
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4171664118
Short name T145
Test name
Test status
Simulation time 151807858542 ps
CPU time 784.63 seconds
Started Aug 09 07:56:39 PM PDT 24
Finished Aug 09 08:09:44 PM PDT 24
Peak memory 267212 kb
Host smart-aba8618d-2415-4824-ab68-ff368bf5bab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171664118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4171664118
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.16962020
Short name T684
Test name
Test status
Simulation time 13950937242 ps
CPU time 18.16 seconds
Started Aug 09 07:56:38 PM PDT 24
Finished Aug 09 07:56:56 PM PDT 24
Peak memory 216692 kb
Host smart-6e1d55da-999b-4b07-a1d0-67722fc0834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16962020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.16962020
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2576142015
Short name T686
Test name
Test status
Simulation time 1552608676 ps
CPU time 5.81 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 07:56:47 PM PDT 24
Peak memory 216668 kb
Host smart-ec4288a5-a5ca-4853-9a76-3c977420fd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576142015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2576142015
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2787296875
Short name T350
Test name
Test status
Simulation time 555857317 ps
CPU time 4.5 seconds
Started Aug 09 07:56:36 PM PDT 24
Finished Aug 09 07:56:40 PM PDT 24
Peak memory 216576 kb
Host smart-60675c4f-7d13-4ed9-8bfb-64852340a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787296875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2787296875
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2477332380
Short name T751
Test name
Test status
Simulation time 112720210 ps
CPU time 0.79 seconds
Started Aug 09 07:56:37 PM PDT 24
Finished Aug 09 07:56:38 PM PDT 24
Peak memory 206268 kb
Host smart-345680a4-23f0-4c1f-b88e-487ab6445cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477332380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2477332380
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.192203109
Short name T804
Test name
Test status
Simulation time 85255900 ps
CPU time 2.35 seconds
Started Aug 09 07:56:42 PM PDT 24
Finished Aug 09 07:56:44 PM PDT 24
Peak memory 224588 kb
Host smart-f4e0a41a-d480-47e9-90f9-b577d8435a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192203109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.192203109
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.303629803
Short name T491
Test name
Test status
Simulation time 12459801 ps
CPU time 0.76 seconds
Started Aug 09 07:56:45 PM PDT 24
Finished Aug 09 07:56:46 PM PDT 24
Peak memory 205264 kb
Host smart-e8ee731f-16d5-477a-9c19-bc34260c8165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303629803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.303629803
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4056564621
Short name T940
Test name
Test status
Simulation time 1119943471 ps
CPU time 6.86 seconds
Started Aug 09 07:56:45 PM PDT 24
Finished Aug 09 07:56:52 PM PDT 24
Peak memory 224920 kb
Host smart-009db111-a7fe-4fcf-90e2-40db3907fbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056564621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4056564621
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2367994964
Short name T661
Test name
Test status
Simulation time 97484024 ps
CPU time 0.79 seconds
Started Aug 09 07:56:40 PM PDT 24
Finished Aug 09 07:56:41 PM PDT 24
Peak memory 206932 kb
Host smart-7eb16f27-97e7-44e7-93c7-19e3ef2b519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367994964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2367994964
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1026328119
Short name T808
Test name
Test status
Simulation time 3468000823 ps
CPU time 41.76 seconds
Started Aug 09 07:56:45 PM PDT 24
Finished Aug 09 07:57:27 PM PDT 24
Peak memory 249728 kb
Host smart-dc1981fe-e4c4-4c30-852a-c0ca28daab2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026328119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1026328119
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2359979340
Short name T992
Test name
Test status
Simulation time 184167418277 ps
CPU time 298.7 seconds
Started Aug 09 07:56:50 PM PDT 24
Finished Aug 09 08:01:49 PM PDT 24
Peak memory 258972 kb
Host smart-abf0021b-34a6-4ad3-8676-547c384dfd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359979340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2359979340
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.634573170
Short name T843
Test name
Test status
Simulation time 12069161010 ps
CPU time 18.34 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 07:56:59 PM PDT 24
Peak memory 251280 kb
Host smart-9b4fb6fe-b646-4cf3-942a-ebb9d76097e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634573170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.634573170
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2668236474
Short name T982
Test name
Test status
Simulation time 338210833125 ps
CPU time 518.48 seconds
Started Aug 09 07:56:44 PM PDT 24
Finished Aug 09 08:05:22 PM PDT 24
Peak memory 262424 kb
Host smart-66a62070-65e4-453b-9b13-f8be99fcc492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668236474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2668236474
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1929646993
Short name T647
Test name
Test status
Simulation time 166467020 ps
CPU time 2.38 seconds
Started Aug 09 07:56:37 PM PDT 24
Finished Aug 09 07:56:39 PM PDT 24
Peak memory 224852 kb
Host smart-9c04a635-daa4-4224-8034-af46ad352f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929646993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1929646993
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3376738882
Short name T79
Test name
Test status
Simulation time 4678578082 ps
CPU time 29.87 seconds
Started Aug 09 07:56:39 PM PDT 24
Finished Aug 09 07:57:09 PM PDT 24
Peak memory 249512 kb
Host smart-6bbaa685-5294-4eb3-a5dd-51980926b5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376738882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3376738882
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.374831007
Short name T921
Test name
Test status
Simulation time 4442913121 ps
CPU time 15.64 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 07:56:57 PM PDT 24
Peak memory 241236 kb
Host smart-3a1e4186-99e7-4b5f-a3db-1e1e6c5a1481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374831007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.374831007
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4123974714
Short name T744
Test name
Test status
Simulation time 374186602 ps
CPU time 3.46 seconds
Started Aug 09 07:56:38 PM PDT 24
Finished Aug 09 07:56:41 PM PDT 24
Peak memory 224848 kb
Host smart-7d99c6a2-4342-41d7-b835-fcf4be052490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123974714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4123974714
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1300092869
Short name T586
Test name
Test status
Simulation time 1930353951 ps
CPU time 14.61 seconds
Started Aug 09 07:56:50 PM PDT 24
Finished Aug 09 07:57:04 PM PDT 24
Peak memory 222764 kb
Host smart-ceb79a96-e239-4ea2-87c7-e63ba38e1df3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1300092869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1300092869
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3455419129
Short name T22
Test name
Test status
Simulation time 78453414962 ps
CPU time 382.83 seconds
Started Aug 09 07:56:44 PM PDT 24
Finished Aug 09 08:03:07 PM PDT 24
Peak memory 256388 kb
Host smart-e360889f-3305-4986-8497-8c23aa4c5c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455419129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3455419129
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4181173446
Short name T973
Test name
Test status
Simulation time 1610924022 ps
CPU time 7.41 seconds
Started Aug 09 07:56:39 PM PDT 24
Finished Aug 09 07:56:46 PM PDT 24
Peak memory 219864 kb
Host smart-f51b2404-7a8b-443c-b024-5f64493ba72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181173446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4181173446
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3426115482
Short name T965
Test name
Test status
Simulation time 163493710 ps
CPU time 1.43 seconds
Started Aug 09 07:56:41 PM PDT 24
Finished Aug 09 07:56:43 PM PDT 24
Peak memory 208200 kb
Host smart-4ae00371-d92f-4874-bd75-eca39cd91971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426115482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3426115482
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3910459864
Short name T331
Test name
Test status
Simulation time 60246869 ps
CPU time 2.05 seconds
Started Aug 09 07:56:39 PM PDT 24
Finished Aug 09 07:56:41 PM PDT 24
Peak memory 216540 kb
Host smart-4f2ac786-f9ed-43d0-a6d3-53f42a9b7381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910459864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3910459864
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.200226883
Short name T777
Test name
Test status
Simulation time 33919640 ps
CPU time 0.75 seconds
Started Aug 09 07:56:39 PM PDT 24
Finished Aug 09 07:56:40 PM PDT 24
Peak memory 206340 kb
Host smart-4fe3db8a-ca25-4015-ac84-a9c210962774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200226883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.200226883
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.393270225
Short name T884
Test name
Test status
Simulation time 680526345 ps
CPU time 4.4 seconds
Started Aug 09 07:56:39 PM PDT 24
Finished Aug 09 07:56:43 PM PDT 24
Peak memory 224816 kb
Host smart-22b6eeae-1200-4384-ac07-b0aae2d87687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393270225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.393270225
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1401264991
Short name T729
Test name
Test status
Simulation time 47703403 ps
CPU time 0.7 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:56:47 PM PDT 24
Peak memory 205888 kb
Host smart-e023c260-cf8e-4752-9b69-345732d97f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401264991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1401264991
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.935786941
Short name T372
Test name
Test status
Simulation time 45635434 ps
CPU time 2.5 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:56:50 PM PDT 24
Peak memory 225128 kb
Host smart-5960f2e0-ddf4-4fd8-9dac-99717794d4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935786941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.935786941
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.401886523
Short name T785
Test name
Test status
Simulation time 37416558 ps
CPU time 0.79 seconds
Started Aug 09 07:56:38 PM PDT 24
Finished Aug 09 07:56:39 PM PDT 24
Peak memory 206968 kb
Host smart-aae8225c-64a0-4844-98ad-6877ca6a3957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401886523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.401886523
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.443013208
Short name T61
Test name
Test status
Simulation time 1947157576 ps
CPU time 45.85 seconds
Started Aug 09 07:56:55 PM PDT 24
Finished Aug 09 07:57:41 PM PDT 24
Peak memory 257604 kb
Host smart-33936733-f1dd-43ff-9b50-b367fae0ed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443013208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.443013208
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.871016348
Short name T1
Test name
Test status
Simulation time 23369287060 ps
CPU time 186.75 seconds
Started Aug 09 07:56:48 PM PDT 24
Finished Aug 09 07:59:54 PM PDT 24
Peak memory 250628 kb
Host smart-362724fe-3798-4399-b6e9-86eaa9107d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871016348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.871016348
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1679435166
Short name T148
Test name
Test status
Simulation time 9476567953 ps
CPU time 116.4 seconds
Started Aug 09 07:56:49 PM PDT 24
Finished Aug 09 07:58:46 PM PDT 24
Peak memory 263564 kb
Host smart-ad8fc52f-4237-4022-b4e7-8da341e773b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679435166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1679435166
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2206202828
Short name T305
Test name
Test status
Simulation time 1411124215 ps
CPU time 11.16 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:56:58 PM PDT 24
Peak memory 224900 kb
Host smart-c06fd229-f890-49ff-a6c8-df4d054f4487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206202828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2206202828
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3054961504
Short name T858
Test name
Test status
Simulation time 42319336975 ps
CPU time 141.8 seconds
Started Aug 09 07:56:48 PM PDT 24
Finished Aug 09 07:59:10 PM PDT 24
Peak memory 250612 kb
Host smart-6c9066b7-05ac-4c74-a6b6-efdbfc6af86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054961504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3054961504
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.398079338
Short name T914
Test name
Test status
Simulation time 11799154781 ps
CPU time 27.9 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:57:15 PM PDT 24
Peak memory 233188 kb
Host smart-3a4f5275-c375-439b-80e1-c73370e9bda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398079338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.398079338
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4100655147
Short name T450
Test name
Test status
Simulation time 23140086363 ps
CPU time 48.65 seconds
Started Aug 09 07:56:48 PM PDT 24
Finished Aug 09 07:57:37 PM PDT 24
Peak memory 233188 kb
Host smart-cbf0a1d9-c77b-4f3f-8fc1-5fe7e1d0fd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100655147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4100655147
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1956267044
Short name T918
Test name
Test status
Simulation time 14264806301 ps
CPU time 13.28 seconds
Started Aug 09 07:56:45 PM PDT 24
Finished Aug 09 07:56:59 PM PDT 24
Peak memory 233132 kb
Host smart-9fe3e81f-4ba3-484d-9f7c-f3d64bf0d3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956267044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1956267044
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.344610623
Short name T359
Test name
Test status
Simulation time 107231374 ps
CPU time 2.42 seconds
Started Aug 09 07:56:45 PM PDT 24
Finished Aug 09 07:56:48 PM PDT 24
Peak memory 224796 kb
Host smart-06b33974-424d-434b-a544-037aef8e3f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344610623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.344610623
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.346848856
Short name T814
Test name
Test status
Simulation time 254616526 ps
CPU time 3.54 seconds
Started Aug 09 07:56:54 PM PDT 24
Finished Aug 09 07:56:58 PM PDT 24
Peak memory 219348 kb
Host smart-fd347467-a06b-496a-bc14-717b6c05ae7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=346848856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.346848856
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1092769572
Short name T323
Test name
Test status
Simulation time 45331835 ps
CPU time 0.77 seconds
Started Aug 09 07:56:53 PM PDT 24
Finished Aug 09 07:56:54 PM PDT 24
Peak memory 206048 kb
Host smart-6a63b333-bbc8-44a1-8543-1cd49b0a8e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092769572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1092769572
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.595216768
Short name T55
Test name
Test status
Simulation time 4286834312 ps
CPU time 4.98 seconds
Started Aug 09 07:56:53 PM PDT 24
Finished Aug 09 07:56:58 PM PDT 24
Peak memory 216624 kb
Host smart-c38be256-130b-4d8a-ba4c-efd8c7217345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595216768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.595216768
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.275060804
Short name T939
Test name
Test status
Simulation time 309930574 ps
CPU time 1.38 seconds
Started Aug 09 07:56:53 PM PDT 24
Finished Aug 09 07:56:55 PM PDT 24
Peak memory 216628 kb
Host smart-fbe6743f-97eb-411a-b1ba-9bba3f1655b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275060804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.275060804
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1006949515
Short name T584
Test name
Test status
Simulation time 67805447 ps
CPU time 0.79 seconds
Started Aug 09 07:56:53 PM PDT 24
Finished Aug 09 07:56:54 PM PDT 24
Peak memory 206304 kb
Host smart-3f1c1349-1736-4010-a2fe-bfe04b9316f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006949515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1006949515
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.434695019
Short name T475
Test name
Test status
Simulation time 798329926 ps
CPU time 7.23 seconds
Started Aug 09 07:56:55 PM PDT 24
Finished Aug 09 07:57:03 PM PDT 24
Peak memory 233052 kb
Host smart-3d7f4377-afce-42b9-951c-b5f478b188f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434695019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.434695019
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1788043954
Short name T399
Test name
Test status
Simulation time 62921889 ps
CPU time 0.77 seconds
Started Aug 09 07:56:50 PM PDT 24
Finished Aug 09 07:56:51 PM PDT 24
Peak memory 206204 kb
Host smart-a8b92ac3-6a23-4149-b625-77bc67706ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788043954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1788043954
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2031181884
Short name T320
Test name
Test status
Simulation time 53858326 ps
CPU time 2.22 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:56:49 PM PDT 24
Peak memory 223932 kb
Host smart-4481b174-e23d-4814-93dc-5daac026f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031181884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2031181884
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3890821435
Short name T498
Test name
Test status
Simulation time 22385111 ps
CPU time 0.8 seconds
Started Aug 09 07:56:55 PM PDT 24
Finished Aug 09 07:56:56 PM PDT 24
Peak memory 207000 kb
Host smart-de30d1aa-fad3-43c9-9a7e-28d79fbbba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890821435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3890821435
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1460148514
Short name T812
Test name
Test status
Simulation time 22473817164 ps
CPU time 146.97 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:59:14 PM PDT 24
Peak memory 254184 kb
Host smart-02de438f-35e0-4f5e-a82d-e3b397c1d729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460148514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1460148514
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1053728163
Short name T592
Test name
Test status
Simulation time 429847365 ps
CPU time 2.32 seconds
Started Aug 09 07:56:49 PM PDT 24
Finished Aug 09 07:56:51 PM PDT 24
Peak memory 217932 kb
Host smart-f52c8a2d-8c09-40d8-b0d8-8c0f9d32334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053728163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1053728163
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3753376161
Short name T367
Test name
Test status
Simulation time 23571409000 ps
CPU time 203.67 seconds
Started Aug 09 07:56:48 PM PDT 24
Finished Aug 09 08:00:12 PM PDT 24
Peak memory 257764 kb
Host smart-dd0deb6e-c390-4413-8d99-d5239d151dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753376161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3753376161
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1218896639
Short name T307
Test name
Test status
Simulation time 1606786961 ps
CPU time 6.81 seconds
Started Aug 09 07:56:48 PM PDT 24
Finished Aug 09 07:56:55 PM PDT 24
Peak memory 224884 kb
Host smart-54428ae1-4188-4e70-bab2-25016467ca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218896639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1218896639
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1052985806
Short name T793
Test name
Test status
Simulation time 5533950626 ps
CPU time 76.98 seconds
Started Aug 09 07:56:53 PM PDT 24
Finished Aug 09 07:58:10 PM PDT 24
Peak memory 257676 kb
Host smart-48bb7788-68e6-4462-bcba-fc68f5e4cf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052985806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1052985806
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1679055151
Short name T526
Test name
Test status
Simulation time 121383119 ps
CPU time 3.86 seconds
Started Aug 09 07:56:49 PM PDT 24
Finished Aug 09 07:56:53 PM PDT 24
Peak memory 233184 kb
Host smart-3a22e7e9-7cde-4f28-a689-f30ae8541484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679055151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1679055151
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2006143103
Short name T813
Test name
Test status
Simulation time 600736064 ps
CPU time 12.2 seconds
Started Aug 09 07:56:48 PM PDT 24
Finished Aug 09 07:57:00 PM PDT 24
Peak memory 234476 kb
Host smart-a1b394fd-50a3-4a39-a7df-1c13cb957f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006143103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2006143103
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.89729904
Short name T284
Test name
Test status
Simulation time 3869533218 ps
CPU time 4.83 seconds
Started Aug 09 07:56:46 PM PDT 24
Finished Aug 09 07:56:51 PM PDT 24
Peak memory 224952 kb
Host smart-51593251-8f04-499e-8d34-10f15adb5843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89729904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.89729904
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1615615443
Short name T520
Test name
Test status
Simulation time 6111606887 ps
CPU time 17.36 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:57:04 PM PDT 24
Peak memory 233104 kb
Host smart-701018c5-9b20-44a5-87d8-e38a68ea2212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615615443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1615615443
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4258429385
Short name T678
Test name
Test status
Simulation time 4794062297 ps
CPU time 10.28 seconds
Started Aug 09 07:56:53 PM PDT 24
Finished Aug 09 07:57:04 PM PDT 24
Peak memory 222152 kb
Host smart-249d48cb-0617-49dc-b266-dfa3a8b35b14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4258429385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4258429385
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3832628229
Short name T512
Test name
Test status
Simulation time 62267431518 ps
CPU time 134.3 seconds
Started Aug 09 07:56:50 PM PDT 24
Finished Aug 09 07:59:04 PM PDT 24
Peak memory 249596 kb
Host smart-a66d9181-176d-49e8-95ad-f689c11af59b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832628229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3832628229
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.832556436
Short name T763
Test name
Test status
Simulation time 5971118127 ps
CPU time 29.17 seconds
Started Aug 09 07:56:48 PM PDT 24
Finished Aug 09 07:57:17 PM PDT 24
Peak memory 216716 kb
Host smart-c48647bb-bb48-465a-9323-82dffe80725b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832556436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.832556436
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.655121737
Short name T937
Test name
Test status
Simulation time 8930755151 ps
CPU time 25.31 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:57:13 PM PDT 24
Peak memory 216588 kb
Host smart-46adc78a-0a61-4065-b068-fa93c3986693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655121737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.655121737
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1497276613
Short name T421
Test name
Test status
Simulation time 457385290 ps
CPU time 1.12 seconds
Started Aug 09 07:56:50 PM PDT 24
Finished Aug 09 07:56:51 PM PDT 24
Peak memory 208044 kb
Host smart-50d629bd-7d26-48dc-9f51-908a10abc830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497276613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1497276613
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4062951446
Short name T332
Test name
Test status
Simulation time 103435231 ps
CPU time 0.88 seconds
Started Aug 09 07:56:53 PM PDT 24
Finished Aug 09 07:56:54 PM PDT 24
Peak memory 206296 kb
Host smart-5f518681-92fe-49a7-90d1-c8baf75f796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062951446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4062951446
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.270586022
Short name T249
Test name
Test status
Simulation time 5168635778 ps
CPU time 6.77 seconds
Started Aug 09 07:56:50 PM PDT 24
Finished Aug 09 07:56:57 PM PDT 24
Peak memory 224976 kb
Host smart-02e49452-c3bf-4a2d-b295-62da330693a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270586022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.270586022
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1860829552
Short name T423
Test name
Test status
Simulation time 25382794 ps
CPU time 0.75 seconds
Started Aug 09 07:57:04 PM PDT 24
Finished Aug 09 07:57:05 PM PDT 24
Peak memory 205260 kb
Host smart-bb99c337-8162-4191-868c-23a6e22d9e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860829552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1860829552
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1197613187
Short name T461
Test name
Test status
Simulation time 114221051 ps
CPU time 2.74 seconds
Started Aug 09 07:57:04 PM PDT 24
Finished Aug 09 07:57:07 PM PDT 24
Peak memory 224892 kb
Host smart-8ed4b028-8936-405a-9f29-fb95b117f284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197613187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1197613187
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2313133895
Short name T63
Test name
Test status
Simulation time 98930681 ps
CPU time 0.77 seconds
Started Aug 09 07:56:45 PM PDT 24
Finished Aug 09 07:56:46 PM PDT 24
Peak memory 205980 kb
Host smart-01a5a449-5888-428c-9839-ec8ea758bcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313133895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2313133895
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.505900088
Short name T5
Test name
Test status
Simulation time 176218896416 ps
CPU time 257.53 seconds
Started Aug 09 07:57:00 PM PDT 24
Finished Aug 09 08:01:17 PM PDT 24
Peak memory 249580 kb
Host smart-acb076ed-25d6-4314-96f2-cadd21a3156d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505900088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.505900088
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2450743563
Short name T33
Test name
Test status
Simulation time 45251886745 ps
CPU time 92.04 seconds
Started Aug 09 07:57:01 PM PDT 24
Finished Aug 09 07:58:33 PM PDT 24
Peak memory 249568 kb
Host smart-00c27448-f2db-49f8-b146-b53f1bd8a145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450743563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2450743563
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4076026103
Short name T829
Test name
Test status
Simulation time 43872764416 ps
CPU time 193.81 seconds
Started Aug 09 07:56:58 PM PDT 24
Finished Aug 09 08:00:12 PM PDT 24
Peak memory 254408 kb
Host smart-96d4b932-b927-44ad-8a55-d43de828cadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076026103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4076026103
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.6161094
Short name T306
Test name
Test status
Simulation time 2434667484 ps
CPU time 24.23 seconds
Started Aug 09 07:56:59 PM PDT 24
Finished Aug 09 07:57:23 PM PDT 24
Peak memory 234884 kb
Host smart-34b20326-5c72-4735-b893-98d7232a61c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6161094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.6161094
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1590632370
Short name T274
Test name
Test status
Simulation time 789684461 ps
CPU time 9.49 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:56:57 PM PDT 24
Peak memory 233156 kb
Host smart-2e888bd9-fa22-42f2-bb27-b0349f3491ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590632370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1590632370
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2815376358
Short name T610
Test name
Test status
Simulation time 3103736264 ps
CPU time 21.26 seconds
Started Aug 09 07:57:02 PM PDT 24
Finished Aug 09 07:57:23 PM PDT 24
Peak memory 241300 kb
Host smart-3fc8d984-33ba-424f-9335-eecefbb25856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815376358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2815376358
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1962042077
Short name T957
Test name
Test status
Simulation time 13728412396 ps
CPU time 9.91 seconds
Started Aug 09 07:56:46 PM PDT 24
Finished Aug 09 07:56:56 PM PDT 24
Peak memory 236100 kb
Host smart-5a4b6bce-31c4-4c70-ad18-e223d9939ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962042077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1962042077
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3266334717
Short name T396
Test name
Test status
Simulation time 438721257 ps
CPU time 4.14 seconds
Started Aug 09 07:56:47 PM PDT 24
Finished Aug 09 07:56:52 PM PDT 24
Peak memory 224844 kb
Host smart-05994b90-3096-4a36-b197-643e626913bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266334717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3266334717
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2523596381
Short name T743
Test name
Test status
Simulation time 5456079371 ps
CPU time 13.63 seconds
Started Aug 09 07:57:01 PM PDT 24
Finished Aug 09 07:57:15 PM PDT 24
Peak memory 221020 kb
Host smart-09907cbb-b585-4307-b8ea-945ae7c24000
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2523596381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2523596381
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1856718918
Short name T172
Test name
Test status
Simulation time 77838177117 ps
CPU time 607.21 seconds
Started Aug 09 07:56:58 PM PDT 24
Finished Aug 09 08:07:06 PM PDT 24
Peak memory 269748 kb
Host smart-469eff67-4ac4-46f5-a228-3e5289f3d622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856718918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1856718918
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1374198107
Short name T353
Test name
Test status
Simulation time 734076653 ps
CPU time 4.17 seconds
Started Aug 09 07:56:50 PM PDT 24
Finished Aug 09 07:56:54 PM PDT 24
Peak memory 219520 kb
Host smart-88971638-9e1a-4cab-940d-f41b482a72d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374198107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1374198107
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.399740250
Short name T597
Test name
Test status
Simulation time 35779316 ps
CPU time 0.71 seconds
Started Aug 09 07:56:51 PM PDT 24
Finished Aug 09 07:56:52 PM PDT 24
Peak memory 206108 kb
Host smart-2705753e-d318-4c90-9ca4-08f7f62258d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399740250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.399740250
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.970723779
Short name T571
Test name
Test status
Simulation time 50044630 ps
CPU time 0.75 seconds
Started Aug 09 07:56:51 PM PDT 24
Finished Aug 09 07:56:52 PM PDT 24
Peak memory 206324 kb
Host smart-00814af6-0a57-4e76-908e-55a79df22802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970723779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.970723779
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1172904131
Short name T180
Test name
Test status
Simulation time 185291211 ps
CPU time 0.81 seconds
Started Aug 09 07:56:48 PM PDT 24
Finished Aug 09 07:56:49 PM PDT 24
Peak memory 206340 kb
Host smart-d012bd73-a401-4a1e-a575-e9fdb5381239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172904131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1172904131
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.529088126
Short name T319
Test name
Test status
Simulation time 35660437 ps
CPU time 2.64 seconds
Started Aug 09 07:56:59 PM PDT 24
Finished Aug 09 07:57:02 PM PDT 24
Peak memory 224620 kb
Host smart-4ad916ba-e493-49d8-9b79-a4801b3fe1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529088126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.529088126
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.839993582
Short name T530
Test name
Test status
Simulation time 72705686 ps
CPU time 0.73 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:31 PM PDT 24
Peak memory 205828 kb
Host smart-15783962-256b-440b-a2cb-fd2d461722bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839993582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.839993582
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1771481529
Short name T910
Test name
Test status
Simulation time 1269002260 ps
CPU time 11.11 seconds
Started Aug 09 07:54:32 PM PDT 24
Finished Aug 09 07:54:44 PM PDT 24
Peak memory 224780 kb
Host smart-c47c827a-0778-49f4-9a82-62260dda5e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771481529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1771481529
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.943044952
Short name T1013
Test name
Test status
Simulation time 41347315 ps
CPU time 0.76 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 07:54:29 PM PDT 24
Peak memory 205956 kb
Host smart-19894621-9ebf-4b30-97ea-9bda701f1c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943044952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.943044952
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3137628629
Short name T582
Test name
Test status
Simulation time 7814444494 ps
CPU time 47.91 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:55:21 PM PDT 24
Peak memory 252372 kb
Host smart-5c7f84e4-4b27-44fc-8563-33e03eeed372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137628629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3137628629
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1717121288
Short name T889
Test name
Test status
Simulation time 16683979414 ps
CPU time 199.89 seconds
Started Aug 09 07:54:32 PM PDT 24
Finished Aug 09 07:57:53 PM PDT 24
Peak memory 266940 kb
Host smart-0109c2d8-43b2-4824-9cb7-1afbad6a7fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717121288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1717121288
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.288481728
Short name T223
Test name
Test status
Simulation time 243494573549 ps
CPU time 609.75 seconds
Started Aug 09 07:54:29 PM PDT 24
Finished Aug 09 08:04:39 PM PDT 24
Peak memory 255580 kb
Host smart-a46bfd12-713e-4c23-89e1-62484274645c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288481728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
288481728
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.538369215
Short name T969
Test name
Test status
Simulation time 135133707 ps
CPU time 3.09 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:33 PM PDT 24
Peak memory 224928 kb
Host smart-affcb089-b0be-43af-8f00-d0a87a55c1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538369215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.538369215
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1439572356
Short name T346
Test name
Test status
Simulation time 4366502597 ps
CPU time 29.91 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:55:06 PM PDT 24
Peak memory 237872 kb
Host smart-61fbe5a7-0267-4ff7-a40e-b7d1af0f84d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439572356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1439572356
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1226231679
Short name T230
Test name
Test status
Simulation time 782136347 ps
CPU time 7.83 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:54:41 PM PDT 24
Peak memory 224872 kb
Host smart-03d20788-f2be-4879-971a-042138e754f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226231679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1226231679
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2877499857
Short name T556
Test name
Test status
Simulation time 119188122 ps
CPU time 2.32 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:33 PM PDT 24
Peak memory 232796 kb
Host smart-74669114-ee4a-4b7d-8044-0118f673d508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877499857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2877499857
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2821713599
Short name T762
Test name
Test status
Simulation time 1204572875 ps
CPU time 5.25 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:41 PM PDT 24
Peak memory 233116 kb
Host smart-e992e8a8-55d6-42fd-a7cf-4f4b24ef0a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821713599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2821713599
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2597058611
Short name T820
Test name
Test status
Simulation time 875767988 ps
CPU time 7.49 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:37 PM PDT 24
Peak memory 241024 kb
Host smart-aa18d587-1789-4261-bd35-b1d17ec35546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597058611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2597058611
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3925513295
Short name T160
Test name
Test status
Simulation time 455345502 ps
CPU time 5.79 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:40 PM PDT 24
Peak memory 223616 kb
Host smart-85fe4c51-74fe-426d-9088-6b8d69ceeb9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3925513295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3925513295
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1645301444
Short name T545
Test name
Test status
Simulation time 42045454848 ps
CPU time 182.31 seconds
Started Aug 09 07:54:32 PM PDT 24
Finished Aug 09 07:57:34 PM PDT 24
Peak memory 257824 kb
Host smart-bccc6a4a-3fd0-4dd2-b1e8-0c09d01dc264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645301444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1645301444
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2869343593
Short name T642
Test name
Test status
Simulation time 688392384 ps
CPU time 6.52 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:38 PM PDT 24
Peak memory 216640 kb
Host smart-52bc3cf7-baff-447a-8805-a0f95b462ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869343593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2869343593
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.454954460
Short name T585
Test name
Test status
Simulation time 15256306321 ps
CPU time 20.23 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:52 PM PDT 24
Peak memory 216744 kb
Host smart-dc5a056f-52e3-4a52-83f8-54ee86675150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454954460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.454954460
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3522130476
Short name T832
Test name
Test status
Simulation time 245368361 ps
CPU time 1.76 seconds
Started Aug 09 07:54:32 PM PDT 24
Finished Aug 09 07:54:34 PM PDT 24
Peak memory 208308 kb
Host smart-182332e4-a23d-4da9-b8b6-c65ef02d704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522130476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3522130476
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3942728844
Short name T329
Test name
Test status
Simulation time 179805215 ps
CPU time 0.89 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:54:34 PM PDT 24
Peak memory 206336 kb
Host smart-48c1d9c8-3a02-4a82-9fbd-5f64b7cc4d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942728844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3942728844
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.508243040
Short name T666
Test name
Test status
Simulation time 64789936 ps
CPU time 2.39 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:34 PM PDT 24
Peak memory 224928 kb
Host smart-1056af29-a3d2-487f-b664-d297c616f83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508243040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.508243040
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.84933949
Short name T378
Test name
Test status
Simulation time 18806540 ps
CPU time 0.72 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:54:37 PM PDT 24
Peak memory 206036 kb
Host smart-42709fe9-ddfe-4641-832a-5e041cfb8834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84933949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.84933949
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.656910872
Short name T873
Test name
Test status
Simulation time 321174086 ps
CPU time 2.52 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:38 PM PDT 24
Peak memory 233108 kb
Host smart-818c0f74-7201-42f6-8549-8f1e5ab30b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656910872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.656910872
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.570461205
Short name T543
Test name
Test status
Simulation time 21817395 ps
CPU time 0.78 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:36 PM PDT 24
Peak memory 206972 kb
Host smart-4b29239a-53d6-48f1-a7c9-d5b20bd99146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570461205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.570461205
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2471930445
Short name T404
Test name
Test status
Simulation time 14360322338 ps
CPU time 31.12 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:55:06 PM PDT 24
Peak memory 241656 kb
Host smart-21c0b9ec-4f76-4118-89f8-f48da1d98875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471930445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2471930445
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1599892473
Short name T147
Test name
Test status
Simulation time 48466021926 ps
CPU time 108.14 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 272544 kb
Host smart-09dfba0f-c754-442f-9280-9f1775d2365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599892473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1599892473
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.194535918
Short name T600
Test name
Test status
Simulation time 60621633678 ps
CPU time 76.04 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:55:52 PM PDT 24
Peak memory 257748 kb
Host smart-a3153552-08f6-4db4-8f93-017de17d992e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194535918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
194535918
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3266396495
Short name T360
Test name
Test status
Simulation time 175390664 ps
CPU time 5.35 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:40 PM PDT 24
Peak memory 219324 kb
Host smart-aac9a44b-bfcb-413a-8fac-324ae9b7f931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266396495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3266396495
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2200564959
Short name T783
Test name
Test status
Simulation time 1658271099 ps
CPU time 19.03 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:55 PM PDT 24
Peak memory 233164 kb
Host smart-9781fd97-3bfc-4bdf-98e4-d08c62d0dbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200564959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2200564959
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3703959619
Short name T231
Test name
Test status
Simulation time 3586522864 ps
CPU time 13.89 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:50 PM PDT 24
Peak memory 224688 kb
Host smart-30e97ebf-ff41-430a-a54b-86e45d86d044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703959619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3703959619
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2649691802
Short name T418
Test name
Test status
Simulation time 2233311708 ps
CPU time 11.38 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:54:48 PM PDT 24
Peak memory 233444 kb
Host smart-42c4c183-52d0-444f-afca-fd1b1b650b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649691802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2649691802
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1053574040
Short name T626
Test name
Test status
Simulation time 192165877 ps
CPU time 2.61 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:39 PM PDT 24
Peak memory 233068 kb
Host smart-ca2928a1-f837-40a8-8842-04ad86b29cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053574040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1053574040
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.487959665
Short name T1008
Test name
Test status
Simulation time 140214435 ps
CPU time 2.37 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:37 PM PDT 24
Peak memory 224172 kb
Host smart-27bddb52-1f9c-439e-8356-c4d1b6b757d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487959665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.487959665
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1546928767
Short name T746
Test name
Test status
Simulation time 954280317 ps
CPU time 5.02 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:54:42 PM PDT 24
Peak memory 219760 kb
Host smart-e84cc67f-acea-4c7c-ba9c-ef51522b796b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1546928767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1546928767
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4256459241
Short name T204
Test name
Test status
Simulation time 51820874957 ps
CPU time 516.14 seconds
Started Aug 09 07:54:37 PM PDT 24
Finished Aug 09 08:03:13 PM PDT 24
Peak memory 264600 kb
Host smart-0731f131-a369-4ea4-9311-9522bc4adee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256459241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4256459241
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1263457310
Short name T467
Test name
Test status
Simulation time 1982070812 ps
CPU time 22.58 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:57 PM PDT 24
Peak memory 220156 kb
Host smart-af545ef2-5705-41ab-88dd-dafca86dbf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263457310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1263457310
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1576364752
Short name T936
Test name
Test status
Simulation time 164708940 ps
CPU time 1.48 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:37 PM PDT 24
Peak memory 207520 kb
Host smart-641f69bc-83f0-42da-b408-8bde4809300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576364752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1576364752
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3563149530
Short name T768
Test name
Test status
Simulation time 267590601 ps
CPU time 1.67 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:36 PM PDT 24
Peak memory 216612 kb
Host smart-4ee13e1d-0abb-47ad-9d9b-b81c11c15158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563149530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3563149530
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.628581312
Short name T517
Test name
Test status
Simulation time 80273798 ps
CPU time 0.85 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:36 PM PDT 24
Peak memory 206304 kb
Host smart-9c67668d-65f4-40c0-95c3-f4a2ad35c671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628581312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.628581312
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3421930289
Short name T619
Test name
Test status
Simulation time 13109772733 ps
CPU time 21.28 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:52 PM PDT 24
Peak memory 233228 kb
Host smart-a6add3c0-8f3d-469f-bce3-6c684e99daeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421930289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3421930289
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.638301771
Short name T755
Test name
Test status
Simulation time 47554897 ps
CPU time 0.76 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:54:34 PM PDT 24
Peak memory 205820 kb
Host smart-0034bdef-22a1-44cb-836e-4ac3237addc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638301771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.638301771
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1166779621
Short name T846
Test name
Test status
Simulation time 110416975 ps
CPU time 2.36 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:54:43 PM PDT 24
Peak memory 232740 kb
Host smart-3419355c-ccfb-4fd2-8044-854634eb7efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166779621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1166779621
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4150305579
Short name T888
Test name
Test status
Simulation time 29267535 ps
CPU time 0.79 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:54:37 PM PDT 24
Peak memory 207212 kb
Host smart-7db98342-f0c5-4497-bb5b-befe67cb4b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150305579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4150305579
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3216558359
Short name T318
Test name
Test status
Simulation time 112488692 ps
CPU time 0.77 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:32 PM PDT 24
Peak memory 216128 kb
Host smart-59f53964-51cc-4c4f-83cb-76ff1d46eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216558359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3216558359
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.310061550
Short name T32
Test name
Test status
Simulation time 10497934508 ps
CPU time 121.68 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:56:32 PM PDT 24
Peak memory 257808 kb
Host smart-cd8f4e6c-e276-46da-8bad-a7a7a7ee3836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310061550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.310061550
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3655491757
Short name T49
Test name
Test status
Simulation time 22345968716 ps
CPU time 222.21 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:58:18 PM PDT 24
Peak memory 257756 kb
Host smart-0585f01a-baad-49df-9143-2b044f32f4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655491757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3655491757
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3468369055
Short name T657
Test name
Test status
Simulation time 834102168 ps
CPU time 6.99 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:45 PM PDT 24
Peak memory 233116 kb
Host smart-4724eac5-586d-4527-817d-c8ec15d4f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468369055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3468369055
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4013955321
Short name T796
Test name
Test status
Simulation time 64034066323 ps
CPU time 121.6 seconds
Started Aug 09 07:54:41 PM PDT 24
Finished Aug 09 07:56:42 PM PDT 24
Peak memory 259272 kb
Host smart-c239c46e-bec8-4c41-a2e6-2efae5c0adf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013955321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4013955321
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.684338613
Short name T383
Test name
Test status
Simulation time 2113022479 ps
CPU time 5.5 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:40 PM PDT 24
Peak memory 224916 kb
Host smart-cb71d11b-6572-4ff2-bb39-6a2dba838d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684338613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.684338613
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.430297662
Short name T12
Test name
Test status
Simulation time 4777850157 ps
CPU time 19.6 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:51 PM PDT 24
Peak memory 249392 kb
Host smart-72644c88-ad7d-4da3-811b-2a76eee7751e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430297662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.430297662
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4292206683
Short name T407
Test name
Test status
Simulation time 3187552830 ps
CPU time 8.92 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:43 PM PDT 24
Peak memory 241144 kb
Host smart-57f073d1-30a1-45f6-9955-4f508107af8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292206683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4292206683
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3063251517
Short name T356
Test name
Test status
Simulation time 374866102 ps
CPU time 3.24 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:39 PM PDT 24
Peak memory 224836 kb
Host smart-92ae767d-0529-4421-a0a9-472951365641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063251517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3063251517
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3244562010
Short name T677
Test name
Test status
Simulation time 943722751 ps
CPU time 5.54 seconds
Started Aug 09 07:54:32 PM PDT 24
Finished Aug 09 07:54:37 PM PDT 24
Peak memory 223464 kb
Host smart-e65ac0a5-4638-4486-8577-224891a572e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3244562010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3244562010
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1816733009
Short name T1001
Test name
Test status
Simulation time 175996369 ps
CPU time 1.03 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:32 PM PDT 24
Peak memory 207392 kb
Host smart-550341dc-5ee5-4f27-b237-dcc9c34dae92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816733009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1816733009
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3772596557
Short name T899
Test name
Test status
Simulation time 17955674642 ps
CPU time 31.61 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:55:05 PM PDT 24
Peak memory 216748 kb
Host smart-3b1d6a6c-8083-4eb9-8299-2458f1cd7cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772596557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3772596557
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3488566760
Short name T595
Test name
Test status
Simulation time 5445406467 ps
CPU time 8.74 seconds
Started Aug 09 07:54:41 PM PDT 24
Finished Aug 09 07:54:50 PM PDT 24
Peak memory 216596 kb
Host smart-ea7a8fea-fef9-4d47-a10e-390196ba54bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488566760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3488566760
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3141587267
Short name T344
Test name
Test status
Simulation time 118398595 ps
CPU time 5.47 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:44 PM PDT 24
Peak memory 216640 kb
Host smart-b18d5f61-1ea0-4547-9181-6a44354cdc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141587267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3141587267
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2527433222
Short name T956
Test name
Test status
Simulation time 15056917 ps
CPU time 0.73 seconds
Started Aug 09 07:54:41 PM PDT 24
Finished Aug 09 07:54:42 PM PDT 24
Peak memory 206260 kb
Host smart-9d898991-4cd1-4e79-8bcc-bea42c89cc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527433222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2527433222
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3541241782
Short name T929
Test name
Test status
Simulation time 536538496 ps
CPU time 2.53 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:40 PM PDT 24
Peak memory 233132 kb
Host smart-2d8539cc-b38c-4dd7-8aef-7881ace1b59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541241782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3541241782
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2864047795
Short name T575
Test name
Test status
Simulation time 17358491 ps
CPU time 0.74 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:39 PM PDT 24
Peak memory 205872 kb
Host smart-52cb44ee-3afe-4805-b8b3-773964570e8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864047795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
864047795
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1330508543
Short name T799
Test name
Test status
Simulation time 2793293709 ps
CPU time 8.06 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:43 PM PDT 24
Peak memory 233148 kb
Host smart-e5e98beb-834b-4505-8c98-33784311e023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330508543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1330508543
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2361641433
Short name T601
Test name
Test status
Simulation time 144436078 ps
CPU time 0.79 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:32 PM PDT 24
Peak memory 205952 kb
Host smart-517f8d41-d927-45e1-9a6a-c33dd81b6458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361641433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2361641433
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2508625737
Short name T532
Test name
Test status
Simulation time 156108128392 ps
CPU time 125.06 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:56:41 PM PDT 24
Peak memory 240904 kb
Host smart-05ee45e2-d032-4ef3-8aab-a439af7d9903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508625737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2508625737
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2566407630
Short name T565
Test name
Test status
Simulation time 3398234325 ps
CPU time 72.28 seconds
Started Aug 09 07:54:37 PM PDT 24
Finished Aug 09 07:55:50 PM PDT 24
Peak memory 250568 kb
Host smart-2955a628-0c14-4369-ac7f-2a329b5d6d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566407630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2566407630
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4176094944
Short name T637
Test name
Test status
Simulation time 755136093 ps
CPU time 9.87 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:44 PM PDT 24
Peak memory 224940 kb
Host smart-7226dc22-0e3b-472d-b082-922bc82f9e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176094944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4176094944
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.4083170101
Short name T97
Test name
Test status
Simulation time 6361956101 ps
CPU time 108.34 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:56:24 PM PDT 24
Peak memory 268920 kb
Host smart-4aa0e34a-f445-4cd8-b397-84c7d78fd728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083170101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.4083170101
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.801321359
Short name T240
Test name
Test status
Simulation time 11840500944 ps
CPU time 24.33 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:54 PM PDT 24
Peak memory 224912 kb
Host smart-b69d932b-e66d-40d0-9782-4d38ed0e1932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801321359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.801321359
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.95429067
Short name T855
Test name
Test status
Simulation time 12560423906 ps
CPU time 13.19 seconds
Started Aug 09 07:54:34 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 238632 kb
Host smart-bad200ad-a3c7-4607-918e-4d535cbfa748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95429067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.95429067
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1236398856
Short name T487
Test name
Test status
Simulation time 924775546 ps
CPU time 4.32 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:36 PM PDT 24
Peak memory 224840 kb
Host smart-64d03531-3507-4f79-a777-7b342384b0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236398856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1236398856
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1919211106
Short name T352
Test name
Test status
Simulation time 6032037142 ps
CPU time 5.12 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:40 PM PDT 24
Peak memory 233152 kb
Host smart-923fb4dd-cc19-4303-b40b-3898d30a2d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919211106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1919211106
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1186228737
Short name T792
Test name
Test status
Simulation time 24708136963 ps
CPU time 13.89 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:50 PM PDT 24
Peak memory 223488 kb
Host smart-f6ee8b36-f099-4b36-9856-48da1df04c07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1186228737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1186228737
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1053716787
Short name T265
Test name
Test status
Simulation time 74786835226 ps
CPU time 152.13 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:57:10 PM PDT 24
Peak memory 251712 kb
Host smart-b8f738ba-d770-47ba-b996-ba52a70c8d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053716787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1053716787
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3330793443
Short name T655
Test name
Test status
Simulation time 2273079314 ps
CPU time 15.78 seconds
Started Aug 09 07:54:30 PM PDT 24
Finished Aug 09 07:54:46 PM PDT 24
Peak memory 216720 kb
Host smart-d849aa35-4c5f-4680-9296-03286ad4ee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330793443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3330793443
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3088864891
Short name T465
Test name
Test status
Simulation time 940238143 ps
CPU time 2.25 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:41 PM PDT 24
Peak memory 216484 kb
Host smart-4c7d00db-5fd6-400f-b1f0-38b8fad90973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088864891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3088864891
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2973940569
Short name T427
Test name
Test status
Simulation time 123982928 ps
CPU time 5.39 seconds
Started Aug 09 07:54:35 PM PDT 24
Finished Aug 09 07:54:41 PM PDT 24
Peak memory 216672 kb
Host smart-76798160-e22c-4313-93a3-7f83ee935cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973940569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2973940569
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2881695096
Short name T728
Test name
Test status
Simulation time 305409969 ps
CPU time 0.94 seconds
Started Aug 09 07:54:31 PM PDT 24
Finished Aug 09 07:54:32 PM PDT 24
Peak memory 206276 kb
Host smart-086111c4-f8e1-4c54-94fb-e75b430f2d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881695096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2881695096
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.804016677
Short name T756
Test name
Test status
Simulation time 6407423410 ps
CPU time 8.23 seconds
Started Aug 09 07:54:33 PM PDT 24
Finished Aug 09 07:54:41 PM PDT 24
Peak memory 233432 kb
Host smart-1b48a70c-bd91-41cd-af75-2a211a78841d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804016677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.804016677
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.141988676
Short name T641
Test name
Test status
Simulation time 53755087 ps
CPU time 0.75 seconds
Started Aug 09 07:54:51 PM PDT 24
Finished Aug 09 07:54:52 PM PDT 24
Peak memory 205836 kb
Host smart-1a0393ae-56c6-4d11-ade1-67656e831d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141988676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.141988676
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.287803601
Short name T570
Test name
Test status
Simulation time 383216721 ps
CPU time 2.56 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:40 PM PDT 24
Peak memory 228484 kb
Host smart-62c3d139-d561-4e2e-8f1b-65c64d0c526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287803601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.287803601
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.249589299
Short name T456
Test name
Test status
Simulation time 15904273 ps
CPU time 0.76 seconds
Started Aug 09 07:54:39 PM PDT 24
Finished Aug 09 07:54:40 PM PDT 24
Peak memory 205896 kb
Host smart-2119234a-fe6e-4522-b668-75731c6de8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249589299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.249589299
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3066356848
Short name T295
Test name
Test status
Simulation time 238438091 ps
CPU time 6.8 seconds
Started Aug 09 07:54:42 PM PDT 24
Finished Aug 09 07:54:49 PM PDT 24
Peak memory 235732 kb
Host smart-5895b0bc-15d0-4196-b488-31a90af2ecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066356848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3066356848
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.428691326
Short name T572
Test name
Test status
Simulation time 106979773156 ps
CPU time 250.22 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:58:49 PM PDT 24
Peak memory 249624 kb
Host smart-e22bab6c-4cda-439c-acc8-c473e65d6f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428691326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.428691326
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.736350130
Short name T201
Test name
Test status
Simulation time 240944028378 ps
CPU time 273.51 seconds
Started Aug 09 07:54:37 PM PDT 24
Finished Aug 09 07:59:11 PM PDT 24
Peak memory 274212 kb
Host smart-80a706ad-7798-4a33-bf17-e7a0143d2ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736350130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
736350130
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.585234723
Short name T901
Test name
Test status
Simulation time 3287153367 ps
CPU time 50.3 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:55:28 PM PDT 24
Peak memory 233216 kb
Host smart-1e1ab456-3d7e-4fa5-b224-cfba6ca87ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585234723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.585234723
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1608126376
Short name T221
Test name
Test status
Simulation time 4109007767 ps
CPU time 88.94 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:56:06 PM PDT 24
Peak memory 265976 kb
Host smart-fd5b152e-c8ee-4667-956b-439b995b164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608126376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1608126376
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.620302329
Short name T895
Test name
Test status
Simulation time 3416157750 ps
CPU time 8.84 seconds
Started Aug 09 07:54:38 PM PDT 24
Finished Aug 09 07:54:47 PM PDT 24
Peak memory 224880 kb
Host smart-35cfdbbc-d17f-41cc-ae15-1044caed1ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620302329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.620302329
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3920340425
Short name T161
Test name
Test status
Simulation time 1918176029 ps
CPU time 27.33 seconds
Started Aug 09 07:54:49 PM PDT 24
Finished Aug 09 07:55:16 PM PDT 24
Peak memory 233132 kb
Host smart-fd21b55b-78fc-4e14-bb79-adea253e8c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920340425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3920340425
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3231951575
Short name T41
Test name
Test status
Simulation time 1184524161 ps
CPU time 4.33 seconds
Started Aug 09 07:54:37 PM PDT 24
Finished Aug 09 07:54:42 PM PDT 24
Peak memory 233092 kb
Host smart-49f54538-b451-43ec-901d-ac95f8360d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231951575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3231951575
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.669365856
Short name T923
Test name
Test status
Simulation time 44137091 ps
CPU time 2.65 seconds
Started Aug 09 07:54:36 PM PDT 24
Finished Aug 09 07:54:39 PM PDT 24
Peak memory 233112 kb
Host smart-e5d55274-2f41-42d0-a141-0217f3faf8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669365856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.669365856
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2332386253
Short name T628
Test name
Test status
Simulation time 663389516 ps
CPU time 4.26 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:54:45 PM PDT 24
Peak memory 223560 kb
Host smart-bbfe077f-17f6-419f-ae6a-d9fe51e0c83c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2332386253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2332386253
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1495247092
Short name T579
Test name
Test status
Simulation time 7989875136 ps
CPU time 128.95 seconds
Started Aug 09 07:54:43 PM PDT 24
Finished Aug 09 07:56:52 PM PDT 24
Peak memory 256228 kb
Host smart-329e0005-2f28-4663-a67f-7f0676b7a09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495247092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1495247092
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2319207931
Short name T607
Test name
Test status
Simulation time 9318759891 ps
CPU time 27.12 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:55:08 PM PDT 24
Peak memory 216728 kb
Host smart-9ceb758a-c8a8-4dbe-83e2-d75e54f437c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319207931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2319207931
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1133891006
Short name T711
Test name
Test status
Simulation time 4445310503 ps
CPU time 7.53 seconds
Started Aug 09 07:54:37 PM PDT 24
Finished Aug 09 07:54:44 PM PDT 24
Peak memory 216724 kb
Host smart-3b1a5b0f-4125-47b8-babb-49ed72d2adfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133891006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1133891006
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.461706
Short name T779
Test name
Test status
Simulation time 37684111 ps
CPU time 0.68 seconds
Started Aug 09 07:54:44 PM PDT 24
Finished Aug 09 07:54:45 PM PDT 24
Peak memory 205976 kb
Host smart-ba48ef7d-918a-4919-984c-9d0c2857de6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.461706
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2972419502
Short name T387
Test name
Test status
Simulation time 76381975 ps
CPU time 0.72 seconds
Started Aug 09 07:54:41 PM PDT 24
Finished Aug 09 07:54:42 PM PDT 24
Peak memory 206636 kb
Host smart-352db70c-1461-4bbc-8313-c3258ffc3d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972419502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2972419502
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3006245504
Short name T415
Test name
Test status
Simulation time 8549266364 ps
CPU time 10.45 seconds
Started Aug 09 07:54:40 PM PDT 24
Finished Aug 09 07:54:51 PM PDT 24
Peak memory 233168 kb
Host smart-8eeaec45-6b06-4660-8a3c-60341c9d4e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006245504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3006245504
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%