Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2715450	1			T1	1		T2	315		T3	1
all_values[1]	2715450	1			T1	1		T2	315		T3	1
all_values[2]	2715450	1			T1	1		T2	315		T3	1
all_values[3]	2715450	1			T1	1		T2	315		T3	1
all_values[4]	2715450	1			T1	1		T2	315		T3	1
all_values[5]	2715450	1			T1	1		T2	315		T3	1
all_values[6]	2715450	1			T1	1		T2	315		T3	1
all_values[7]	2715450	1			T1	1		T2	315		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20479768

1

T1

8

T2

2520

T3

8

auto[1]

1243832

1

T33

30

T14

15

T15

80

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21698947

1

T1

8

T2

2520

T3

8

auto[1]

24653

1

T33

187

T34

111

T36

62

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2574156	1			T1	1		T2	315		T3	1
all_values[0]	auto[0]	auto[1]	11597	1			T33	85		T34	69		T36	35
all_values[0]	auto[1]	auto[0]	128978	1			T15	1		T17	4		T18	4
all_values[0]	auto[1]	auto[1]	719	1			T33	2		T15	9		T17	5
all_values[1]	auto[0]	auto[0]	2618107	1			T1	1		T2	315		T3	1
all_values[1]	auto[0]	auto[1]	6980	1			T33	65		T34	42		T36	27
all_values[1]	auto[1]	auto[0]	89957	1			T33	2		T14	5		T15	9
all_values[1]	auto[1]	auto[1]	406	1			T33	1		T15	2		T17	2
all_values[2]	auto[0]	auto[0]	2523535	1			T1	1		T2	315		T3	1
all_values[2]	auto[0]	auto[1]	2624	1			T33	16		T37	38		T14	104
all_values[2]	auto[1]	auto[0]	188889	1			T14	2		T15	5		T17	5
all_values[2]	auto[1]	auto[1]	402	1			T33	1		T14	2		T15	6
all_values[3]	auto[0]	auto[0]	2568000	1			T1	1		T2	315		T3	1
all_values[3]	auto[0]	auto[1]	195	1			T14	3		T15	3		T18	3
all_values[3]	auto[1]	auto[0]	147046	1			T33	1		T15	5		T17	5
all_values[3]	auto[1]	auto[1]	209	1			T33	1		T14	1		T15	7
all_values[4]	auto[0]	auto[0]	2627565	1			T1	1		T2	315		T3	1
all_values[4]	auto[0]	auto[1]	205	1			T33	1		T14	3		T17	3
all_values[4]	auto[1]	auto[0]	87485	1			T33	5		T14	1		T15	8
all_values[4]	auto[1]	auto[1]	195	1			T33	2		T15	3		T17	2
all_values[5]	auto[0]	auto[0]	2508937	1			T1	1		T2	315		T3	1
all_values[5]	auto[0]	auto[1]	170	1			T33	1		T14	1		T15	2
all_values[5]	auto[1]	auto[0]	206194	1			T33	5		T15	2		T17	1
all_values[5]	auto[1]	auto[1]	149	1			T33	2		T14	1		T15	5
all_values[6]	auto[0]	auto[0]	2544878	1			T1	1		T2	315		T3	1
all_values[6]	auto[0]	auto[1]	208	1			T33	5		T14	3		T15	5
all_values[6]	auto[1]	auto[0]	170169	1			T33	2		T15	2		T17	1
all_values[6]	auto[1]	auto[1]	195	1			T15	4		T17	1		T20	4
all_values[7]	auto[0]	auto[0]	2492439	1			T1	1		T2	315		T3	1
all_values[7]	auto[0]	auto[1]	172	1			T33	3		T14	1		T15	3
all_values[7]	auto[1]	auto[0]	222612	1			T33	4		T14	1		T15	9
all_values[7]	auto[1]	auto[1]	227	1			T33	2		T14	2		T15	3