Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34785	1			T2	46		T9	94		T10	6
auto[SpiFlashAddrCfg]	7346	1			T1	2		T2	24		T3	2
auto[SpiFlashAddr3b]	8728	1			T1	2		T2	38		T8	2
auto[SpiFlashAddr4b]	7400	1			T2	32		T9	48		T10	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34120

1

T1

4

T2

76

T3

2

auto[1]

24139

1

T2

64

T9

75

T10

22

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32051

1

T1

2

T2

77

T3

2

auto[1]

26208

1

T1

2

T2

63

T6

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39163	1			T2	57		T9	123		T10	2
values[1]	1027	1			T2	2		T9	4		T10	4
values[2]	1356	1			T2	10		T9	5		T10	4
values[3]	1462	1			T2	6		T9	14		T10	2
values[4]	1437	1			T2	6		T9	1		T12	2
values[5]	1374	1			T2	8		T9	6		T10	2
values[6]	1422	1			T2	4		T9	10		T33	13
values[7]	1358	1			T1	2		T2	9		T8	2
values[8]	9660	1			T1	2		T2	38		T3	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31518

1

T1

4

T2

140

T3

2

auto[1]

26741

1

T9

220

T34

388

T36

435

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55181

1

T1

4

T2

133

T3

2

write

3078

1

T2

7

T9

23

T33

15

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18773

1

T1

4

T2

84

T9

104

valids[0x1]

39486

1

T2

56

T3

2

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1479	1			T2	3		T9	10		T10	2
internal_process_ops[0x5a]	1486	1			T2	7		T8	2		T9	11
internal_process_ops[0x05]	21396	1			T2	2		T9	10		T12	2
internal_process_ops[0x35]	1501	1			T2	2		T9	8		T33	9
internal_process_ops[0x15]	1442	1			T2	5		T9	8		T46	2
internal_process_ops[0x03]	1056	1			T2	5		T9	3		T10	2
internal_process_ops[0x0b]	975	1			T2	6		T6	2		T9	2
internal_process_ops[0x3b]	1043	1			T1	2		T2	7		T3	2
internal_process_ops[0x6b]	1033	1			T2	2		T9	3		T12	2
internal_process_ops[0xbb]	1062	1			T2	3		T9	2		T10	4
internal_process_ops[0xeb]	1125	1			T1	2		T2	9		T9	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56729

1

T1

4

T2

138

T3

2

auto[1]

1530

1

T2

2

T9

8

T33

11

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55944

1

T1

4

T2

133

T3

2

auto[1]

2315

1

T2

7

T9

20

T33

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10886

1

T2

37

T12

2

T46

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6635

1

T2

9

T10

6

T13

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2009

1

T1

2

T2

7

T3

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1833

1

T2

15

T10

4

T13

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2517

1

T1

2

T2

16

T8

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2164

1

T2

21

T10

6

T13

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2056

1

T2

14

T12

4

T46

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1812

1

T2

14

T10

6

T13

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T14

2

T24

2

T15

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T33

2

T14

6

T25

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

81

1

T14

1

T50

1

T51

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

100

1

T33

1

T14

1

T49

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

128

1

T24

1

T25

1

T50

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

112

1

T2

1

T14

2

T25

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T2

1

T33

1

T14

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T33

2

T14

3

T25

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

92

1

T14

2

T164

3

T165

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

101

1

T33

1

T14

6

T24

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

100

1

T14

1

T25

1

T15

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

99

1

T2

1

T33

2

T25

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

105

1

T2

1

T33

2

T47

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T33

2

T50

1

T51

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

106

1

T2

3

T33

1

T14

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

87

1

T33

1

T14

2

T52

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10578

1

T9

67

T34

190

T36

183

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5901

1

T9

18

T34

39

T36

121

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1446

1

T9

18

T34

21

T36

12

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1263

1

T9

10

T34

16

T36

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1705

1

T9

30

T34

29

T36

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1630

1

T9

15

T34

30

T36

24

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1389

1

T9

18

T34

16

T36

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1357

1

T9

21

T34

27

T36

20

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

77

1

T9

6

T36

2

T14

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T34

2

T94

3

T166

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

98

1

T9

2

T37

1

T14

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

133

1

T9

1

T37

3

T14

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

94

1

T34

1

T36

2

T14

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

74

1

T34

1

T36

1

T37

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

96

1

T9

3

T36

6

T14

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

90

1

T9

1

T34

1

T167

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

78

1

T36

2

T14

4

T27

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

89

1

T9

1

T34

1

T36

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

81

1

T34

6

T36

3

T14

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

72

1

T168

2

T166

4

T169

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T9

2

T34

1

T14

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

103

1

T9

3

T34

1

T14

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

122

1

T9

2

T36

1

T14

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

78

1

T9

2

T34

6

T36

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3924	1			T2	28		T12	4		T33	49
auto[0]	values[0]	valids[0x1]	16487	1			T2	29		T10	2		T12	2
auto[0]	values[1]	valids[0x1]	573	1			T2	2		T10	4		T33	9
auto[0]	values[2]	valids[0x0]	502	1			T2	5		T10	4		T33	8
auto[0]	values[2]	valids[0x1]	275	1			T2	5		T33	2		T14	4
auto[0]	values[3]	valids[0x0]	570	1			T2	4		T10	2		T33	6
auto[0]	values[3]	valids[0x1]	256	1			T2	2		T33	2		T14	7
auto[0]	values[4]	valids[0x0]	519	1			T2	5		T12	2		T33	7
auto[0]	values[4]	valids[0x1]	335	1			T2	1		T13	8		T33	3
auto[0]	values[5]	valids[0x0]	528	1			T2	8		T10	2		T12	2
auto[0]	values[5]	valids[0x1]	288	1			T33	1		T14	6		T15	3
auto[0]	values[6]	valids[0x0]	509	1			T2	1		T33	10		T14	8
auto[0]	values[6]	valids[0x1]	292	1			T2	3		T33	3		T14	7
auto[0]	values[7]	valids[0x0]	497	1			T1	2		T2	5		T12	2
auto[0]	values[7]	valids[0x1]	338	1			T2	4		T8	2		T33	3
auto[0]	values[8]	valids[0x0]	3663	1			T1	2		T2	28		T10	4
auto[0]	values[8]	valids[0x1]	1962	1			T2	10		T3	2		T6	2
auto[1]	values[0]	valids[0x0]	3648	1			T9	53		T34	54		T36	57
auto[1]	values[0]	valids[0x1]	15104	1			T9	70		T34	198		T36	272
auto[1]	values[1]	valids[0x1]	454	1			T9	4		T34	9		T36	10
auto[1]	values[2]	valids[0x0]	340	1			T9	1		T34	2		T36	2
auto[1]	values[2]	valids[0x1]	239	1			T9	4		T34	5		T36	1
auto[1]	values[3]	valids[0x0]	374	1			T9	8		T34	13		T36	7
auto[1]	values[3]	valids[0x1]	262	1			T9	6		T34	11		T36	2
auto[1]	values[4]	valids[0x0]	332	1			T9	1		T34	1		T36	7
auto[1]	values[4]	valids[0x1]	251	1			T34	1		T36	5		T37	1
auto[1]	values[5]	valids[0x0]	344	1			T9	3		T34	4		T36	6
auto[1]	values[5]	valids[0x1]	214	1			T9	3		T34	6		T36	1
auto[1]	values[6]	valids[0x0]	396	1			T9	10		T34	7		T36	6
auto[1]	values[6]	valids[0x1]	225	1			T34	1		T36	3		T14	7
auto[1]	values[7]	valids[0x0]	285	1			T9	2		T34	3		T36	4
auto[1]	values[7]	valids[0x1]	238	1			T9	7		T34	4		T36	4
auto[1]	values[8]	valids[0x0]	2342	1			T9	26		T34	41		T36	26
auto[1]	values[8]	valids[0x1]	1693	1			T9	22		T34	28		T36	22