Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3323634

1

T1

522

T2

9756

T3

310

auto[1]

34890

1

T2

163

T9

145

T33

65

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018472

1

T1

522

T2

321

T3

310

auto[1]

2340052

1

T2

9598

T9

7406

T12

6

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	678431	1			T1	133		T2	2814		T3	307
auto[524288:1048575]	380504	1			T2	2962		T3	3		T6	1344
auto[1048576:1572863]	389700	1			T2	928		T6	1311		T9	84
auto[1572864:2097151]	385146	1			T2	24		T6	1		T9	1540
auto[2097152:2621439]	405738	1			T2	2		T9	215		T33	1701
auto[2621440:3145727]	352977	1			T1	7		T2	44		T6	529
auto[3145728:3670015]	379620	1			T1	139		T2	11		T9	20
auto[3670016:4194303]	386408	1			T1	243		T2	3134		T6	701

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2375422

1

T1

8

T2

9914

T3

4

auto[1]

983102

1

T1

514

T2

5

T3

306

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2894613

1

T1

522

T2

9907

T3

310

auto[1]

463911

1

T2

12

T9

3173

T33

2349

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	234168	1			T1	133		T2	66		T3	307
auto[0]	auto[0]	auto[0:524287]	auto[1]	375784	1			T2	2743		T9	1007		T12	6
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	86861	1			T2	42		T3	3		T6	1344
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	226105	1			T2	2916		T9	31		T33	5049
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	107121	1			T2	59		T6	1311		T9	28
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	216807	1			T2	866		T9	42		T33	1000
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	129605	1			T2	16		T6	1		T9	99
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	196493	1			T9	1374		T33	4770		T34	2469
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	116973	1			T2	2		T9	18		T33	8
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	227525	1			T9	57		T33	1692		T36	1399
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	94531	1			T1	7		T2	25		T6	529
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	205552	1			T9	1734		T34	2285		T36	2817
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	120180	1			T1	139		T2	11		T9	12
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	200324	1			T33	2938		T34	790		T36	385
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	113389	1			T1	243		T2	56		T6	701
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	213725	1			T2	2945		T9	1		T34	256
auto[0]	auto[1]	auto[0:524287]	auto[0]	1914	1			T9	2		T33	1		T34	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	59057	1			T36	1		T14	2029		T24	2938
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	527	1			T2	2		T9	21		T33	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	62583	1			T33	2328		T36	130		T37	2275
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1239	1			T9	6		T33	1		T34	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	61304	1			T34	131		T36	132		T14	11
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3712	1			T9	5		T33	4		T36	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51173	1			T36	887		T14	130		T184	2545
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	699	1			T9	8		T33	1		T34	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	56313	1			T9	128		T34	626		T36	4551
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	697	1			T2	7		T34	4		T48	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	49541	1			T34	935		T14	642		T50	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1502	1			T33	4		T48	7		T36	7
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	54070	1			T33	1		T36	259		T37	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1504	1			T9	26		T33	3		T34	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	52656	1			T9	2969		T33	1		T34	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	500	1			T2	5		T34	3		T36	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	5413	1			T34	14		T36	17		T37	17
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	365	1			T2	2		T9	3		T33	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3647	1			T33	10		T36	37		T14	73
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	361	1			T2	3		T33	2		T14	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2464	1			T33	18		T15	1		T50	30
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	402	1			T2	8		T9	17		T33	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2907	1			T9	45		T33	16		T34	15
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	436	1			T9	4		T50	6		T237	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3312	1			T50	11		T237	2		T167	9
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	309	1			T2	9		T9	40		T34	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1897	1			T34	30		T36	20		T14	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	378	1			T9	8		T33	4		T14	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2655	1			T33	7		T14	217		T25	14
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	427	1			T2	5		T9	5		T14	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3997	1			T2	128		T9	15		T14	23
auto[1]	auto[1]	auto[0:524287]	auto[0]	101	1			T36	1		T14	3		T24	8
auto[1]	auto[1]	auto[0:524287]	auto[1]	1494	1			T36	3		T14	9		T15	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	60	1			T36	2		T14	3		T27	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	356	1			T14	1		T27	2		T50	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	141	1			T9	5		T36	4		T14	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	263	1			T9	3		T36	32		T14	13
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	80	1			T14	2		T166	1		T19	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	774	1			T14	3		T197	8		T163	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	73	1			T36	3		T51	2		T195	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	407	1			T36	37		T51	2		T168	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	48	1			T2	3		T14	1		T50	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	402	1			T50	5		T51	8		T20	14
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	77	1			T33	1		T36	3		T14	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	434	1			T33	1		T36	9		T14	65
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	92	1			T33	1		T34	2		T14	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	618	1			T34	37		T14	9		T25	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1889898	1			T1	8		T2	9747		T3	4
auto[0]	auto[0]	auto[1]	975245	1			T1	514		T3	306		T6	5237
auto[0]	auto[1]	auto[0]	451314	1			T2	9		T9	3165		T33	2346
auto[0]	auto[1]	auto[1]	7177	1			T34	1		T36	7		T14	1
auto[1]	auto[0]	auto[0]	28908	1			T2	156		T9	123		T33	57
auto[1]	auto[0]	auto[1]	562	1			T2	4		T9	14		T33	5
auto[1]	auto[1]	auto[0]	5302	1			T2	2		T9	7		T33	3
auto[1]	auto[1]	auto[1]	118	1			T2	1		T9	1		T34	2