Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2715450	1			T1	1		T2	315		T3	1
all_pins[1]	2715450	1			T1	1		T2	315		T3	1
all_pins[2]	2715450	1			T1	1		T2	315		T3	1
all_pins[3]	2715450	1			T1	1		T2	315		T3	1
all_pins[4]	2715450	1			T1	1		T2	315		T3	1
all_pins[5]	2715450	1			T1	1		T2	315		T3	1
all_pins[6]	2715450	1			T1	1		T2	315		T3	1
all_pins[7]	2715450	1			T1	1		T2	315		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21549121	1			T1	8		T2	2520		T3	8
values[0x1]	174479	1			T33	11		T14	6		T15	39
transitions[0x0=>0x1]	172419	1			T33	9		T14	6		T15	26
transitions[0x1=>0x0]	172435	1			T33	9		T14	6		T15	26

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2714685	1			T1	1		T2	315		T3	1
all_pins[0]	values[0x1]	765	1			T33	2		T15	9		T17	5
all_pins[0]	transitions[0x0=>0x1]	479	1			T33	2		T15	9		T17	3
all_pins[0]	transitions[0x1=>0x0]	137	1			T33	1		T15	2		T19	1
all_pins[1]	values[0x0]	2715027	1			T1	1		T2	315		T3	1
all_pins[1]	values[0x1]	423	1			T33	1		T15	2		T17	2
all_pins[1]	transitions[0x0=>0x1]	337	1			T17	2		T18	1		T19	90
all_pins[1]	transitions[0x1=>0x0]	332	1			T14	2		T15	4		T17	3
all_pins[2]	values[0x0]	2715032	1			T1	1		T2	315		T3	1
all_pins[2]	values[0x1]	418	1			T33	1		T14	2		T15	6
all_pins[2]	transitions[0x0=>0x1]	361	1			T33	1		T14	2		T15	3
all_pins[2]	transitions[0x1=>0x0]	152	1			T33	1		T14	1		T15	4
all_pins[3]	values[0x0]	2715241	1			T1	1		T2	315		T3	1
all_pins[3]	values[0x1]	209	1			T33	1		T14	1		T15	7
all_pins[3]	transitions[0x0=>0x1]	159	1			T33	1		T14	1		T15	6
all_pins[3]	transitions[0x1=>0x0]	145	1			T33	2		T15	2		T17	1
all_pins[4]	values[0x0]	2715255	1			T1	1		T2	315		T3	1
all_pins[4]	values[0x1]	195	1			T33	2		T15	3		T17	2
all_pins[4]	transitions[0x0=>0x1]	153	1			T33	1		T15	2		T17	2
all_pins[4]	transitions[0x1=>0x0]	2228	1			T33	1		T14	1		T15	4
all_pins[5]	values[0x0]	2713180	1			T1	1		T2	315		T3	1
all_pins[5]	values[0x1]	2270	1			T33	2		T14	1		T15	5
all_pins[5]	transitions[0x0=>0x1]	854	1			T33	2		T14	1		T15	2
all_pins[5]	transitions[0x1=>0x0]	168556	1			T15	1		T20	4		T21	1718
all_pins[6]	values[0x0]	2545478	1			T1	1		T2	315		T3	1
all_pins[6]	values[0x1]	169972	1			T15	4		T17	1		T20	4
all_pins[6]	transitions[0x0=>0x1]	169910	1			T15	3		T20	3		T21	1719
all_pins[6]	transitions[0x1=>0x0]	165	1			T33	2		T14	2		T15	2
all_pins[7]	values[0x0]	2715223	1			T1	1		T2	315		T3	1
all_pins[7]	values[0x1]	227	1			T33	2		T14	2		T15	3
all_pins[7]	transitions[0x0=>0x1]	166	1			T33	2		T14	2		T15	1
all_pins[7]	transitions[0x1=>0x0]	720	1			T33	2		T15	7		T17	3