Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18300

1

T1

4

T2

76

T3

2

auto[1]

13218

1

T2

64

T10

22

T13

22

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3601	1			T8	2		T33	69		T25	50
values[1]	4004	1			T33	42		T14	92		T24	20
values[2]	3044	1			T2	20		T33	20		T14	22
values[3]	4961	1			T2	20		T6	2		T33	76
values[4]	4068	1			T1	4		T10	22		T13	22
values[5]	3633	1			T2	40		T3	2		T33	37
values[6]	3890	1			T2	40		T12	16		T33	27
values[7]	4317	1			T2	20		T14	45		T25	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4045	1			T2	20		T33	37		T14	86
values[1]	3453	1			T2	40		T162	4		T24	20
values[2]	4525	1			T2	20		T10	22		T33	113
values[3]	3596	1			T1	4		T3	2		T13	22
values[4]	4257	1			T12	16		T33	20		T48	22
values[5]	4060	1			T33	23		T67	8		T14	21
values[6]	3702	1			T2	20		T8	2		T33	99
values[7]	3880	1			T2	40		T6	2		T46	18

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	365	1			T25	7		T51	31		T163	14
auto[0]	values[0]	values[1]	214	1			T195	16		T86	42		T156	6
auto[0]	values[0]	values[2]	337	1			T25	9		T15	13		T165	6
auto[0]	values[0]	values[3]	308	1			T190	90		T214	13		T196	18
auto[0]	values[0]	values[4]	316	1			T195	6		T194	13		T238	10
auto[0]	values[0]	values[5]	181	1			T184	15		T19	8		T193	10
auto[0]	values[0]	values[6]	235	1			T8	2		T33	31		T184	8
auto[0]	values[0]	values[7]	313	1			T33	11		T51	13		T19	11
auto[0]	values[1]	values[0]	287	1			T14	9		T25	21		T18	16
auto[0]	values[1]	values[1]	149	1			T24	10		T50	9		T198	17
auto[0]	values[1]	values[2]	319	1			T33	17		T14	34		T198	30
auto[0]	values[1]	values[3]	304	1			T190	6		T41	65		T239	12
auto[0]	values[1]	values[4]	462	1			T50	12		T198	13		T19	21
auto[0]	values[1]	values[5]	393	1			T25	11		T50	20		T52	17
auto[0]	values[1]	values[6]	218	1			T18	26		T240	7		T41	12
auto[0]	values[1]	values[7]	188	1			T50	58		T184	6		T241	4
auto[0]	values[2]	values[0]	270	1			T23	16		T242	14		T243	2
auto[0]	values[2]	values[1]	312	1			T2	17		T25	8		T51	4
auto[0]	values[2]	values[2]	215	1			T25	9		T164	16		T244	8
auto[0]	values[2]	values[3]	95	1			T185	10		T156	6		T202	14
auto[0]	values[2]	values[4]	194	1			T33	13		T15	14		T184	37
auto[0]	values[2]	values[5]	192	1			T197	23		T183	10		T83	10
auto[0]	values[2]	values[6]	292	1			T14	12		T245	6		T156	40
auto[0]	values[2]	values[7]	214	1			T15	19		T195	15		T18	11
auto[0]	values[3]	values[0]	270	1			T14	29		T96	16		T191	10
auto[0]	values[3]	values[1]	294	1			T162	4		T191	10		T197	22
auto[0]	values[3]	values[2]	311	1			T33	9		T14	12		T246	6
auto[0]	values[3]	values[3]	608	1			T15	12		T18	14		T203	18
auto[0]	values[3]	values[4]	317	1			T48	22		T14	12		T247	2
auto[0]	values[3]	values[5]	243	1			T33	13		T67	8		T25	11
auto[0]	values[3]	values[6]	275	1			T14	13		T184	17		T209	10
auto[0]	values[3]	values[7]	479	1			T2	8		T6	2		T33	24
auto[0]	values[4]	values[0]	223	1			T24	11		T248	4		T51	16
auto[0]	values[4]	values[1]	226	1			T25	12		T51	7		T249	8
auto[0]	values[4]	values[2]	421	1			T33	19		T14	16		T250	2
auto[0]	values[4]	values[3]	109	1			T1	4		T198	10		T194	11
auto[0]	values[4]	values[4]	311	1			T14	33		T19	15		T191	33
auto[0]	values[4]	values[5]	273	1			T198	12		T21	12		T83	8
auto[0]	values[4]	values[6]	311	1			T33	13		T14	17		T225	18
auto[0]	values[4]	values[7]	395	1			T46	18		T14	28		T51	6
auto[0]	values[5]	values[0]	480	1			T33	27		T14	13		T191	12
auto[0]	values[5]	values[1]	204	1			T50	64		T20	1		T197	18
auto[0]	values[5]	values[2]	305	1			T2	11		T14	26		T184	7
auto[0]	values[5]	values[3]	315	1			T3	2		T25	10		T51	11
auto[0]	values[5]	values[4]	283	1			T194	14		T251	2		T252	9
auto[0]	values[5]	values[5]	164	1			T20	12		T253	10		T191	11
auto[0]	values[5]	values[6]	197	1			T14	18		T29	8		T16	13
auto[0]	values[5]	values[7]	224	1			T2	13		T50	12		T191	24
auto[0]	values[6]	values[0]	178	1			T207	13		T224	11		T254	2
auto[0]	values[6]	values[1]	194	1			T2	13		T255	10		T193	12
auto[0]	values[6]	values[2]	230	1			T14	11		T52	8		T198	16
auto[0]	values[6]	values[3]	177	1			T14	21		T198	13		T18	15
auto[0]	values[6]	values[4]	292	1			T12	16		T47	2		T15	18
auto[0]	values[6]	values[5]	395	1			T14	12		T25	9		T93	12
auto[0]	values[6]	values[6]	364	1			T2	7		T33	22		T197	9
auto[0]	values[6]	values[7]	398	1			T52	15		T195	7		T198	20
auto[0]	values[7]	values[0]	324	1			T2	7		T19	12		T197	9
auto[0]	values[7]	values[1]	131	1			T184	15		T256	6		T257	10
auto[0]	values[7]	values[2]	600	1			T14	16		T50	42		T258	8
auto[0]	values[7]	values[3]	190	1			T52	15		T236	14		T86	8
auto[0]	values[7]	values[4]	466	1			T14	9		T195	12		T20	14
auto[0]	values[7]	values[5]	314	1			T15	16		T217	8		T51	26
auto[0]	values[7]	values[6]	266	1			T25	12		T199	16		T19	15
auto[0]	values[7]	values[7]	170	1			T16	13		T216	15		T135	8
auto[1]	values[0]	values[0]	207	1			T25	23		T51	12		T163	6
auto[1]	values[0]	values[1]	100	1			T195	4		T86	11		T156	15
auto[1]	values[0]	values[2]	143	1			T25	11		T15	8		T195	7
auto[1]	values[0]	values[3]	159	1			T190	9		T214	7		T135	5
auto[1]	values[0]	values[4]	171	1			T195	14		T194	7		T257	5
auto[1]	values[0]	values[5]	168	1			T184	5		T19	13		T229	16
auto[1]	values[0]	values[6]	193	1			T33	18		T184	12		T19	4
auto[1]	values[0]	values[7]	191	1			T33	9		T51	7		T19	9
auto[1]	values[1]	values[0]	179	1			T14	13		T25	4		T18	5
auto[1]	values[1]	values[1]	141	1			T24	10		T50	13		T198	8
auto[1]	values[1]	values[2]	254	1			T33	25		T14	36		T198	2
auto[1]	values[1]	values[3]	191	1			T259	10		T190	70		T41	9
auto[1]	values[1]	values[4]	352	1			T50	10		T198	8		T19	35
auto[1]	values[1]	values[5]	328	1			T25	27		T50	4		T52	9
auto[1]	values[1]	values[6]	144	1			T18	4		T240	13		T41	8
auto[1]	values[1]	values[7]	95	1			T49	16		T50	9		T184	14
auto[1]	values[2]	values[0]	104	1			T190	8		T260	12		T239	10
auto[1]	values[2]	values[1]	333	1			T2	3		T25	16		T51	61
auto[1]	values[2]	values[2]	156	1			T25	11		T164	4		T216	9
auto[1]	values[2]	values[3]	56	1			T156	22		T202	6		T261	6
auto[1]	values[2]	values[4]	110	1			T33	7		T15	8		T184	9
auto[1]	values[2]	values[5]	107	1			T197	10		T183	10		T83	21
auto[1]	values[2]	values[6]	121	1			T14	10		T262	14		T156	8
auto[1]	values[2]	values[7]	273	1			T15	7		T195	5		T18	10
auto[1]	values[3]	values[0]	160	1			T14	15		T191	38		T86	10
auto[1]	values[3]	values[1]	436	1			T191	10		T197	11		T163	38
auto[1]	values[3]	values[2]	297	1			T33	11		T14	24		T50	8
auto[1]	values[3]	values[3]	304	1			T15	14		T18	10		T257	42
auto[1]	values[3]	values[4]	203	1			T14	8		T51	11		T263	6
auto[1]	values[3]	values[5]	262	1			T33	10		T25	9		T52	7
auto[1]	values[3]	values[6]	360	1			T14	7		T184	3		T16	1
auto[1]	values[3]	values[7]	142	1			T2	12		T33	9		T50	14
auto[1]	values[4]	values[0]	146	1			T24	9		T51	4		T18	7
auto[1]	values[4]	values[1]	165	1			T25	12		T51	13		T197	11
auto[1]	values[4]	values[2]	282	1			T10	22		T33	32		T14	8
auto[1]	values[4]	values[3]	225	1			T13	22		T198	10		T194	9
auto[1]	values[4]	values[4]	153	1			T14	10		T19	9		T191	18
auto[1]	values[4]	values[5]	290	1			T198	10		T21	10		T83	12
auto[1]	values[4]	values[6]	325	1			T33	10		T14	10		T191	24
auto[1]	values[4]	values[7]	213	1			T14	19		T51	14		T184	11
auto[1]	values[5]	values[0]	335	1			T33	10		T14	7		T191	50
auto[1]	values[5]	values[1]	201	1			T50	28		T20	73		T197	14
auto[1]	values[5]	values[2]	243	1			T2	9		T14	20		T184	26
auto[1]	values[5]	values[3]	236	1			T25	18		T51	16		T198	13
auto[1]	values[5]	values[4]	106	1			T194	14		T252	11		T216	4
auto[1]	values[5]	values[5]	158	1			T20	8		T191	9		T86	20
auto[1]	values[5]	values[6]	87	1			T14	2		T16	7		T198	7
auto[1]	values[5]	values[7]	95	1			T2	7		T50	11		T191	4
auto[1]	values[6]	values[0]	144	1			T233	4		T207	7		T224	9
auto[1]	values[6]	values[1]	140	1			T2	7		T193	8		T264	12
auto[1]	values[6]	values[2]	167	1			T14	12		T265	8		T52	20
auto[1]	values[6]	values[3]	97	1			T14	19		T198	7		T18	5
auto[1]	values[6]	values[4]	347	1			T15	6		T195	7		T266	6
auto[1]	values[6]	values[5]	371	1			T14	9		T25	11		T184	6
auto[1]	values[6]	values[6]	158	1			T2	13		T33	5		T197	24
auto[1]	values[6]	values[7]	238	1			T52	6		T195	13		T183	15
auto[1]	values[7]	values[0]	373	1			T2	13		T19	8		T197	11
auto[1]	values[7]	values[1]	213	1			T184	27		T257	10		T267	66
auto[1]	values[7]	values[2]	245	1			T14	9		T50	34		T86	20
auto[1]	values[7]	values[3]	222	1			T52	7		T86	13		T257	45
auto[1]	values[7]	values[4]	174	1			T14	11		T195	8		T20	36
auto[1]	values[7]	values[5]	221	1			T15	5		T51	7		T19	9
auto[1]	values[7]	values[6]	156	1			T25	8		T19	7		T191	5
auto[1]	values[7]	values[7]	252	1			T16	63		T268	2		T216	5