Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	411	1			T1	2		T2	1		T6	2
auto[ReadAddrCrossIntoMailbox]	304	1			T2	2		T33	5		T14	8
auto[ReadAddrCrossOutOfMailbox]	286	1			T33	4		T14	3		T25	3
auto[ReadAddrCrossAllMailbox]	214	1			T1	2		T2	1		T33	3
auto[ReadAddrOutsideMailbox]	3618	1			T2	28		T10	8		T12	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2399

1

T1

2

T2

21

T6

1

auto[1]

2434

1

T1

2

T2

11

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	793	1			T2	5		T10	2		T13	2
read_ops[0x0b]	741	1			T2	6		T6	2		T10	2
read_ops[0x3b]	836	1			T1	2		T2	7		T13	2
read_ops[0x6b]	805	1			T2	2		T12	2		T13	2
read_ops[0xbb]	803	1			T2	3		T10	4		T12	2
read_ops[0xeb]	855	1			T1	2		T2	9		T46	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T2	1		T14	1		T25	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T14	2		T25	1		T51	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T14	2		T25	1		T164	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T33	1		T25	1		T51	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T25	3		T18	1		T19	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T51	1		T198	2		T156	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T2	1		T197	1		T83	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T14	2		T20	1		T183	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T2	3		T10	1		T13	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T10	1		T13	1		T33	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T6	1		T14	1		T50	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T6	1		T14	2		T51	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T33	1		T14	1		T51	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T14	1		T15	1		T19	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T198	1		T194	1		T86	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T33	2		T50	1		T220	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T14	2		T248	1		T163	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T248	1		T191	1		T197	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	259	1			T2	5		T10	1		T33	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T2	1		T10	1		T33	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T14	1		T24	1		T25	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T50	1		T18	1		T19	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T2	1		T198	2		T244	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T25	1		T52	1		T244	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T14	1		T51	1		T183	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T33	1		T50	1		T51	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T1	1		T184	1		T244	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T1	1		T14	1		T50	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T13	1		T33	10		T14	8
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T2	6		T13	1		T33	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T24	1		T50	1		T51	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T33	1		T15	1		T195	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T14	1		T25	1		T51	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T14	1		T51	1		T234	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T51	1		T198	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T195	1		T198	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T33	1		T14	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T14	1		T15	1		T198	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T2	1		T12	1		T13	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T2	1		T12	1		T13	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T33	1		T248	1		T50	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T14	1		T248	1		T50	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T2	1		T33	1		T24	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T33	2		T14	1		T51	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T51	1		T234	1		T198	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T234	1		T191	2		T163	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T33	1		T14	2		T24	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T33	1		T51	2		T198	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T2	2		T10	2		T12	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T10	2		T12	1		T13	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T1	1		T191	1		T156	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T1	1		T33	1		T51	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T184	1		T234	2		T198	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T14	1		T25	1		T50	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T14	1		T198	2		T18	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T33	1		T14	1		T51	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T14	1		T51	1		T184	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T184	1		T234	1		T198	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	332	1			T2	6		T46	3		T33	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T2	3		T46	3		T33	1