Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4718	1			T2	20		T33	127		T14	66
values[1]	3694	1			T2	20		T33	43		T14	65
values[2]	3351	1			T1	4		T6	2		T33	47
values[3]	4038	1			T2	40		T8	2		T33	20
values[4]	4076	1			T12	16		T13	22		T33	22
values[5]	4614	1			T3	2		T10	22		T46	18
values[6]	3290	1			T2	40		T33	31		T67	8
values[7]	3737	1			T2	20		T33	33		T14	60

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3649	1			T2	20		T8	2		T14	43
values[1]	4058	1			T2	20		T3	2		T10	22
values[2]	3505	1			T33	27		T47	2		T14	41
values[3]	3458	1			T33	47		T14	112		T25	38
values[4]	4788	1			T33	20		T14	91		T25	20
values[5]	4227	1			T1	4		T6	2		T13	22
values[6]	4173	1			T2	60		T33	84		T14	110
values[7]	3660	1			T2	40		T46	18		T33	22

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30721

1

T1

4

T2

138

T3

2

auto[1]

797

1

T2

2

T33

11

T14

20

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	307	1			T2	20		T14	22		T165	6
auto[0]	values[0]	values[1]	550	1			T33	42		T195	35		T269	23
auto[0]	values[0]	values[2]	486	1			T50	28		T51	43		T197	156
auto[0]	values[0]	values[3]	631	1			T33	47		T14	42		T50	20
auto[0]	values[0]	values[4]	815	1			T199	16		T51	62		T16	117
auto[0]	values[0]	values[5]	1003	1			T33	35		T15	20		T195	20
auto[0]	values[0]	values[6]	469	1			T25	20		T248	4		T52	22
auto[0]	values[0]	values[7]	348	1			T50	22		T184	20		T135	44
auto[0]	values[1]	values[0]	624	1			T236	14		T198	20		T197	29
auto[0]	values[1]	values[1]	448	1			T2	19		T33	23		T14	20
auto[0]	values[1]	values[2]	315	1			T15	24		T93	12		T198	21
auto[0]	values[1]	values[3]	437	1			T198	19		T19	32		T191	26
auto[0]	values[1]	values[4]	431	1			T33	19		T50	25		T208	20
auto[0]	values[1]	values[5]	443	1			T14	22		T233	4		T50	78
auto[0]	values[1]	values[6]	440	1			T14	20		T15	26		T190	150
auto[0]	values[1]	values[7]	462	1			T195	20		T83	31		T216	20
auto[0]	values[2]	values[0]	350	1			T15	21		T263	6		T191	25
auto[0]	values[2]	values[1]	391	1			T162	4		T14	22		T198	45
auto[0]	values[2]	values[2]	510	1			T33	26		T25	27		T16	66
auto[0]	values[2]	values[3]	399	1			T49	12		T50	59		T198	19
auto[0]	values[2]	values[4]	294	1			T14	23		T25	19		T50	22
auto[0]	values[2]	values[5]	397	1			T1	4		T6	2		T19	28
auto[0]	values[2]	values[6]	386	1			T33	20		T29	8		T198	20
auto[0]	values[2]	values[7]	522	1			T198	31		T197	33		T270	4
auto[0]	values[3]	values[0]	362	1			T8	2		T191	19		T271	18
auto[0]	values[3]	values[1]	241	1			T33	19		T48	22		T234	14
auto[0]	values[3]	values[2]	443	1			T14	20		T15	21		T197	31
auto[0]	values[3]	values[3]	437	1			T14	24		T25	35		T269	21
auto[0]	values[3]	values[4]	627	1			T52	20		T272	2		T188	123
auto[0]	values[3]	values[5]	663	1			T14	22		T16	20		T191	88
auto[0]	values[3]	values[6]	804	1			T2	39		T20	35		T163	20
auto[0]	values[3]	values[7]	350	1			T25	19		T20	49		T273	10
auto[0]	values[4]	values[0]	509	1			T14	20		T245	6		T250	2
auto[0]	values[4]	values[1]	890	1			T12	16		T33	22		T25	20
auto[0]	values[4]	values[2]	506	1			T47	2		T164	20		T265	8
auto[0]	values[4]	values[3]	411	1			T184	20		T86	30		T238	10
auto[0]	values[4]	values[4]	572	1			T50	24		T198	21		T197	20
auto[0]	values[4]	values[5]	406	1			T13	22		T14	35		T23	16
auto[0]	values[4]	values[6]	371	1			T184	20		T191	37		T228	30
auto[0]	values[4]	values[7]	327	1			T80	2		T157	23		T274	14
auto[0]	values[5]	values[0]	280	1			T16	75		T194	23		T214	18
auto[0]	values[5]	values[1]	726	1			T3	2		T10	22		T163	89
auto[0]	values[5]	values[2]	520	1			T191	20		T275	4		T193	20
auto[0]	values[5]	values[3]	557	1			T14	23		T51	27		T18	20
auto[0]	values[5]	values[4]	789	1			T14	62		T258	8		T225	18
auto[0]	values[5]	values[5]	536	1			T19	43		T191	37		T216	14
auto[0]	values[5]	values[6]	496	1			T14	46		T51	20		T184	43
auto[0]	values[5]	values[7]	598	1			T46	18		T33	19		T24	18
auto[0]	values[6]	values[0]	549	1			T163	22		T192	16		T157	19
auto[0]	values[6]	values[1]	459	1			T67	8		T15	21		T52	20
auto[0]	values[6]	values[2]	255	1			T184	20		T268	2		T207	18
auto[0]	values[6]	values[3]	151	1			T14	19		T209	10		T222	4
auto[0]	values[6]	values[4]	393	1			T198	20		T18	20		T85	14
auto[0]	values[6]	values[5]	424	1			T52	26		T253	10		T212	6
auto[0]	values[6]	values[6]	586	1			T2	20		T33	29		T14	42
auto[0]	values[6]	values[7]	370	1			T2	20		T14	27		T24	20
auto[0]	values[7]	values[0]	580	1			T247	2		T232	14		T195	19
auto[0]	values[7]	values[1]	263	1			T51	40		T19	23		T86	26
auto[0]	values[7]	values[2]	381	1			T14	20		T51	20		T194	20
auto[0]	values[7]	values[3]	328	1			T184	32		T19	24		T276	4
auto[0]	values[7]	values[4]	732	1			T184	39		T16	26		T19	33
auto[0]	values[7]	values[5]	252	1			T14	20		T191	43		T277	20
auto[0]	values[7]	values[6]	518	1			T33	33		T25	46		T195	20
auto[0]	values[7]	values[7]	601	1			T2	20		T14	19		T25	27
auto[1]	values[0]	values[0]	8	1			T14	1		T184	2		T257	1
auto[1]	values[0]	values[1]	20	1			T33	1		T195	5		T269	1
auto[1]	values[0]	values[2]	10	1			T197	3		T227	3		T278	2
auto[1]	values[0]	values[3]	15	1			T14	1		T20	2		T194	6
auto[1]	values[0]	values[4]	16	1			T51	3		T16	5		T190	3
auto[1]	values[0]	values[5]	17	1			T33	2		T15	2		T189	4
auto[1]	values[0]	values[6]	10	1			T52	6		T279	2		T280	1
auto[1]	values[0]	values[7]	13	1			T50	3		T189	2		T235	2
auto[1]	values[1]	values[0]	17	1			T163	1		T216	2		T129	1
auto[1]	values[1]	values[1]	8	1			T2	1		T156	2		T214	4
auto[1]	values[1]	values[2]	9	1			T15	2		T198	1		T281	1
auto[1]	values[1]	values[3]	13	1			T198	1		T191	2		T194	1
auto[1]	values[1]	values[4]	11	1			T33	1		T50	1		T156	1
auto[1]	values[1]	values[5]	13	1			T14	3		T50	2		T51	2
auto[1]	values[1]	values[6]	13	1			T190	1		T282	5		T283	4
auto[1]	values[1]	values[7]	10	1			T41	1		T284	3		T285	2
auto[1]	values[2]	values[0]	16	1			T188	3		T286	1		T287	3
auto[1]	values[2]	values[1]	8	1			T14	1		T224	3		T288	2
auto[1]	values[2]	values[2]	11	1			T33	1		T25	3		T16	1
auto[1]	values[2]	values[3]	21	1			T49	4		T50	6		T198	1
auto[1]	values[2]	values[4]	20	1			T14	2		T25	1		T50	1
auto[1]	values[2]	values[5]	11	1			T191	3		T289	1		T290	1
auto[1]	values[2]	values[6]	10	1			T19	2		T135	1		T291	1
auto[1]	values[2]	values[7]	5	1			T198	1		T292	1		T290	1
auto[1]	values[3]	values[0]	3	1			T191	1		T210	2		-	-
auto[1]	values[3]	values[1]	8	1			T33	1		T183	1		T257	1
auto[1]	values[3]	values[2]	16	1			T14	1		T15	3		T197	2
auto[1]	values[3]	values[3]	20	1			T25	3		T190	1		T214	2
auto[1]	values[3]	values[4]	20	1			T52	2		T188	4		T286	1
auto[1]	values[3]	values[5]	17	1			T191	3		T41	3		T202	1
auto[1]	values[3]	values[6]	24	1			T2	1		T260	2		T267	1
auto[1]	values[3]	values[7]	3	1			T25	1		T20	1		T286	1
auto[1]	values[4]	values[0]	7	1			T198	1		T197	1		T83	1
auto[1]	values[4]	values[1]	22	1			T293	2		T156	1		T216	2
auto[1]	values[4]	values[2]	9	1			T197	1		T190	2		T207	1
auto[1]	values[4]	values[3]	13	1			T135	2		T294	2		T142	2
auto[1]	values[4]	values[4]	12	1			T163	1		T239	2		T207	2
auto[1]	values[4]	values[5]	8	1			T14	1		T267	2		T295	2
auto[1]	values[4]	values[6]	7	1			T228	1		T287	1		T282	2
auto[1]	values[4]	values[7]	6	1			T187	1		T279	1		T296	2
auto[1]	values[5]	values[0]	11	1			T16	1		T214	2		T287	4
auto[1]	values[5]	values[1]	15	1			T156	1		T285	1		T297	4
auto[1]	values[5]	values[2]	7	1			T239	1		T188	1		T296	1
auto[1]	values[5]	values[3]	10	1			T20	2		T207	3		T235	1
auto[1]	values[5]	values[4]	16	1			T14	4		T129	1		T188	1
auto[1]	values[5]	values[5]	22	1			T19	3		T216	6		T257	1
auto[1]	values[5]	values[6]	13	1			T184	3		T20	2		T207	1
auto[1]	values[5]	values[7]	18	1			T33	3		T24	2		T183	2
auto[1]	values[6]	values[0]	15	1			T163	3		T157	1		T216	2
auto[1]	values[6]	values[1]	6	1			T279	1		T261	3		T298	1
auto[1]	values[6]	values[2]	13	1			T207	2		T297	1		T280	3
auto[1]	values[6]	values[3]	7	1			T14	3		T227	3		T261	1
auto[1]	values[6]	values[4]	25	1			T85	2		T86	1		T299	1
auto[1]	values[6]	values[5]	13	1			T190	2		T41	5		T300	1
auto[1]	values[6]	values[6]	16	1			T33	2		T14	2		T25	1
auto[1]	values[6]	values[7]	8	1			T83	2		T299	2		T279	1
auto[1]	values[7]	values[0]	11	1			T195	1		T197	1		T183	3
auto[1]	values[7]	values[1]	3	1			T19	1		T281	1		T301	1
auto[1]	values[7]	values[2]	14	1			T83	2		T135	3		T201	2
auto[1]	values[7]	values[3]	8	1			T184	1		T216	2		T257	2
auto[1]	values[7]	values[4]	15	1			T184	3		T235	4		T302	1
auto[1]	values[7]	values[5]	2	1			T191	1		T54	1		-	-
auto[1]	values[7]	values[6]	10	1			T25	3		T198	1		T19	1
auto[1]	values[7]	values[7]	19	1			T14	1		T25	1		T18	4